System and method for repairing memory in chip

Abstract

The invention provides an in-chip memory restoration system and method, the system comprises an in-chip BIST logic and BIST controller, an in-chip BISR logic and BISR controller, an in-chip TAP controller and an in-chip memory restoration controller, and further comprises an external nonvolatile storage medium, the external nonvolatile storage medium and the in-chip memory restoration controller are provided with an access interface C17, and the access interface C17 is connected with the external nonvolatile storage medium. And the access interface C17 is used for recording the memory repair information stored in the memory recovery controller in the chip to an external nonvolatile storage medium or loading the memory repair information in the external nonvolatile storage medium to the memory recovery controller in the chip. According to the technical scheme, it is guaranteed that the memory can be repaired on the board level from the system, the efuse burning time for testing and repairing the memory on the ATE is saved, and efuse resources in a chip are saved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor storage technology, and in particular, relates to a system and method for repairing memory within a chip. Background Art

[0002] With the continuous development of chip technology and the continuous improvement of chip complexity, the probability of chip defects or failures has also increased. Among them, the memory that occupies the largest chip area, including RAM and ROM, has a huge impact on the operation of the chip if it fails or fails. It is inevitable that there may be some memory defects in the chip production process. How to continue to use these defective chips and maximize the chip yield is an urgent problem to be solved.

[0003] The related on-chip memory repair methods are mainly based on the BIST logic test designed in the chip to find memory defects, and design redundant BISR repair logic to repair them. However, this method has some shortcomings: first, it takes up expensive ATE test time; second, the method of using efuse to record repair information is one-time and irreversible, so it is not flexible enough when multiple modifications or repairs are required; third, it cannot be repaired in actual system use.

[0004] Therefore, it is necessary to provide a memory repair system and method with higher efficiency and flexibility to meet the actual use requirements of the chip in the system. Summary of the invention

[0005] The purpose of this application is to provide a system and method for repairing memory in a chip, aiming to ensure that memory repair can be performed at the board level from a system perspective, save the efuse burning time of testing and repairing memory on ATE, and save efuse resources in the chip.

[0006] The first aspect of the present application proposes an in-chip memory repair system, including an in-chip TAP (Test Access Port, test access interface) controller, an in-chip BIST logic, an in-chip BISR logic and BISR controller, an in-chip storage recovery controller, and an external non-volatile storage medium. The external non-volatile storage medium and the in-chip storage recovery controller have an access interface C17. The access interface C17 is used to record the memory repair information stored in the in-chip storage recovery controller to the external non-volatile storage medium or load the memory repair information in the external non-volatile storage medium into the in-chip storage recovery controller.

[0007] In an optional implementation, an external non-volatile storage medium update tool is further included, and the external non-volatile storage medium update tool has an access interface C23 for updating the external non-volatile storage medium.

[0008] In an optional implementation, the TAP controller is logically connected to the BIST via a BIST control interface C3, a first MUX (Multiplexer) is provided between the TAP controller and the on-chip storage recovery controller, and the TAP controller is connected to the first MUX via a repair information transmission interface C13.1.

[0009] In an optional embodiment, the BISR controller is connected to a single BISR logic through a BISR configuration interface C21, and the single BISR logic is connected to different ROM entities C11.1, C11.2...C11.m in the chip through access buses C9.1, C9.2...C9.m, and is connected to different RAM entities C12.1, C12.2...C12.n in the chip through access buses C10.1, C10.2...C10.n.

[0010] In an optional implementation, the BISR controller is connected to a plurality of BISR logics via a BISR configuration interface, and the plurality of BISR logics are respectively connected to a ROM entity or a RAM entity within the chip.

[0011] In an optional embodiment, there are one or more second MUXs between the BIST logic and the single or multiple BISR logics, and the one or more second MUXs are connected to the BIST logic through the memory test access interface C5.0, and the second MUX is connected to the single or multiple BISR logics through the memory access interface C7.

[0012] In an optional implementation, the on-chip storage recovery controller is connected to the BISR controller via a repair information transmission interface C19.

[0013] In an optional implementation manner, the second-MUX has a main function access interface C5.1 of the memory.

[0014] In an optional implementation, the BIST logic is connected to the on-chip storage recovery controller via a repair information transmission interface C13.0.

[0015] In an optional embodiment, the TAP controller has a test interface C1, and the test interface C1 is used to provide test control and comparison information of ROM content.

[0016] A second aspect of the present application provides a method for repairing memory in a chip, comprising the following steps:

[0017] Perform a boot test, provide test control and ROM content comparison information to the memory through the test interface of the TAP controller, and test the memory through the BIST logic;

[0018] If a memory defect is found during the test, the memory repair information is transmitted to the on-chip storage recovery controller, and the on-chip storage recovery controller records the memory repair information to an external non-volatile medium; or,

[0019] Without performing a startup test, the external non-volatile storage medium is directly updated through the external non-volatile storage medium update tool;

[0020] When the chip starts, the storage recovery controller in the chip loads the repair information of the memory in the external non-volatile medium, and repairs the specified location on the memory through the BISR repair logic.

[0021] In an optional implementation, the BISR repair logic controls or repairs all ROM or RAM entities of the memory.

[0022] In an optional implementation, the BISR repair logic controls or repairs each ROM or RAM entity of the memory separately.

[0023] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0024] 1. This application uses the chip board-level platform and the customization and redundant design in the chip to repair the memory in the chip. The board-level design can be compatible with the previous design, keeping the BOM cost (Bill of Materials, the cost of various raw materials, parts, tools and labor required in the product manufacturing process, mainly referring to the board-level raw material cost) unchanged;

[0025] 2. This application changes the memory testing and repair update method from the ATE testing process to the board-level SLT testing process or the board-level mass production burning process, saving expensive ATE testing time;

[0026] 3. This application saves the efuse overhead required for recording memory repair information in the chip;

[0027] 4. Since the repair information is recorded in an external non-volatile storage medium, and this part of the repair information is a dynamic configuration for the BISR repair logic in the chip, this application can be re-modified and updated multiple times;

[0028] 5. Repair information can be updated repeatedly at different locations or the same location for multiple times. In particular, the modification of ROM content is not limited to repair. When it is found that the ROM content (for example, if some important parameters are placed in the ROM) needs to be updated, the same location or different locations of the ROM can be modified multiple times as needed and reused repeatedly to improve chip utilization and yield;

[0029] 6. This application provides multiple repairs throughout the life cycle of the chip, as long as redundancy allows;

[0030] 7. When redundancy is exhausted, the present application can adjust the priority and repair strategy according to the importance of different locations of different memories that need to be repaired, maximize the use of the memory within the chip, and ensure that the most important functions in the chip can operate normally through differentiated repair strategies.

[0031] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 is a schematic diagram of a centrally controlled memory repair system according to an exemplary embodiment of the present application.

[0034] Figure 2 is a schematic diagram of a memory repair system with separate control according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] With the continuous development of chip technology and the continuous improvement of chip complexity, the probability of chip defects or failures has also increased. Among them, memory occupies the largest area of ​​the chip. The memory in the chip generally includes RAM (Random Access Memory) and ROM (Read Only Memory). Since the program or data when the chip is working comes from the memory inside the chip, memory defects or failures have a huge impact on the work of the chip. In addition, as an unavoidable process in chip production, it is inevitable that there may be some memory defects introduced in the production process. How to continue to use these defective chips and maximize the yield of the chip? Redundant design is generally considered at the beginning of chip design, so that the chip can repair the memory during shipment and use. In fact, memory repair has become an indispensable technical means in the process of chip development and manufacturing.

[0037] At present, the related methods of chip memory repair are mainly based on the BIST (Buildin Self Test, built-in self-test logic developed in the chip) logic test designed in the chip to find memory defects, and design redundant BISR repair logic (Buildin Self Repair, built-in self-repair logic developed in the chip) for repair. After the memory defect is found through the BIST logic test designed in the chip, the repair information is actively burned into the efuse in the chip through the efuse (Electronic Fuse) controller for recording. Finally, when the chip is started, the repair information recorded by the efuse is used by the BISR repair logic to repair the memory. Once the efuse in the chip is burned, the corresponding repair information cannot be changed again. This set of methods has been supported by many EDA (Electronic Design Automation, Electronic Design Automation) manufacturers, and has in fact become a typical design method and technology on the DFT (Design for Test, Design for Testability) tool chain in chip design.

[0038] However, this method has some shortcomings: first, the relevant design ideas mainly consider the test and repair information recording on ATE (Automatic Test Equipment, an automatic test machine for chip testing), which takes up expensive ATE test time; second, the method of using efuse to record repair information is one-time and irreversible, so it is not flexible enough when multiple modifications or repairs are required; third, it cannot be repaired in actual system use, because memory repair may need to be solved throughout the life cycle of the chip. The use of efuse and one-time factory repair cannot solve the problems faced by the chip in actual use in the system to the greatest extent.

[0039] Based on the above analysis, an exemplary implementation scheme of a centralized controlled memory repair system provided in the specific implementation scheme of the present application is as follows: Figure 1 The centrally controlled memory repair system includes an on-chip TAP controller (TAPcontroller) C2, an on-chip BIST logic C4, an on-chip BISR logic C8 and a BISR controller C20, an on-chip storage recovery controller (Save and Restore Controller, a controller for storing and restoring data inside the chip) C16, an external non-volatile storage medium C18, and an on-chip non-volatile storage medium update tool C22. A first MUX C14 is provided between the on-chip TAP controller C2 and the on-chip storage recovery controller C16, and a second MUX C6 is provided between the on-chip BISR logic C8 and the on-chip BIST logic C4.

[0040] Exemplarily, the above-mentioned TAP controller C2 has a test interface C1, which is used to provide test control and comparison information of ROM contents. The test interface C1 is usually a JTAG interface (Joint Test Action Group, a common name for IEEE standard 1149.1 for standard test access port and boundary scan structure), but is not limited to the JTAG interface. Considering the process of accelerating test and repair information recording at the system level, the interface can also be customized.

[0041] Exemplarily, the TAP controller C2 provides BIST test control and ROM content comparison information through the external test interface C1, or directly starts and configures the on-chip storage repair controller C16 to record memory repair information after being selected by the first MUXC14 logic, wherein the first MUXC14 implements the switching control of the repair information transmission interface C13.1, and the first MUXC14 has a corresponding repair information transmission interface C15 after the selection switching, and the repair information transmitted by the BIST logic C4 or the TAP controller C2 is finally transmitted to the on-chip storage repair controller C16 through this interface. The TAP controller C2 is connected to the first MUX through the repair information transmission interface C13.1. Similarly, considering the process of accelerating testing and repair information recording at the system level, the TAP controller C2 can be developed and designed according to a custom test interface.

[0042] Exemplarily, the TAP controller C2 is connected to the BIST logic C4 in the chip through the BIST control interface C3. The BIST logic C4 in the chip is an embedded self-test (Buildin SelfTest) logic. When a memory defect is found during the test, the repair information of the memory can be transmitted to the on-chip storage repair controller C16. The BIST logic in the chip is connected to the on-chip storage recovery controller C16 through the repair information transmission interface C13.0, and the on-chip storage repair controller C16 records the repair information of the memory to the external non-volatile storage medium C18.

[0043] Furthermore, the BISR controller C20 is connected to the BISR logic C8 via the BISR configuration interface C21. The BISR logic C8 is an embedded redundant memory repair logic (Buildin SelfRepair). The configured memory repair information can be used to repair the specified location on the specified memory. Different configurations can achieve repairs of different locations on different memories, that is, changing the BISR configuration means changing the repair location and repair strategy of different memories. The on-chip storage recovery controller C16 is connected to the BISR controller C20 via the repair information transmission interface C19.

[0044] Exemplarily, the BISR logic C8 is connected to different ROM entities C11.1, C11.2 ... C11.m in the chip through access buses C9.1, C9.2 ... C9.m, and is connected to different RAM entities C12.1, C12.2 ... C12.n in the chip through access buses C10.1, C10.2 ... C10.m.

[0045] There is a second MUXC6 between the BIST logic C4 and the BISR logic C8. The second MUXC6 is connected to the BIST logic C4 through the memory test access interface C5.0. The second MUXC6 is connected to the BISR logic C8 through the memory access interface C7. After the memory access interface C7 passes through the BISR logic C8, the repaired memory can be replaced by the redundant repair logic provided in the BISR to realize the memory repair function. The second MUXC6 has the main function access interface C5.1 of the memory.

[0046] The above-mentioned external non-volatile storage medium C18 and the on-chip storage recovery controller C16 have an access interface C17, and the access interface C17 is used to record the memory repair information stored in the above-mentioned on-chip storage recovery controller C16 to the external non-volatile storage medium C18 or load the memory repair information in the external non-volatile storage medium C18 into the on-chip storage recovery controller C16. The external non-volatile storage medium update tool C22 has an access interface C23, which is used to update the external non-volatile storage medium C18.

[0047] In another embodiment, the BISR repair logic and repair information can be distributed to the ROM or RAM entity corresponding to each memory to implement a separately controlled memory repair system, such as Figure 2 As shown. The BISR controller is connected to multiple BISR logics through a BISR configuration interface, and the multiple BISR logics are respectively connected to a ROM entity or a RAM entity in the chip. Each of the BISR logics is connected to a BIST logic through multiple MUXs.

[0048] The second aspect of the present application exemplarily proposes a method for repairing memory in a chip using the above-mentioned on-chip memory repair system, comprising the following steps:

[0049] Perform a boot test, provide test control and ROM content comparison information to the memory through the test interface of the TAP controller, and test the memory through the BIST logic;

[0050] If a memory defect is found during the test, the memory repair information is transmitted to the on-chip storage recovery controller, and the on-chip storage recovery controller records the memory repair information to an external non-volatile medium;

[0051] Alternatively, when the startup test is not performed, the external non-volatile storage medium is directly updated through the external non-volatile storage medium update tool;

[0052] When the chip starts, the storage recovery controller in the chip loads the repair information of the memory in the external non-volatile medium, and repairs the specified location on the memory through the BISR repair logic.

[0053] Exemplarily, the BISR repair logic may control or repair all ROM or RAM entities of the memory, or may control or repair each ROM or RAM entity of the memory separately.

[0054] It can be seen that the in-chip memory repair system and method proposed in this application have the following advantages compared with the related art:

[0055] The memory repair system in the chip of the present application maintains the existing BIST and BISR designs in the chip to the maximum extent, but introduces the memory repair method from the inside of the chip to the board-level system of the chip for solution. A new workflow and mechanism are defined on the system compatible with the previous board-level design and in conjunction with the unique design in the chip, the memory repair information is recorded in an external non-volatile storage medium, and the repair information is loaded from the external non-volatile storage medium for repair when the chip is started, so that the memory repair can be performed at the board level from the system perspective, which saves the efuse burning time of the test and repair memory on the ATE, and also saves the efuse resources in the chip. At the same time, since the repair information can be conveniently modified and adjusted at will on the external non-volatile storage medium and this part of the repair information belongs to the dynamic configuration for the BISR repair logic in the chip, it can be repeatedly updated, especially for the content modification of the ROM is not limited to repair, but when it is found that the content of the ROM (such as some important parameters placed in the ROM) needs to be adjusted, the same position of the ROM can also be modified multiple times as needed and reused repeatedly.

[0056] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0057] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory repair system in a chip, comprising an in-chip TAP controller, an in-chip BIST logic, an in-chip BISR logic and BISR controller, and an in-chip storage recovery controller, characterized in that: It includes an external non-volatile storage medium, and the external non-volatile storage medium and the on-chip storage recovery controller have an access interface C17, and the access interface C17 is used to record the memory repair information stored in the on-chip storage recovery controller to the external non-volatile storage medium or load the memory repair information in the external non-volatile storage medium into the on-chip storage recovery controller.

2. The on-chip memory repair system according to claim 1, characterized in that: It further comprises an external non-volatile storage medium update tool, wherein the external non-volatile storage medium update tool has an access interface C23 for updating the external non-volatile storage medium.

3. The on-chip memory repair system according to claim 1, characterized in that: The TAP controller is logically connected to the BIST via a BIST control interface C3. A first MUX is provided between the TAP controller and the on-chip storage recovery controller. The TAP controller is connected to the first MUX via a repair information transmission interface C13.

1.

4. The on-chip memory repair system according to claim 1, characterized in that: The BISR controller is connected to a single BISR logic through a BISR configuration interface C21, and the single BISR logic is connected to different ROM entities C11.1, C11.2...C11.m in the chip through access buses C9.1, C9.2...C9.m, and is connected to different RAM entities C12.1, C12.2...C12.n in the chip through access buses C10.1, C10.2...C10.n.

5. The on-chip memory repair system according to claim 1, characterized in that: The BISR controller is connected to a plurality of BISR logics via a BISR configuration interface, and the plurality of BISR logics are respectively connected to ROM entities or RAM entities in each chip.

6. The on-chip memory repair system according to claim 4 or 5, characterized in that: There are one or more second MUXs between the BIST logic and the single or multiple BISR logics. The one or more second MUXs are connected to the BIST logic through the memory test access interface C5.0, and the second MUXs are connected to the single or multiple BISR logics through the memory access interface C7.

7. The on-chip memory repair system according to claim 6, characterized in that: The second MUX has a main function access interface C5.1 of the memory.

8. The on-chip memory repair system according to claim 1, characterized in that: The on-chip storage recovery controller is connected to the BISR controller via a repair information transmission interface C19.

9. The on-chip memory repair system according to claim 1, characterized in that: The BIST logic is connected to the on-chip storage recovery controller C16 via the repair information transmission interface C13.

0.

10. The on-chip memory repair system according to claim 1, characterized in that: The TAP controller has a test interface C1, which is used to provide test control and comparison information of ROM content.

11. A method for repairing memory in a chip, characterized in that: The steps include: Perform a boot test, provide test control and ROM content comparison information to the memory through the test interface of the TAP controller, and test the memory through the BIST logic; If a memory defect is found during the test, the memory repair information is transmitted to the on-chip storage recovery controller, and the on-chip storage recovery controller records the memory repair information to an external non-volatile medium; or, Without performing a startup test, the external non-volatile storage medium is directly updated through the external non-volatile storage medium update tool; When the chip starts, the storage recovery controller in the chip loads the repair information of the memory in the external non-volatile medium, and repairs the specified location on the memory through the BISR repair logic.

12. The method for repairing memory in a chip according to claim 11, characterized in that: The BISR repair logic controls or repairs all ROM or RAM entities of the memory; or, the BISR repair logic controls or repairs each ROM or RAM entity of the memory separately.

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