On-chip oscillation system and method

Abstract

The embodiment of the invention relates to an on-chip oscillation system, and the system comprises a bias generation circuit which processes the voltage of a power input end, and generates a first bias voltage; the starting circuit generates a first branch voltage when the enable signal is overturned to a high level; the oscillation generation circuit comprises first to third stages of reverse phase time shift circuits, the first stage of reverse phase time shift circuit performs charging, and when the first branch voltage is greater than a preset first threshold value and the current of the first stage of reverse phase time shift circuit is greater than a first bias current, the second stage of reverse phase time shift circuit starts and discharges; when the second branch voltage of the second-stage anti-phase time shift circuit is pulled down to a second threshold value, the third-stage anti-phase time shift circuit is started, and a pre-output clock signal is generated; and the clock output circuit generates a pull-up clock signal, performs pull-up shaping on the pre-output clock signal, generates a reverse-phase discharge signal, pulls down the first branch voltage to the ground potential through the reverse-phase discharge signal, inverts the first branch voltage and the pre-output clock signal, and outputs the clock signal.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an on-chip oscillation system and method. Background Art

[0002] An oscillator is a device that can automatically convert a DC signal into a periodic AC signal without an external excitation signal. It has a wide range of uses. For example, an oscillator can be used as a timer in a timing device; in the field of wireless communication technology, an oscillator is an important component of a transmitter and a receiver; in measurement technology, it is used to generate various test signals. With the development of electronic communication technology, the requirements for terminal equipment are getting higher and higher, which has led to the development of oscillators towards lower cost, power consumption, and power supply voltage. It has become an urgent need to provide reliable low-cost, low-voltage, and low-power clock modules.

[0003] Conventional oscillator types include: (1) LC oscillator. An oscillator that uses an LC resonant circuit as a feedback oscillator of a dependent network is called an LC oscillator. It is mainly used in high-frequency systems. Due to the presence of inductance, it is difficult to implement this technology on a chip. (2) Phase-Locked Loop (PLL) phase-locked oscillation structure. The frequency and phase of the oscillation signal inside the loop are controlled by an external reference signal to achieve equal input and output frequencies. This method has the characteristics of complex structure, huge power consumption, and extremely high cost. (3) RC oscillator. It is composed of a constant current source, a charging and discharging capacitor, a comparator, and an RS latch. The capacitor is charged and discharged by a constant current to generate a clock signal. This method has the characteristics of high power consumption, complex structure, and high requirements for power supply voltage. Summary of the invention

[0004] The purpose of the present invention is to provide an on-chip oscillation system to solve the problems existing in the prior art in view of the defects existing in the prior art.

[0005] To achieve the above object, the present invention provides an on-chip oscillator system in a first aspect, comprising:

[0006] A bias generating circuit is connected to the power input terminal, processes the current of the power input terminal, and generates a first bias voltage and a second bias voltage; the first bias voltage corresponds to a first bias current, and the second bias voltage corresponds to a second bias current;

[0007] a start-up circuit, connected to the enable terminal, the power input terminal and the first output terminal of the bias generating circuit respectively, receiving the first bias voltage, and starting charging according to the first bias voltage when the enable signal input to the enable terminal is flipped to a high level, and generating a first branch voltage for charging;

[0008] an oscillation generating circuit, connected to the output end of the start-up circuit, the power input end, the first output end of the bias generating circuit and the second output end of the bias generating circuit respectively, the oscillation generating circuit comprising a first-stage inverting time shift circuit, a second-stage inverting time shift circuit and a third-stage inverting time shift circuit, the first-stage inverting time shift circuit is charged according to the first branch voltage, when the first branch voltage is greater than a preset first threshold value, when the current of the first-stage inverting time shift circuit is greater than a first bias current, the first-stage inverting time shift circuit outputs a low level; the second-stage inverting time shift circuit is started and discharged, when the second branch voltage of the second-stage inverting time shift circuit is pulled down to the second threshold value, the third-stage inverting time shift circuit is started to generate a pre-output clock signal;

[0009] The clock output circuit is respectively connected to the output end of the oscillation generating circuit, the output end of the starting circuit and the power input end. After receiving the pre-output clock signal and generating a pull-up clock signal, the pre-output clock signal is pulled up and shaped according to the pull-up clock signal to generate an inverted discharge signal. The first branch voltage is pulled down to the ground potential through the inverted discharge signal, the first branch voltage and the pre-output clock signal are inverted, and the clock signal is output.

[0010] In a possible implementation, the bias generating circuit includes a first MOS transistor, a second MOS transistor and a resistor;

[0011] The gate of the first MOS tube is connected to the drain of the first MOS tube and the first end of the resistor, the source of the first MOS tube is grounded, the second end of the resistor is connected to the gate of the second MOS tube and the drain of the second MOS tube, and the source of the second MOS tube is connected to the power input end.

[0012] In a possible implementation, the startup circuit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor;

[0013] The gate of the third MOS tube is connected to the gate of the second MOS tube, the source of the third MOS tube is connected to the power input terminal, the drain of the third MOS tube is connected to the source of the fourth MOS tube, the gate of the fourth MOS tube is respectively connected to the drain of the fifth MOS tube, the drain of the sixth MOS tube, and the gate of the seventh MOS tube, the drain of the fourth MOS tube is connected to the drain of the seventh MOS tube, the gate of the fifth MOS tube and the gate of the sixth MOS tube are respectively connected to the enable terminal, the drain of the fifth MOS tube is connected to the drain of the sixth MOS tube, the source of the fifth MOS tube is connected to the power input terminal, and the source of the sixth MOS tube and the source of the seventh MOS tube are grounded.

[0014] In a possible implementation, the first-stage inverting time-shift circuit includes an eighth MOS tube, a ninth MOS tube, and a tenth MOS tube; the second-stage inverting time-shift circuit includes an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, and a fourteenth MOS tube; the third-stage inverting time-shift circuit includes a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, and an eighteenth MOS tube;

[0015] The gate of the eighth MOS tube is respectively connected to the drain of the fourth MOS tube, the drain of the seventh MOS tube and the gate of the tenth MOS tube, the drain and source of the eighth MOS tube, the source of the tenth MOS tube, the source of the fourteenth MOS tube, the source of the sixteenth MOS tube and the source of the eighteenth MOS tube are grounded, the gate of the ninth MOS tube, the gate of the eleventh MOS tube and the gate of the seventeenth MOS tube are respectively connected to the first bias current, the source of the ninth MOS tube, the source of the eleventh MOS tube, the source and drain of the twelfth MOS tube, the source of the fifteenth MOS tube, the source of the seventeenth MOS tube and the power input The input end of the ninth MOS tube is connected to the drain of the tenth MOS tube and the gate of the thirteenth MOS tube, the drain of the eleventh MOS tube is connected to the gate of the twelfth MOS tube, the source of the thirteenth MOS tube and the gate of the fifteenth MOS tube, the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube, the gate of the fourteenth MOS tube and the gate of the sixteenth MOS tube are respectively connected to the second bias current, the drain of the fifteenth MOS tube is connected to the drain of the sixteenth MOS tube and the gate of the eighteenth MOS tube, and the drain of the seventeenth MOS tube is connected to the drain of the eighteenth MOS tube.

[0016] In a possible implementation, the clock output circuit includes a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, and a twenty-second MOS transistor;

[0017] The source of the nineteenth MOS tube and the source of the twentieth MOS tube are respectively connected to the power input terminal, the drain of the nineteenth MOS tube is respectively connected to the drain of the seventeenth MOS tube, the drain of the eighteenth MOS tube, the gate of the twentieth MOS tube and the gate of the twenty-first MOS tube, the gate of the nineteenth MOS tube is respectively connected to the drain of the twentieth MOS tube and the drain of the twenty-first MOS tube, the drain of the 20th MOS tube is connected to the drain of the twenty-first MOS tube and the gate of the twenty-second MOS tube, the source of the twenty-first MOS tube and the source of the twenty-second MOS tube are grounded, and the drain of the twenty-second MOS tube is connected to the first branch voltage.

[0018] In a possible implementation, the first-stage inverting time-shift circuit is charged according to the first branch voltage, and when the first branch voltage is greater than a preset first threshold value and the current of the first-stage inverting time-shift circuit is greater than a first bias current, the first-stage inverting time-shift circuit outputs a low level; the second-stage inverting time-shift circuit is started and discharged, and when the second branch voltage of the second-stage inverting time-shift circuit is pulled down to the second threshold value, the third-stage inverting time-shift circuit is started, and generating a pre-output clock signal specifically includes:

[0019] The eighth MOS tube is charged according to the current of the first branch voltage; when the first branch voltage is greater than the first threshold, the tenth MOS tube is turned on, the thirteenth MOS tube is turned on, the second bias current of the fourteenth MOS tube is greater than the current of the eleventh MOS tube, the twelfth MOS tube is discharged, the second branch voltage is pulled down, and when the second branch voltage is pulled down to the second threshold, the pre-output clock signal is pulled down to a low level.

[0020] In a second aspect, the present invention provides a method based on an on-chip oscillation system, the method comprising:

[0021] The bias generating circuit processes the voltage at the power input terminal to generate a first bias voltage and a second bias voltage; the first bias voltage corresponds to a first bias current, and the second bias voltage corresponds to a second bias current;

[0022] The start-up circuit receives the first bias voltage, and when the enable signal inputted at the enable terminal is flipped to a high level, starts charging according to the first bias voltage and generates a first branch voltage for charging;

[0023] Oscillation generating circuit The oscillation generating circuit comprises a first-stage inverting time shift circuit, a second-stage inverting time shift circuit and a third-stage inverting time shift circuit. The first-stage inverting time shift circuit is charged according to the first branch voltage. When the first branch voltage rises to be greater than a preset first threshold value and the current of the first-stage inverting time shift circuit is greater than a first bias current, the first-stage inverting time shift circuit outputs a low level. The second-stage inverting time shift circuit is started and discharged. When the second branch voltage of the second-stage inverting time shift circuit is pulled down to the second threshold value, the third-stage inverting time shift circuit is started to generate a pre-output clock signal.

[0024] After receiving the pre-output clock signal, the clock output circuit generates a pull-up clock signal, pulls up and shapes the pre-output clock signal according to the pull-up clock signal, generates an inverted discharge signal, pulls the first branch voltage down to the ground potential through the inverted discharge signal, inverts the first branch voltage and the pre-output clock signal, and outputs a clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A structural diagram of an on-chip oscillator system provided by an embodiment of the present invention;

[0026] Figure 2 for Figure 1 A specific embodiment of

[0027] Figure 3 for Figure 2 A magnified view of the bias generation circuit in FIG.

[0028] Figure 4 for Figure 2 Method diagram of the starting circuit in;

[0029] Figure 5 for Figure 2 An enlarged view of the oscillation generating circuit in FIG.

[0030] Figure 6 for Figure 2 An enlarged view of the clock output circuit in FIG.

[0031] Figure 7 A flow chart of a method based on an on-chip oscillation system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.

[0034] Figure 1 This is a structural diagram of an on-chip oscillator system provided by an embodiment of the present invention. The on-chip oscillator system is used in scenarios that are not sensitive to clock accuracy but are sensitive to power consumption and cost. Figure 1 As shown, the on-chip oscillation system includes: a bias generating circuit 10 , a start-up circuit 20 , an oscillation generating circuit 30 and a clock output circuit 40 .

[0035] The bias generating circuit 10 is connected to the power input terminal, processes the voltage of the power input terminal, and generates a first bias voltage and a second bias voltage; the first bias voltage corresponds to a first bias current, and the second bias voltage corresponds to a second bias current;

[0036] The start-up circuit 20 is respectively connected to the enable terminal, the power input terminal and the first output terminal of the bias generation circuit, receives the first bias current, and starts charging according to the first bias current when the enable signal input to the enable terminal is flipped to a high level, and generates a first branch voltage for charging;

[0037] The oscillation generating circuit 30 is respectively connected to the output end of the start-up circuit, the power input end, the first output end of the bias generating circuit and the second output end of the bias generating circuit. The oscillation generating circuit includes a first-stage inverting time shift circuit, a second-stage inverting time shift circuit and a third-stage inverting time shift circuit. The first-stage inverting time shift circuit is charged according to the first branch voltage. When the first branch voltage rises to a value greater than a preset first threshold value and the current of the first-stage inverting time shift circuit is greater than the first bias current, the first-stage inverting time shift circuit outputs a low level. The second-stage inverting time shift circuit is started and discharged. When the second branch voltage of the second-stage inverting time shift circuit is pulled down to the second threshold value, the third-stage inverting time shift circuit is started to generate a pre-output clock signal.

[0038] The clock output circuit 40 is respectively connected to the output end of the oscillation generating circuit, the output end of the starting circuit and the power input end. After receiving the pre-output clock signal, after generating the pull-up clock signal, the pre-output clock signal is pulled up and shaped according to the pull-up clock signal to generate an inverted discharge signal. The first branch voltage is pulled down to the ground potential through the inverted discharge signal, the first branch voltage and the pre-output clock signal are inverted, and the clock signal is output.

[0039] See also Figure 2-Figure 6 , the bias generating circuit includes a first MOS tube M1, a second MOS tube M2 and a resistor R;

[0040] The gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1 and the first end of the resistor, the source of the first MOS tube M1 is grounded, the second end of the resistor R is connected to the gate of the second MOS tube M2 and the drain of the second MOS tube M2, and the source of the second MOS tube M2 is connected to the power input terminal. Among them, the bias generation circuit determines the current bias by connecting the first MOS tube M2, the resistor R1 and the second MOS tube M2 in series, and transmits it to the charging current source of the startup circuit and the oscillation generation circuit through VBP0 and VBN0. The first MOS tube M1 corresponds to the second bias current VNN0, and the second bias current provides a current reference for all NMOS current drains. The second MOS tube M2 corresponds to the first bias current VBP0, and the first bias current provides a current reference for all PMOS current sources in the circuit. The resistance value of the resistor R1 can be set as needed, so that different resistance values ​​can correspond to different frequency clock signals, ensuring the flexibility of the on-chip oscillation system and reducing power consumption.

[0041] Further, the startup circuit includes a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6 and a seventh MOS tube M7;

[0042] The gate of the third MOS tube M3 is connected to the gate of the second MOS tube M2, the source of the third MOS tube M3 is connected to the power input terminal, the drain of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, the gate of the fourth MOS tube M4 is respectively connected to the drain of the fifth MOS tube M5, the drain of the sixth MOS tube M6, and the gate of the seventh MOS tube M7, the drain of the fourth MOS tube M4 is connected to the drain of the seventh MOS tube M7, the gate of the fifth MOS tube M5 and the gate of the sixth MOS tube M6 are respectively connected to the enable terminal, the drain of the fifth MOS tube M5 is connected to the drain of the sixth MOS tube M6, the source of the fifth MOS tube M5 is connected to the power input terminal, and the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7 are grounded. Among them, the enable terminal is Enable, which is connected to the external system and receives the enable signal sent by the external system.

[0043] Further, the first-stage inverting time shift circuit includes an eighth MOS tube M8, a ninth MOS tube M9, and a tenth MOS tube M10; the second-stage inverting time shift circuit includes an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, and a fourteenth MOS tube M14; the third-stage inverting time shift circuit includes a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, and an eighteenth MOS tube M18;

[0044] The gate of the eighth MOS tube M8 is respectively connected to the drain of the fourth MOS tube M4, the drain of the seventh MOS tube M7 and the gate of the tenth MOS tube M10, the drain and source of the eighth MOS tube M8, the source of the tenth MOS tube, the source of the fourteenth MOS tube, the source of the sixteenth MOS tube and the source of the eighteenth MOS tube are grounded, the gate of the ninth MOS tube M9, the gate of the eleventh MOS tube M11 and the gate of the seventeenth MOS tube M17 are respectively connected to the first bias current, the source of the ninth MOS tube M9, the source of the eleventh MOS tube M11, the source and drain of the twelfth MOS tube M12, the source of the fifteenth MOS tube M15, the source of the seventeenth MOS tube M17 are connected to the power input terminal, The drain of the ninth MOS tube M9 is connected to the drain of the tenth MOS tube M10 and the gate of the thirteenth MOS tube M13, the drain of the eleventh MOS tube M11 is connected to the gate of the twelfth MOS tube M12, the source of the thirteenth MOS tube M13 and the gate of the fifteenth MOS tube M15, the drain of the thirteenth MOS tube M13 is connected to the drain of the fourteenth MOS tube M14, the gate of the fourteenth MOS tube M14 and the gate of the sixteenth MOS tube M16 are respectively connected to the second bias current, the drain of the fifteenth MOS tube M15 is connected to the drain of the sixteenth MOS tube M16 and the gate of the eighteenth MOS tube M18, and the drain of the seventeenth MOS tube M17 is connected to the drain of the eighteenth MOS tube M18. Among them, CHG1 is the first branch voltage, and CHG2 is the second branch voltage.

[0045] Further, the clock output circuit 40 includes a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, and a twenty-second MOS transistor M22;

[0046] The source of the nineteenth MOS tube M19 and the source of the twentieth MOS tube M20 are respectively connected to the power input terminal, the drain of the nineteenth MOS tube M19 is respectively connected to the drain of the seventeenth MOS tube M17, the drain of the eighteenth MOS tube M18, the gate of the twentieth MOS tube M20 and the gate of the twenty-first MOS tube M21, the gate of the nineteenth MOS tube M19 is respectively connected to the drain of the twentieth MOS tube M20 and the drain of the twenty-first MOS tube M21, the drain of the twentieth MOS tube M20 is connected to the drain of the twenty-first MOS tube M21 and the gate of the twenty-second MOS tube M20, the source of the twenty-first MOS tube M21 and the source of the twenty-second MOS tube M22 are grounded, and the drain of the twenty-second MOS tube M22 is connected to the first branch voltage. CLK_PRE is a pre-output clock signal, and CLK is a pull-up clock signal.

[0047] The working process of the on-chip oscillation system is described below:

[0048] The bias generating circuit 10 generates two bias currents, namely, a first bias current and a second bias current. The first bias current is input to the third MOS tube M3 of the start-up circuit. At the same time, the fifth MOS tube M5 and the sixth MOS tube M6 of the start-up circuit receive an enable signal. The enable signal is buffered by the fourth MOS tube M4 to the seventh MOS tube M7 to generate an enable buffer signal. The enable buffer signal enhances the analog level of the external input logic signal. When the enable signal turns high, the fourth MOS tube M4 is turned on, the seventh MOS tube M7 is turned off, and the current source of the third MOS tube M3 is turned on under the action of the first bias current. At this time, the start-up circuit 20 starts charging, and charges the capacitor equivalent to the eighth MOS tube M8 of the oscillation generating circuit 30 through the first branch voltage CHG1. During the charging process, when the first branch voltage CHG1 is greater than the preset level V1, if V1 is the start-up level of the tenth MOS tube M10, the tenth MOS tube M10 is turned on, the ninth MOS tube M9 and the tenth MOS tube M10 form a current comparator, and the tenth The MOS tube is equivalent to a constant current source, and its current leakage pulls down the output of the current comparator to a low level. The thirteenth MOS tube M13 is turned on, and the fourteenth MOS tube M14 receives the second bias current. If the current leakage current capability of the fourteenth MOS tube M14 is greater than the current source capability of the eleventh MOS tube M11, after the thirteenth MOS tube M13 is turned on, the fourteenth MOS tube M14 discharges the equivalent capacitance of the twelfth MOS tube M12, so that the second branch voltage CHG2 is pulled down to the preset voltage V2. If V2 is the turn-on level of the fifteenth MOS tube M15, when V2 drops to the turn-on level of the fifteenth MOS tube M15, the fifteenth MOS tube M15 and the sixteenth MOS tube M16 form a current comparator. The fifteenth MOS tube is equivalent to a current source, and the current source pulls up the output of the current comparator to a high level. The eighteenth MOS tube M18 is turned on, and the seventeenth MOS tube M17 and the eighteenth MOS tube M18 form a current comparator. The pre-output clock signal CLK_PRE output by the current comparator of this level is pulled down to a low level. Among them, V1 is the first threshold, and V2 is the second threshold, which can be set according to actual needs.

[0049] After the clock output circuit 40 receives the pulled-down CLK_PRE signal, the clock signal CLK is pulled up through the nineteenth MOS tube M19 and the twentieth MOS tube M20, and the CLK is transmitted to the gates of the twenty-second MOS tube M22 and the nineteenth MOS tube M19, and the drain of the twenty-second MOS tube M22 is connected to the first branch voltage, and the drain of the nineteenth MOS tube M19 is connected to the pre-output clock signal CLK_PRE, which is equivalent to generating a positive phase charging signal to pull up the pre-output clock signal CLK_PRE and generating a negative phase discharge signal to pull down CHG1 to the ground potential, thereby inverting CHG1 and CLK_PRE. Since CHG1 is inverted, the oscillation generating circuit will not charge, and after CLK_PRE is inverted, it becomes a high level, so that the on-chip oscillation system enters the next charging cycle, and through these continuous charging cycles, the on-chip oscillation system can output a periodic clock signal CLK. The positive promotion effect of the nineteenth MOS tube M19 on the change of the CLK_PRE signal constitutes positive feedback; and the twenty-second MOS tube M22 constitutes negative feedback on the reverse discharge of CHG1.

[0050] Specifically, CLK_PRE is input to the nineteenth MOS tube M19, the twentieth MOS tube M20 and the twenty-first MOS tube M21, and the change process of CLK is as follows:

[0051] CLK changes from high to low: when CLK_PRE changes from high to low, CLK tends to change from low to high. When CLK gradually becomes high, the nineteenth MOS tube M19 is turned off, and the eighteenth MOS tube M18 of the previous stage can pull down the CLK_PRE signal faster, thereby pulling up CLK faster.

[0052] CLK changes from high to low: when CLK_PRE changes from low to high, CLK tends to change from high to low. When CLK gradually becomes low, the nineteenth MOS tube M19 is turned on, and the seventeenth MOS tube M17 and the nineteenth MOS tube M19 of the previous stage can pull up the CLK_PRE signal faster, thereby pulling down CLK faster.

[0053] By applying the on-chip oscillation system provided by the example of the present invention, through a self-bias generating circuit with adjustable power consumption, through the three-stage inverting time-shift circuit of the oscillation generating circuit, and the clock output circuit with positive and negative feedback of the clock output circuit, a reliable and low-cost clock module is realized, which can be used in fields such as timers and measurement technology that are not sensitive to clock accuracy but are sensitive to power consumption and cost.

[0054] Figure 7 A flow chart of a method based on an on-chip oscillation system provided by an embodiment of the present invention, such as Figure 7 As shown, the method comprises the following steps:

[0055] In step 710, the bias generating circuit processes the current at the power input terminal to generate a first bias voltage and a second bias voltage; the first bias voltage corresponds to a first bias current, and the second bias voltage corresponds to a second bias current.

[0056] Step 720: The start-up circuit receives the first bias voltage, and when the enable signal input to the enable terminal is flipped to a high level, the start-up circuit starts charging according to the first bias voltage and generates a first branch voltage for charging.

[0057] Step 730, the oscillation generating circuit includes a first-stage inverting time-shift circuit, a second-stage inverting time-shift circuit and a third-stage inverting time-shift circuit. The first-stage inverting time-shift circuit is charged according to the first branch voltage. When the first branch voltage rises to be greater than a preset first threshold value and the current of the first-stage inverting time-shift circuit is greater than the first bias current, the first-stage inverting time-shift circuit outputs a low level; the second-stage inverting time-shift circuit is started and discharged. When the second branch voltage of the second-stage inverting time-shift circuit is pulled down to the second threshold value, the third-stage inverting time-shift circuit is started to generate a pre-output clock signal.

[0058] Step 740, after the clock output circuit receives the pre-output clock signal and generates a pull-up clock signal, it pulls up and shapes the pre-output clock signal according to the pull-up clock signal to generate an inverted discharge signal, pulls the first branch voltage down to the ground potential through the inverted discharge signal, inverts the first branch voltage and the pre-output clock signal, and outputs the clock signal.

[0059] The professionals should further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0060] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0061] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An on-chip oscillator system, characterized in that: The on-chip oscillation system comprises: A bias generating circuit is connected to the power input terminal, processes the voltage of the power input terminal, and generates a first bias voltage and a second bias voltage; the first bias voltage corresponds to a first bias current, and the second bias voltage corresponds to a second bias current; a start-up circuit, connected to the enable terminal, the power input terminal and the first output terminal of the bias generating circuit respectively, receiving the first bias voltage, and starting charging according to the first bias voltage when the enable signal input to the enable terminal is flipped to a high level, and generating a first branch voltage for charging; an oscillation generating circuit, connected to the output end of the start-up circuit, the power input end, the first output end of the bias generating circuit and the second output end of the bias generating circuit respectively, the oscillation generating circuit comprising a first-stage inverting time shift circuit, a second-stage inverting time shift circuit and a third-stage inverting time shift circuit, the first-stage inverting time shift circuit is charged according to the first branch voltage, when the first branch voltage is greater than a preset first threshold value, when the current of the first-stage inverting time shift circuit is greater than a first bias current, the first-stage inverting time shift circuit outputs a low level; the second-stage inverting time shift circuit is started and discharged, when the second branch voltage of the second-stage inverting time shift circuit is pulled down to the second threshold value, the third-stage inverting time shift circuit is started to generate a pre-output clock signal; The clock output circuit is respectively connected to the output end of the oscillation generating circuit, the output end of the starting circuit and the power input end. After receiving the pre-output clock signal and generating a pull-up clock signal, the pre-output clock signal is pulled up and shaped according to the pull-up clock signal to generate an inverted discharge signal. The first branch voltage is pulled down to the ground potential through the inverted discharge signal, the first branch voltage and the pre-output clock signal are inverted, and the clock signal is output.

2. The system according to claim 1, characterized in that The bias generating circuit comprises a first MOS tube, a second MOS tube and a resistor; The gate of the first MOS tube is connected to the drain of the first MOS tube and the first end of the resistor, the source of the first MOS tube is grounded, the second end of the resistor is connected to the gate of the second MOS tube and the drain of the second MOS tube, and the source of the second MOS tube is connected to the power input end.

3. The system according to claim 2, characterized in that The startup circuit includes a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; The gate of the third MOS tube is connected to the gate of the second MOS tube, the source of the third MOS tube is connected to the power input terminal, the drain of the third MOS tube is connected to the source of the fourth MOS tube, the gate of the fourth MOS tube is respectively connected to the drain of the fifth MOS tube, the drain of the sixth MOS tube, and the gate of the seventh MOS tube, the drain of the fourth MOS tube is connected to the drain of the seventh MOS tube, the gate of the fifth MOS tube and the gate of the sixth MOS tube are respectively connected to the enable terminal, the drain of the fifth MOS tube is connected to the drain of the sixth MOS tube, the source of the fifth MOS tube is connected to the power input terminal, and the source of the sixth MOS tube and the source of the seventh MOS tube are grounded.

4. The system according to claim 3, characterized in that The first-stage inverting time-shift circuit includes an eighth MOS tube, a ninth MOS tube, and a tenth MOS tube; the second-stage inverting time-shift circuit includes an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, and a fourteenth MOS tube; the third-stage inverting time-shift circuit includes a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, and an eighteenth MOS tube; The gate of the eighth MOS tube is respectively connected to the drain of the fourth MOS tube, the drain of the seventh MOS tube and the gate of the tenth MOS tube, the drain and source of the eighth MOS tube, the source of the tenth MOS tube, the source of the fourteenth MOS tube, the source of the sixteenth MOS tube and the source of the eighteenth MOS tube are grounded, the gate of the ninth MOS tube, the gate of the eleventh MOS tube and the gate of the seventeenth MOS tube are respectively connected to the first bias current, the source of the ninth MOS tube, the source of the eleventh MOS tube, the source and drain of the twelfth MOS tube, the source of the fifteenth MOS tube, the source of the seventeenth MOS tube and the power input The input end of the ninth MOS tube is connected to the drain of the tenth MOS tube and the gate of the thirteenth MOS tube, the drain of the eleventh MOS tube is connected to the gate of the twelfth MOS tube, the source of the thirteenth MOS tube and the gate of the fifteenth MOS tube, the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube, the gate of the fourteenth MOS tube and the gate of the sixteenth MOS tube are respectively connected to the second bias current, the drain of the fifteenth MOS tube is connected to the drain of the sixteenth MOS tube and the gate of the eighteenth MOS tube, and the drain of the seventeenth MOS tube is connected to the drain of the eighteenth MOS tube.

5. The system according to claim 4, characterized in that The clock output circuit includes a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, and a twenty-second MOS tube; The source of the nineteenth MOS tube and the source of the twentieth MOS tube are respectively connected to the power input terminal, the drain of the nineteenth MOS tube is respectively connected to the drain of the seventeenth MOS tube, the drain of the eighteenth MOS tube, the gate of the twentieth MOS tube and the gate of the twenty-first MOS tube, the gate of the nineteenth MOS tube is respectively connected to the drain of the twentieth MOS tube and the drain of the twenty-first MOS tube, the drain of the 20th MOS tube is connected to the drain of the twenty-first MOS tube and the gate of the twenty-second MOS tube, the source of the twenty-first MOS tube and the source of the twenty-second MOS tube are grounded, and the drain of the twenty-second MOS tube is connected to the first branch voltage.

6. The system according to claim 5, characterized in that The first-stage inverting time-shift circuit is charged according to the first branch voltage, and when the first branch voltage is greater than a preset first threshold value and the current of the first-stage inverting time-shift circuit is greater than a first bias current, the first-stage inverting time-shift circuit outputs a low level; The second-stage inverting time shift circuit starts and discharges. When the second branch voltage of the second-stage inverting time shift circuit is pulled down to the second threshold, the third-stage inverting time shift circuit starts. Generating the pre-output clock signal specifically includes: The eighth MOS tube is charged according to the current of the first branch voltage; when the first branch voltage is greater than the first threshold, the tenth MOS tube is turned on, the thirteenth MOS tube is turned on, the second bias current of the fourteenth MOS tube is greater than the current of the eleventh MOS tube, the twelfth MOS tube is discharged, the second branch voltage is pulled down, and when the second branch voltage is pulled down to the second threshold, the pre-output clock signal is pulled down to a low level.

7. An on-chip oscillation method based on an on-chip oscillation system, characterized in that: The method comprises: The bias generating circuit processes the current at the power input terminal to generate a first bias voltage and a second bias voltage; the first bias voltage corresponds to a first bias current, and the second bias voltage corresponds to a second bias current; The start-up circuit receives the first bias voltage, and when the enable signal inputted at the enable terminal is flipped to a high level, starts charging according to the first bias voltage and generates a first branch voltage for charging; Oscillation generating circuit The oscillation generating circuit comprises a first-stage inverting time shift circuit, a second-stage inverting time shift circuit and a third-stage inverting time shift circuit. The first-stage inverting time shift circuit is charged according to the first branch voltage. When the first branch voltage rises to be greater than a preset first threshold value and the current of the first-stage inverting time shift circuit is greater than a first bias current, the first-stage inverting time shift circuit outputs a low level. The second-stage inverting time shift circuit is started and discharged. When the second branch voltage of the second-stage inverting time shift circuit is pulled down to the second threshold value, the third-stage inverting time shift circuit is started to generate a pre-output clock signal. After receiving the pre-output clock signal, the clock output circuit generates a pull-up clock signal, pulls up and shapes the pre-output clock signal according to the pull-up clock signal, generates an inverted discharge signal, pulls the first branch voltage down to the ground potential through the inverted discharge signal, inverts the first branch voltage and the pre-output clock signal, and outputs a clock signal.

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