An electronic countermeasure system integrating transmission and reception

Abstract

The present invention discloses an electronic countermeasure system with integrated transceiver, and relates to the field of radio frequency technology. The signal processor of the present invention includes a data receiving and sending unit, a data processing and main control unit, and a clock management unit, wherein the data processing and main control unit are respectively connected to the data receiving and sending unit and the clock management unit; the data receiving and sending unit includes multiple synchronously working integrated transceiver chips, and the multiple integrated transceiver chips realize beam synthesis by setting multiple independent local oscillators or by setting multiple identical local oscillators; the data processing and main control unit is composed of multiple FPGAs; the clock management unit includes a clock generation module and a clock synchronization module, and the clock synchronization module is used for inter-board synchronization and intra-board synchronization. The present invention integrates the functions of reconnaissance, direction finding, interference, etc. through multi-chip synchronous acquisition, bandwidth splicing and FPGA technology, which greatly simplifies the design difficulty of traditional superheterodyne architecture receivers, greatly reduces the design cost, and expands the scope of application.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency technology, and in particular to an electronic countermeasure system integrating transmission and reception. Background Art

[0002] With the continuous development of information technology, electromagnetic information is becoming more and more complex. Electronic countermeasure systems are generally composed of electronic reconnaissance equipment and electronic jamming equipment. The reconnaissance equipment directly searches for electromagnetic wave signals emitted by the target, detects the existence of the target, and then measures its direction, signal frequency and information. Finally, according to the information, the target is interfered. Electronic systems are constantly developing in the direction of complexity, miniaturization and digitization. Therefore, the requirements for electronic countermeasure systems are getting higher and higher. Separate reconnaissance and jamming tasks can no longer meet the complex requirements of confrontation. Electronic countermeasures are developing towards integrated reconnaissance and jamming, multi-task and multi-function. Separate reconnaissance and jamming tasks can no longer meet the complex requirements of confrontation. Large frequency band coverage, large bandwidth fast scanning and reconnaissance are required, and at the same time, they have the functions of jamming, reconnaissance, and direction finding. How to quickly and efficiently realize signal reconnaissance and identification within the frequency band and find the direction of the target so that the target interference confrontation can be quickly carried out has become the focus of system design. Highly flexible, software configurable, low-cost, and domestically produced electronic countermeasure systems are receiving more and more attention.

[0003] Receivers and transmitters, as the core parts of electronic reconnaissance equipment, are related to the performance of the entire system. For high-frequency and high-bandwidth electronic receivers, superheterodyne structures or digital intermediate frequency structures are usually used. For superheterodyne structures, there are defects such as complex design, low integration, high filter requirements and high cost. Therefore, many solutions now use digital intermediate frequency structures. The digital intermediate frequency structure first converts the analog RF signal to a broadband intermediate frequency, and then samples it through a high-bandwidth ADC (analog-to-digital converter). This requires very high ADC performance and very high data transmission rate. The back-end processing also requires high-end FPGA. If multi-channel direction finding and anti-interference functions are added, the system becomes complex, expensive and high power consumption. Summary of the invention

[0004] The purpose of the present invention is to overcome the technical problems existing in the prior art and provide an integrated transceiver electronic countermeasure system, so that the electronic countermeasure system can realize the integration of reconnaissance, direction finding, interference and other functions in a software-based and multifunctional manner, and the design platform configuration is more flexible, the frequency band switching is more convenient, and the scope of application is wider.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] Provided is an electronic countermeasure system with integrated transmission and reception, comprising a broadband reconnaissance receiver, a direction-finding receiver, a jammer and a signal processor, wherein the signal processor is connected to the broadband reconnaissance receiver, the direction-finding receiver and the jammer respectively;

[0007] The signal processor includes a data receiving and sending unit, a data processing and main control unit and a clock management unit, and the data processing and main control unit are connected to the data receiving and sending unit and the clock management unit respectively; the data receiving and sending unit includes multiple synchronously working transceiver chips, and the multiple transceiver chips realize beam synthesis by setting multiple independent local oscillators or by setting multiple identical local oscillators; the data processing and main control unit is composed of multiple FPGAs, which at least completes the functions of data receiving and sending and processing, and peripheral chip configuration management; the clock management unit includes a clock generation module and a clock synchronization module, and the clock synchronization module is used for inter-board synchronization and intra-board synchronization.

[0008] In some embodiments, the data receiving and sending unit includes 4 integrated transceiver chips, 8 independent local oscillators are set through the 4 integrated transceiver chips, and they are spliced ​​into a 1600MHz broadband signal through synchronous acquisition and transmission technology to complete broadband reconnaissance and frequency measurement; or 8 identical local oscillators are set through 4 integrated transceiver chips, and a 16-element RF antenna array is used to complete beam synthesis for reconnaissance and direction finding.

[0009] In some embodiments, the data processing and main control unit includes three FPGAs, which are defined as FPGA1, FPGA2 and FPGA3 respectively, wherein FPGA1 completes data transmission and reception and data preprocessing between the transceiver chip, FPGA2 completes part of the transmission and reception data processing, and FPGA3 completes peripheral chip configuration management and program loading of FPGA1 and FPGA2.

[0010] In some embodiments, the model of FPGA1 is JFM7VX690T80, the model of FPGA2 is JFM7VX690T80, and the model of FPGA3 is JFM7K325T8.

[0011] In some embodiments, the clock generation module uses the 100 MHz clock provided by the system as a clock source, and outputs a 100 MHz clock through a built-in clock distributor to provide clocks for multiple FPGAs of the data processing and main control unit.

[0012] In some embodiments, the clock generation module uses a 25 MHz crystal oscillator or a 25 MHz clock provided by an external clock source connector (LRM connector for short) as a clock source to provide clocks for the multiple FPGAs.

[0013] In some embodiments, the clock synchronization module includes a synchronization signal generating unit and an adjustable delay circuit, wherein the synchronization signal generating unit is used to receive an externally input synchronization signal and provide a synchronization signal for multiple FPGAs and a clock generation module; the adjustable delay circuit is used to adjust the delay value of the synchronization signal output by the synchronization signal generating unit.

[0014] Preferably, the synchronization signal generating unit comprises a clock generator.

[0015] In some embodiments, the adjustable delay circuit adjusts the delay value of the synchronization signal output by the synchronization signal generating unit, including:

[0016] Time-to-Digital Converters (TDC) chips are used to measure the time difference between the synchronization signal output by the clock manager (such as a dual-loop integer N-division jitter attenuator) and the system reference event SYSREF signal generated after hard synchronization of the clock generator. The stable range of the synchronization signal is obtained by repeatedly adjusting the delay value of the SYSREF signal output by the clock generator.

[0017] In some embodiments, it also includes a display control device, a storage device and a power supply device respectively connected to the signal processor.

[0018] It should be further explained that the technical features corresponding to the above options can be combined or replaced with each other to form a new technical solution if there is no conflict.

[0019] Compared with the prior art, the technical solution provided by the present invention brings at least the following beneficial effects:

[0020] (1) The present invention can achieve performance indicators (mainly bandwidth) far exceeding those of a single device through multi-chip synchronous acquisition, bandwidth splicing, adjustable independent local oscillator (LO) and FPGA technology, greatly simplifying the design difficulty of traditional superheterodyne architecture receivers, and greatly reducing design costs, power consumption and system size. At the same time, it expands the scope of application. Specifically, four integrated transceiver chips are used to work synchronously, and the software configures the radio frequency to collect and transmit 200MHz~6000MHz signals, with a maximum instantaneous bandwidth of 1600MHz. The integrated transceiver chip has the advantages of high integration of integrated transceiver, low power consumption, wide coverage frequency band, and low cost, providing a platform support for the hardware implementation of the electronic countermeasure system. The electronic countermeasure system is designed using software radio technology and radio frequency software technology, so that the electronic countermeasure system can realize the integration of reconnaissance, direction finding, interference and other functions in a software-based and multifunctional manner, and the design platform configuration is more flexible, the frequency band switching is more convenient, and the scope of application is wider.

[0021] (2) The present invention uses FPGA devices to realize parallel data processing and flexible development of high-speed interfaces. Since the hardware of the present invention supports the coverage of 1600MHz bandwidth signals, the data processing volume is huge, and non-FPGA devices cannot complete the related work. At the same time, FPGA devices can be used to realize customized broadband signal applications, such as reconnaissance, lateral and interference.

[0022] (3) The present invention adjusts the delay value of the synchronization signal output by the synchronization signal generating unit through an adjustable delay circuit, obtains the stable interval of the synchronization signal, realizes synchronization between system boards and within the board, and ensures sampling stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of an electronic countermeasure system with integrated transmission and reception according to an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a signal processing machine shown as an embodiment of the present invention;

[0026] Figure 3 A circuit diagram of a clock generation module according to an embodiment of the present invention;

[0027] Figure 4 A circuit diagram of a clock synchronization module according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of a synchronization signal stability interval shown in an embodiment of the present invention;

[0029] Figure 6 A circuit diagram of a data receiving and sending unit shown in an embodiment of the present invention;

[0030] Figure 7 This is a circuit diagram of a data processing and main control unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention is clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various configurations. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0032] In view of the technical problems pointed out in the background technology, the embodiments provided by the present invention are as follows:

[0033] In an exemplary embodiment, a specific design process of a transceiver-integrated electronic countermeasure system is provided, and specific design parameters of the system are as follows:

[0034] Working frequency: receiving 200MHz~6000MHz; transmitting 200MHz~6000MHz;

[0035] Maximum instantaneous bandwidth: 1600MHz for reception; 1600MHz for transmission;

[0036] Maximum number of channels: 16 for receiving and 16 for transmitting;

[0037] Analog-to-digital converter (ADC) spurious-free dynamic range: ≥60dBFS; digital-to-analog converter (DAC) spurious suppression: ≥50dB.

[0038] The electronic countermeasure system provided in this embodiment is composed of: Figure 1 As shown, it includes a broadband reconnaissance receiver, a direction-finding receiver, an interference transmitter and a signal processor. The signal processor is connected to the broadband reconnaissance receiver, the direction-finding receiver and the interference transmitter respectively. The signal processor integrates reception, direction-finding and transmission and can switch between multiple functions and multiple tasks. The broadband reconnaissance receiver receives signals through a frequency-measuring antenna, and the direction-finding receiver receives signals through a direction-finding antenna. The received signals are processed by a signal extension and sent to the signal processor. After the signal is processed by the signal processor, frequency measurement and direction-finding can be performed according to the processing results. When an interference signal needs to be transmitted, the interference is transmitted through the interference antenna by switching to the interference transmitter. In addition, it also includes a display and control device, a storage device and a power supply device respectively connected to the signal processor. The display and control device is an operation interface for user debugging, the storage device is used to store the loading program required by the signal processor and the data processed by the signal processor, and the power supply device is used to supply power to the signal post-processor and manage the power supply.

[0039] The system uses 4 integrated transceiver chips (such as ADRV9026 chips) to synchronously collect 200MHz~6000MHz RF signals. Through the 4 integrated transceiver chips, 8 independent local oscillators can be quickly and arbitrarily set by software. Through synchronous acquisition and transmission technology, they can be spliced ​​into 1600MHz wideband signals to complete broadband reconnaissance and frequency measurement. It is also possible to set 8 identical local oscillators with 4 integrated transceiver chips, and the 16-element RF antenna array can complete beam synthesis for reconnaissance and direction finding. Therefore, the design can be used for broadband reconnaissance, quickly scanning all signals in the 200MHz~6000MHz frequency band, and at the same time has broadband transmission as broadband noise interference. It can also be used for multi-channel digital beam synthesis for target direction finding, etc. Therefore, the integrated transceiver electronic countermeasure system has software-based, broadband frequency band reconnaissance, interference, direction finding and other multi-task functions. Its overall principle block diagram is as follows Figure 2 As shown, the specific design of the data receiving and sending unit, the data processing and main control unit, and the clock management unit of the electronic countermeasure system with an integrated transceiver provided in this embodiment is described in detail as follows:

[0040] (1) Clock management unit design

[0041] The board is equipped with a phase-locked loop: it can lock with the external reference clock and output 50MHz, 125MHz, and 156.25MHz clocks. For single-board debugging, the board's 25MHz clock can be used.

[0042] See also Figure 2 and Figure 3 The clock generation module mainly uses the 100MHz clock provided by the system (external clock, such as provided by symmetrical processing SMP) or the internal crystal oscillator 122.88MHz as the clock source. Then it outputs 100MHz or 122.88MHz clocks through the clock distributor (chip GMH1208 can be used), of which 3 are given to FPGA1, FPGA2, and FPGA3 as system clocks; 1 is output through the clock generator (chip GM4526CN can be used) to output 3 clock signals (CLK) to FPGA1, FPGA2, and FPGA3 respectively; 1 is given to the clock manager (chip HMC7044 can be used), and the reference clock (GTH CLK) of the high-speed transceiver (GTH) of FPGA1 and FPGA2 is generated through the clock manager, that is, the GTH reference clock output by the clock manager is distributed through the clock driver (chip GMD950C can be used) and enters FPGA1 and FPGA2, thereby obtaining 6 GTH CLKs of FPGA1 and FPGA2, such as Figure 3As shown, the clock manager also sends the system reference event (SYSREF) signal and the data clock signal (CORE CLK) to FPGA1. In addition, the output clock of the clock generator is also connected to the time measurement device (the chip GMDGP22 can be used) to realize synchronization detection; and the clock manager also sends the SYSREF signal generated after hard synchronization to the time measurement device, so that the time difference between the synchronization signal after the synchronization signal is output by the clock generator and the SYSREF signal generated after hard synchronization of the clock manager can be measured by the TDC chip. At the same time, the system clock can also be provided to the SRIO (Serial RapidIO Interface) switching chip through the clock selection distributor (the chip GMD00804 can be used) or through another clock manager (such as HMC7044), so as to realize the data exchange and transmission based on the SRIO protocol between the three FPGAs (FPGA1, FPGA2, FPGA3) and the LRM connector based on the SRIO switching chip. Among them, the LRM connector is connected to the clock generator through a clock driver (chip GMD946C can be used); the clock source of the clock manager / clock selection distributor can be provided by a 25MHz crystal oscillator or a 25MHz clock provided by the LRM connector, and then connected to the FPGA clock pin (such as the MRCC pin) of FPGA3 through the clock manager or clock selection distributor for external 25MHz detection. When there is an external 25MHz input, the external clock is used first. When there is no external 25MHz, it is switched to the internal 25MHz through FPGA control. Preferably, in this embodiment, the device model of the LRM connector is LRMX-A144T9G2-B144H2BT9R-AT-MZ.

[0043] Clock synchronization is the key to multi-channel data synchronization. In this embodiment, the clock signal is automatically detected first. When the external reference clock is detected to be locked, the external input 100MHz clock is used for frequency multiplication and phase locking to generate a 240MHz system clock for signal processing. When no external input clock is detected, it automatically switches to the internal clock 122.88MHz for frequency multiplication and phase locking to generate a 245.76MHz system clock for signal processing. Since the phase relationship between the two clock signals and the relationship between the input and output frequency multiples are different, and the channel synchronization relationship needs to remain unchanged, it is necessary to adaptively adjust the phase to ensure synchronization between channels. The system synchronization method uses a synchronization signal to trigger the clock chip for clock synchronization. Specifically, see Figure 4The clock synchronization module receives the external input synchronization signal (SYNC signal) based on the LRM connector, and then outputs 5 SYNC signals after the clock generator, of which 3 are used for related processing by 3 FPGAs, 1 is used for clock synchronization by the clock manager (i.e., clock signals (CLK) and SYSREF signals are distributed to 4 transceiver chips respectively), and 1 is used for synchronization detection by the time measurement device (GMDGP22 chip can be used). The clock manager also sends the SYSREF signal to the time measurement device.

[0044] Due to the different frequencies and phases of the external clock signal and the internal crystal oscillator, the on-board delays are different, and there may be a timing competition between the synchronization signal and the rising edge of the input clock of the clock manager, resulting in sampling metastable state. Therefore, the embodiment of the present invention uses a TDC chip to measure the time difference between the SYNC signal after the SYNC is output by the clock generator and the SYSREF signal generated after the clock manager is hard synchronized. The FPGA can obtain the delay value of the SYNC signal output by the automatic scanning configuration clock generator, such as Figure 5 The stable interval of the synchronization signal shown, Figure 5 Where T_start represents the start time, the ordinate is the measured time difference, the unit is ns, and the abscissa is the delay time, the unit is ps. The FPGA software automatically analyzes the boundary position of the unstable interval, such as Figure 5 The area where the steep curve after T_start+1200ps is located corresponds to Figure 5 The interval corresponding to the two dotted lines in is the unstable interval, and then the corresponding boundary position is obtained, and then 2ns delay is added or reduced at the boundary position as the stable position. The entire synchronization process can be automatically trained by the FPGA software. Whether it is an external clock or an internal clock, it can be automatically matched to form a closed-loop synchronization system. Many synchronization systems use manual measurement and then configure delay parameters. Different frequencies lead to completely different results, and are also affected by the high and low temperatures of the environment, resulting in complex system synchronization. This closed-loop synchronization system is not affected by the high and low temperatures of the environment. Under different environments, it automatically generates the best synchronization state to ensure synchronization between channels.

[0045] In order to ensure the relationship between the on-board synchronization signal and the sampling clock, this embodiment uses the TDC function inside the transceiver chip to measure the relative time relationship between the rising edge of the SYSREF signal and the rising edge of the sampling clock, and adjusts the delay of the SYSREF signal through the clock manager. The following can also be obtained: Figure 5 The stable interval of the synchronization signal shown in FIG. 1 is achieved by setting the delay value of the SYSREF signal output by the clock manager to ensure that the sampling clock is in a stable sampling interval, thereby achieving on-board sampling synchronization of multiple transceiver chips.

[0046] (2) Data receiving and sending unit design

[0047] See also Figure 2 and Figure 6 The signal acquisition function of the data receiving and transmitting unit provided in the embodiment of the present invention has a 16-channel sampling capability and is connected to FPGA1, that is, each transceiver chip interacts with FPGA1 through 4 high-speed interfaces (Serders) to realize data transmission of control signals and synchronization signals; the signal generation function has an 8-channel signal generation capability; the analog-to-digital converter (ADC) signal acquisition and the digital-to-analog converter (DAC) signal generation both meet inter-board synchronization; the receiving and transmitting frequency range is 200 MHz ~6000MHz, the maximum instantaneous bandwidth is 1600MHz, and a zero intermediate frequency RF transceiver is used. The transceiver chip of the corresponding chip model can be selected based on the actual application requirements to complete this function. The transceiver chip used in this embodiment is a highly integrated radio frequency (RF) agile transceiver, which provides four independently controlled transmitters, a dedicated observation receiver input for monitoring each transmitter channel, four independently controlled receivers, an integrated frequency synthesizer and digital signal processing functions, forming a complete transceiver solution. The data receive and transmit units provide the performance required for a variety of cellular infrastructure applications, such as small cell base station radios, 3G / 4G / 5G macro systems and massive multiple-input / multiple-output (MIMO) base stations.

[0048] The four independently controlled receivers of the data receiving and transmitting unit provided in this embodiment are independent wide bandwidth direct conversion receivers with wide dynamic range. The four independent transmitters use direct conversion modulators to achieve low noise operation at low power consumption. The data receiving and transmitting unit also includes two wide bandwidth time-sharing observation path receivers, each receiver having two inputs for monitoring the transmitter output.

[0049] The transceiver subsystem (four independently controlled transmitters, dedicated observation receiver input, four independently controlled receivers) of the data receiving and transmitting unit provided in this embodiment includes automatic and manual attenuation control, DC offset correction, orthogonal error correction (QEC), and digital filtering functions, thereby reducing the complexity of digital baseband processing.

[0050] The data receiving and sending unit provided in this embodiment also integrates an ADC, a DAC, and a general purpose input / output (GPIO) interface for providing various digital control options.

[0051] To achieve high RF performance levels, the data receiving and transmitting units of this embodiment include five fully integrated phase-locked loops (PLLs). Two PLLs provide low-noise and low-power fractional-N RF frequency synthesis for the transmitter and receiver signal paths. The third fully integrated PLL supports the independent local oscillator (LO) mode of the observation receiver. The fourth PLL can generate the clocks required for the converter and digital circuits, and the fifth PLL can provide the clock for the serial data interface.

[0052] The multi-chip synchronization mechanism can synchronize all LO phases and baseband clocks between multiple transceiver chips. All voltage-controlled oscillators (VCOs) and loop filter components are integrated and can be adjusted through a digital control interface.

[0053] The serial data interface of the transceiver chip includes four serializer channels and four deserializer channels. The interface supports the high-speed serial interface standards JESD204B and JESD204C, and can operate at data rates up to 24.33 Gbps. The serial data interface also supports interleaving mode for lower bandwidth, reducing the number of high-speed data interface channels to 1. Fixed and floating-point data formats are supported. The floating-point format makes the internal automatic gain control (AGC) invisible to the demodulator device.

[0054] (3) Data processing and main control unit design

[0055] See also Figure 2 and Figure 7, the data processing and main control unit includes three FPGAs and a main control unit composed of a microcontroller MCU. In this embodiment, the specific selection of the three FPGAs is: 1 JFM7VX690T80 (FPGA1), 1 JFM7VX690T80 (FPGA2) and 1 JFM7K325T8 (FPGA3). Each FPGA is configured with flash memory FLASH and 4 DDR3L memories. Among them, FPGA1 mainly completes data transmission and reception and data preprocessing with the transceiver chip; FPGA2 also completes part of the transceiver data processing. FPGA3 mainly completes peripheral chip configuration management, as well as FPGA1 and FPGA2 program loading. Among them, MCU uses FPGA3 as the main control unit to realize system control, such as the device startup sequence and global reset of the data receiving and sending unit, data processing and main control unit and clock management unit. In this embodiment, the processed received data is transmitted through the LRM connector using GTH / SRIO; similarly, the data input by GTH / SRIO to FPGA1 and FPGA2 through the LRM connector is processed and transmitted and output through the transceiver chip. FPGA3 is mainly used for the configuration and control functions of FPGA1 and FPGA2. In this embodiment, the single-chip microcomputer model of MCU adopts GD32F405VKT6, which can use 8MHz crystal oscillator as clock source to provide clock for MCU. MCU is used to control the device startup sequence of data receiving and sending unit, data processing and main control unit and clock management unit, as well as voltage monitoring and global reset. Preferably, in this embodiment, MCU realizes serial communication of bus through controller area network (CAN) transceiver (such as chip SN65HVD230D) and LRM connector, and LRM connector is also connected to MCU through CMOS (Complementary Metal-Oxide-Semiconductor) monitoring circuit (such as MAX706 monitoring circuit) to monitor power supply voltage, battery failure and working status of microprocessor. In addition, power supply and power management of the electronic countermeasure system with integrated transceiver provided in this embodiment can also be realized through the power management unit connected to the LRM connector. In this embodiment, FPGA3 is also connected to the LRM connector through an Ethernet transceiver communicator (which can use the chip SM88E1111) and a network transformer (such as LT5120A) to achieve network transmission of data, wherein the Ethernet transceiver communicator is used to send a Gigabit Ethernet interface (SGMII) clock to FPGA3, and a 4-way Ethernet port connection using twisted pair cables, such as MDI, is configured between the network transformer and the Ethernet transceiver communicator. In addition, in the embodiment of the present invention, the MCU and the three FPGAs are externally controlled through a debugging interface (the interface device model can be J63A-2F2-065-441-TH) to achieve functions such as data communication and status reporting.

[0056] See also Figure 7 , 16-way transceiver channels are used for data exchange between FPGA1 and the ADC module and DAC module, 8-way transceiver channels are used between FPGA1 and the LRM connector, and 16-way transceiver channels are used for data exchange between FPGA1 and FPGA2. FPGA1 is also connected to the RapidIO serial port through 4-way transceiver channels, and high-speed data interaction with the LRM connector, FPGA2 and FPGA3 is realized based on the RapidIO serial port; among them, all three FPGAs are connected to the RapidIO serial port through 4-way transceiver channels. FPGA2 is connected to the LRM connector through 8-way transceiver channels, and inter-chip data interaction is realized between FPGA2 and FPGA3, and between FPGA1 and FPGA3 through low voltage differential signals (LVDS). The MCU connected to the LRM connector can be used to realize the switch reset of the system. It should be noted that Figure 7 The R and T after the number are used to represent the receiving channel and the transmitting channel respectively.

[0057] The internal data processing of the transceiver integrated electronic countermeasure system provided by the embodiment of the present invention adopts a single module and multi-function mode. Multiple versions of programs are stored in the FLASH of each FPGA, and different versions of functional programs are dynamically loaded from the FLASH through commands to switch between different tasks. Including broadband reconnaissance mode, 8 channels of 200MHz width data are processed in parallel internally to synthesize 1.6GHz broadband signals to detect and search targets. When the target is detected, the direction finding mode is dynamically loaded, and beam synthesis is performed by receiving 16-channel array elements to form sum and difference beams for direction finding. The target direction is measured and the target interference is performed. The interference signal can generate a variety of interference modes according to the target information, including smart noise interference (i.e. flexible noise interference), deception interference, forwarding interference, intensive false interference, etc. Through program switching, the single module multi-function is realized. Compared with traditional modules, it has small size, low power consumption and powerful functions. For small space devices such as drones and seekers, it has irreplaceable advantages.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0059] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An integrated electronic countermeasure system, characterized in that: It includes a broadband reconnaissance receiver, a direction-finding receiver, an interference transmitter and a signal processor, wherein the signal processor is connected to the broadband reconnaissance receiver, the direction-finding receiver and the interference transmitter respectively; The signal processor includes a data receiving and sending unit, a data processing and main control unit and a clock management unit; the data receiving and sending unit includes multiple synchronously working transceiver integrated chips, and the multiple transceiver integrated chips realize beam synthesis by setting multiple independent local oscillators or by setting multiple identical local oscillators; the data processing and main control unit is composed of multiple FPGAs, which at least completes the functions of data receiving and sending and processing, and peripheral chip configuration management; the clock management unit includes a clock generation module and a clock synchronization module, and the clock synchronization module is used for inter-board synchronization and intra-board synchronization; The data receiving and sending unit includes 4 integrated transceiver chips, 8 independent local oscillators are set through the 4 integrated transceiver chips, and spliced ​​into a 1600MHz broadband signal through synchronous acquisition and transmission technology to complete broadband reconnaissance and frequency measurement; or 8 identical local oscillators are set through 4 integrated transceiver chips, and a 16-element radio frequency antenna array is used to complete beam synthesis for reconnaissance and direction finding; The data processing and main control unit includes three FPGAs, which are defined as FPGA1, FPGA2 and FPGA3 respectively, wherein FPGA1 completes data transmission and reception and data preprocessing between the transceiver chip, FPGA2 completes part of the transceiver data processing, and FPGA3 completes peripheral chip configuration management and program loading of FPGA1 and FPGA2; The clock synchronization module includes a synchronization signal generating unit and an adjustable delay circuit, wherein the synchronization signal generating unit is used to receive an externally input synchronization signal and provide synchronization signals for multiple FPGAs and clock generation modules; the synchronization signal generating unit includes a clock generator, and the adjustable delay circuit is used to adjust the delay value of the synchronization signal output by the synchronization signal generating unit; the adjustable delay circuit adjusts the delay value of the synchronization signal output by the synchronization signal generating unit, including: The time-to-digital conversion chip is used to measure the time difference between the synchronization signal after the external synchronization signal passes through the clock generator output and the system reference event SYSREF signal generated after the clock manager is hard synchronized. By adjusting the delay value of the SYSREF signal output by the clock generator multiple times, the stable interval of the synchronization signal is obtained. The clock generation module uses the 100MHz clock provided by the system as the clock source, and outputs the 100MHz clock through the built-in clock distributor to provide clocks for the multiple FPGAs of the data processing and main control unit; or the clock generation module uses a 25MHz crystal oscillator or a 25MHz clock provided by an external clock source connector as the clock source to provide clocks for the multiple FPGAs; when it is detected that the external reference clock is locked, the external input clock is used for frequency multiplication and phase locking to generate a system clock for signal processing; when no external input clock is detected, it automatically switches to the internal clock for frequency multiplication and phase locking to generate a system clock for signal processing; the clock manager also sends the system reference event signal generated after hard synchronization to the time measurer, so as to measure the time difference between the synchronization signal after the synchronization signal is output by the clock generator and the system clock signal generated by the clock manager after hard synchronization through the time measurer; the FPGA obtains the stable interval of the synchronization signal by automatically scanning the delay value of the synchronization signal output by the configuration clock generator: the FPGA software analyzes the boundary position, and increases or decreases the 2ns delay at the boundary position as the stable position.

2. The electronic countermeasure system according to claim 1, characterized in that: The model of FPGA1 is JFM7VX690T80, the model of FPGA2 is JFM7VX690T80, and the model of FPGA3 is JFM7K325T8.

3. The electronic countermeasure system according to claim 1, characterized in that: It also includes display and control equipment, storage equipment and power supply equipment which are respectively connected with the signal processor.

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