CPU (Central Processing Unit) butterfly network computing method

Abstract

The invention discloses a CPU (central processing unit) butterfly network computing method, which relates to the field of network computing and comprises a butterfly network optimization step, a butterfly algorithm optimization step and an SIMD (single instruction multiple data) optimization step. The butterfly network optimization comprises the following steps of: on the basis of an iterative Stockham FFT (Fast Fourier Transform) calculation framework, combining calculation kernels by using a Cooley-Tukey FFT algorithm so as to improve the performance of the butterfly network; the butterfly algorithm optimization comprises the following steps: extracting a common item of a butterfly calculation formula, and simplifying large-base butterfly calculation for butterfly algorithm optimization; the SIMD optimization comprises the following steps: optimizing an SIMD assembly instruction, designing a register multiplexing strategy and a stack memory use mode, and relieving the memory access pressure of large-base butterfly computation by utilizing a memory. Through the scheme, the instructions with low delay and high throughput are screened, the instruction processing speed is increased, and the efficiency of processing data by operation resources is improved through register multiplexing.

Description

Technical Field

[0001] The present application relates to the field of network computing, and in particular to a CPU butterfly network computing method, a CPU butterfly network computing device, an electronic device, a storage medium, and a vehicle CPU operating platform. Background Art

[0002] Fast Fourier Transform (FFT) has greatly promoted the development of digital signal processing technology. For example, the FFT algorithm significantly reduces the amount of calculation required by utilizing the symmetry properties of the DFT operation, making the time complexity of the algorithm from O(n 2 ) is reduced to O(nlogn), making the application of real-time digital signal processing a reality.

[0003] In smart cockpit application cases, the FFT algorithm plays a vital role. For example, in audio processing, FFT is used to achieve sound equalization, noise suppression, and simulated surround sound effects. In radar and sensor technology, the FFT algorithm is used to analyze and process sensor data to detect the vehicle's surrounding environment and provide decision support for the driver assistance system. For example, in the field of wireless communications, FFT also plays a key role. It is used in scenarios such as in-vehicle Internet access, vehicle-to-vehicle communication (V2V), and vehicle-to-infrastructure communication (V2I) to optimize communication efficiency and improve data transmission reliability.

[0004] For a one-dimensional input sequence with a data size of N, the DFT calculation formula is as follows:

[0005]

[0006] in, is called the rotation factor, e ix =cosx+isinx,i= Is an imaginary unit.

[0007] From the DFT transformation formula, we know that the calculation of each X(k) requires N complex multiplications and (N-1) complex additions, so we need to find the N-term complex sequence X(k), that is, it takes about N complex multiplications and (N-1) complex additions to realize the N-point DFT transformation. 2 The time complexity of the algorithm is O(n 2 ). When N is large, the computational cost is too high.

[0008] FFT is a fast algorithm of DFT, which mainly uses the characteristics of rotation factors to reduce the amount of calculation.

[0009] For example, symmetry: Periodicity: Availability: Special points:

[0010] For a sequence with an input length of N, if N can be decomposed into the product of N1 and N2, that is, N = N1 × N2, then the calculation of the N-point one-dimensional FFT can be decomposed into small-scale one-dimensional FFT problems of N1 and N2 points (divide and conquer method). The specific calculation steps are: (1) calculate N2 N1-point FFTs; (2) multiply each element by a rotation factor; (3) calculate N1 N2-point FFTs; (4) transpose the two-dimensional array to obtain ordered calculation results.

[0011] The minimum number of elements in the divided subsequence is called the radix. For example, in radix-2 FFT, N (assuming N = 2 k , and k is an integer) sequence is decomposed into two N / 2 point sequences (odd sequence and even sequence) according to the divide-and-conquer idea, and the FFT of the original N point sequence is obtained by calculating the FFT of these two N / 2 point sequences. Then the decomposition is performed recursively until the last level is decomposed into a 2-point sequence.

[0012] Assume that there is an input sequence x=[x0,x1,…,x7] with a one-dimensional length of 8. According to the Cooley-Tukey FFT algorithm, the subscripts are first divided into odd and even sequences, and the division stops when the minimum sequence length is 2. The division result is as follows: Figure 3 shown.

[0013] The subscript numbers of the original sequence and the partitioned sequence are "symmetrical", that is, the "bit flip" phenomenon. Each subsequence is recursively split until a 2-point sequence is generated. When the operation is simplified to the optimal level through the rotation factor characteristics, the calculation process can be represented by a butterfly-shaped flowchart, that is, a butterfly operation diagram, such as Figure 4 shown.

[0014] Figure 4 In the formula, G(k) and H(k) represent the even sequence and odd sequence of the N-point DFT sequence X(k) of x(n), respectively.

[0015] In the vehicle industry, with the continuous advancement of automation and intelligent functions, the tasks undertaken by vehicle computer systems have become more complex and diverse. These tasks include not only basic vehicle control and monitoring, but may also involve advanced data processing, decision-making, real-time communication and environmental perception. The problems that cars with automation and intelligent functions need to deal with are becoming more and more complex, which puts higher requirements on the real-time computing performance (higher efficiency) of vehicle computers.

[0016] For example, the current mainstream car computers use Qualcomm Snapdragon 8155 and 8295, which use the ARMv8 architecture. The ARMv8 architecture supports the AArch64 execution state and introduces 64-bit wide registers for the first time. However, making full use of the features of ARMv8 and its SIMD instructions requires specific optimization of the FFT algorithm to adapt to the characteristics of the new architecture.

[0017] Previous research and achievements focused on optimizing FFT using a large number of accelerator platforms (accelerators refer to accelerated computing devices such as GPUs and FPGAs). Although this has high computational efficiency, it also consumes more power and is not a common solution in vehicle systems. More vehicle systems use CPUs for calculations, but due to limitations in instruction-level parallelism and power consumption, the results are often not ideal. The unique mathematical properties of FFT still cause problems in its implementation and optimization on, for example, ARMv8:

[0018] 1. In the Cooley-Tukey FFT algorithm, which is currently the most widely used and popular fast Fourier algorithm, there are still problems such as complex butterfly networks and complex and diverse butterfly calculations. Especially for the implementation of large radix (refer to the definition of "radix" above, large radix means that the smallest sequence divided is relatively large, small radix means relatively small, radix-2 above is a small radix, radix-14 below is a large radix, and it is generally believed that the smallest sequence with more than 8 elements is a large radix), although the large radix improves performance by reducing memory access, the large radix butterfly implementation still has problems such as complex assembly implementation and insufficient registers.

[0019] 2. Most FFT math libraries use small basis algorithms, which are more flexible and easier to implement, but also require a large number of calculations. Using large basis FFT algorithms will bring better performance, but the implementation is more complicated and it is impossible to obtain relatively consistent optimization effects on FFTs of various sizes or multi-dimensional FFTs.

[0020] Therefore, a CPU butterfly network computing solution is needed to further improve the deficiencies based on, for example, the ARMv8 architecture or platform. Summary of the invention

[0021] The purpose of the present invention is to provide a CPU butterfly network computing method, a CPU butterfly network computing device, an electronic device, a storage medium and a vehicle CPU operating platform, which can at least solve one of the technical problems among the butterfly network optimization problem, the butterfly algorithm optimization problem and the SIMD optimization problem.

[0022] The present invention provides the following scheme:

[0023] According to one aspect of the present invention, a CPU butterfly network computing method is provided, based on an ARM architecture CPU, the CPU butterfly network computing method comprising:

[0024] The steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization;

[0025] The steps of butterfly network optimization include: merging the computing kernels with the Cooley-Tukey FFT algorithm based on the iterative Stockham FFT computing framework to improve the performance of the butterfly network;

[0026] The steps of butterfly algorithm optimization include extracting common items of butterfly calculation formulas, simplifying large-base butterfly calculations, and using them for butterfly algorithm optimization;

[0027] The SIMD optimization steps include optimizing SIMD assembly instructions, designing register reuse strategies and stack memory usage, and using memory to alleviate the memory access pressure of large-radix butterfly calculations.

[0028] Furthermore, the butterfly network optimization step includes merging the calculation kernels based on the iterative Stockham FFT calculation framework with the Cooley-Tukey FFT algorithm to improve the butterfly network performance, including:

[0029] Input natural sequence data into the butterfly network to obtain output data of the natural sequence;

[0030] Among them, the rotation factor of the first-level butterfly network is 1;

[0031] Among them, during the assembly stage, optimization is performed through data reorganization and transposition.

[0032] Furthermore, the step of optimizing the butterfly algorithm includes extracting common terms of the butterfly calculation formula, simplifying the large-base butterfly calculation, and using the butterfly algorithm optimization to include:

[0033] Applications based on radix-14FFT calculations;

[0034]

[0035] Among them, the rotation factors of the butterfly network have symmetry and periodicity;

[0036] According to the symmetry and periodicity of the rotation factor, we can calculate Three rotation factors, the remaining rotation factors are The real or imaginary part of the rotation factor is negated to obtain:

[0037]

[0038] Simplified, the butterfly network calculation formula of Radix-14 is:

[0039] X(0)=(x0-x7)+S0+S4+S8

[0040] X(7)=(x0+x7)+S5-S1-S9

[0041] X(1)=A+B

[0042] X(13)=AB

[0043] X(3)=C+D

[0044] X(11)=CD

[0045] X(5)=E+F

[0046] X(9)=EF

[0047] X(2)=G+H

[0048] X(12)=GH

[0049] X(4)=IJ

[0050] X(10)=I+J

[0051] X(6)=K+L

[0052] X(8)=KL

[0053] Among them, the time complexity of butterfly network calculation is reduced by extracting and pre-calculating common factors, reducing floating-point calculations and code redundancy.

[0054] Furthermore, the butterfly network calculation includes:

[0055] Read the input sequence, according to the preset step length r, read the input sequence x1~x with a length of r r-1 ;

[0056] Multiply by the rotation factor;

[0057] Among them, since the rotation factor of the first-level butterfly network is 1, the multiplication of the rotation factor in this stage is skipped;

[0058] Calculate the common factors of the butterfly network calculation formula and store A~L in the register;

[0059] Calculating the output sequence, including obtaining the output results in sequence according to the common factors and the calculation formula and storing them in the register;

[0060] Writes the output sequence and stores the results according to the output step size.

[0061] Furthermore, it also includes:

[0062] Based on the CPU having 32 128-bit floating-point registers, each floating-point register stores 4 32-bit single-precision floating-point numbers or 2 64-bit double-precision floating-point numbers. One instruction processes 4 data in parallel at the same time. Each butterfly calculation is independent of each other. SIMD optimization processes 4 butterfly calculations at the same time.

[0063] Among them, the optimization of registers is divided into two parts: register multiplexing and stack storage of temporary data;

[0064] Among them, the register-based optimization includes register multiplexing, which realizes independent processing of input data and rotation factor data by multiplexing the temporary register tmptw of the rotation factor;

[0065] When register resources are limited, a strategy of loading twiddle factors in batches is adopted, and the tmptw registers are continued to be used for data storage after the complex multiplication is completed.

[0066] Furthermore, it also includes:

[0067] Register-based optimizations include stack storage of temporary data;

[0068] Among them, by reusing the temporary input register tmpin, after loading part of the input data and calculating the intermediate variables, the register tmpin is released in time for reuse;

[0069] Among them, during the multiplication operation, the temporary register tmpout is reused in time, the data is immediately stored in the memory after the output result is calculated, and the temporary register tmpout is released for reuse.

[0070] Furthermore, it also includes:

[0071] Filter instructions with low latency and high throughput;

[0072] Among them, based on the ARMv8 platform under the ARM architecture, select the multiplication and addition, multiplication and subtraction instructions of fmla and fmls;

[0073] Among them, based on the support of ld2 and st2 load access instructions in ARM NEON, the ARMv8 platform under the ARM architecture uses ld2, faddp, and st2 instructions to perform complex arithmetic operations.

[0074] Furthermore, it also includes:

[0075] Determine whether there is a dependency relationship between adjacent instructions;

[0076] If,None, then instruction reordering is allowed;

[0077] Among them, according to the instruction reordering, the order of loading data is adjusted and the intermediate results are calculated in time;

[0078] After the intermediate results are calculated, the occupancy of register tmpin is released for reuse in outputting the intermediate results.

[0079] Furthermore, it also includes:

[0080] According to the steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization, multi-level butterfly operation is realized;

[0081] The multi-stage butterfly operation includes stride memory access, bit reversal, Wing operation and parallel processing.

[0082] Furthermore, it also includes:

[0083] Application based on radix-14FFT calculation, temporarily store common factors in stack, calculate output results and load them into registers;

[0084] Among them, the real and imaginary parts of the intermediate result scratch occupy 26 floating-point registers respectively;

[0085] Input data and rotation factors are loaded in pairs;

[0086] Among them, the input data is multiplied by the rotation factor and then loaded into the next pair of data to calculate the intermediate result, and the rotation factor and the input data reuse the same register;

[0087] Among them, after calculating the intermediate results, the registers occupied by the intermediate results are reused in the calculation process;

[0088] Among them, the butterfly calculation results are output in time and the occupied registers are released.

[0089] According to two aspects of the present invention, there is provided a CPU butterfly network computing device, the CPU butterfly network computing device comprising:

[0090] The step module is used to set the steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization;

[0091] The butterfly network optimization module includes the following steps for butterfly network optimization: based on the iterative Stockham FFT calculation framework, the Cooley-Tukey FFT algorithm is used to merge the calculation kernels to improve the butterfly network performance;

[0092] The butterfly algorithm optimization module is used for the butterfly algorithm optimization steps including extracting the common items of the butterfly calculation formula, simplifying the large-base butterfly calculation, and using it for the butterfly algorithm optimization;

[0093] SIMD optimization module, the steps for SIMD optimization include optimizing SIMD assembly instructions, designing register reuse strategies and stack memory usage, and using memory to alleviate the memory access pressure of large-radix butterfly calculations.

[0094] According to three aspects of the present invention, there is provided an electronic device, comprising: a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0095] The memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the CPU butterfly network computing method.

[0096] According to four aspects of the present invention, a computer-readable storage medium is provided, comprising: a computer program executable by an electronic device is stored therein, and when the computer program runs on the electronic device, the electronic device executes the steps of the CPU butterfly network computing method.

[0097] According to five aspects of the present invention, a vehicle CPU operation platform is provided, including:

[0098] An electronic device, used to implement the steps of the CPU butterfly network computing method;

[0099] A processor, wherein the processor runs a program, and when the program runs, the steps of the CPU butterfly network computing method are executed from the data output by the electronic device;

[0100] The storage medium is used to store a program, and when the program is running, the steps of the CPU butterfly network computing method are executed for the data output from the electronic device.

[0101] Through the above scheme, the following beneficial technical effects are obtained:

[0102] This application optimizes the performance of the butterfly network by merging the computing kernels with the Cooley-Tukey FFT algorithm based on the iterative Stockham FFT computing framework. The input data and output data of the butterfly network are both natural sequences. The input eliminates the "bit reversal" permutation operation, reduces the memory order adjustment operation, and improves the computing efficiency.

[0103] This application uses the symmetry and periodicity of the rotation factor to calculate Three rotation factors, the remaining rotation factors are The real or imaginary part of the rotation factor is inverted, which simplifies the calculation of the data.

[0104] This application accelerates instruction processing speed by screening instructions with low latency and high throughput, and improves the efficiency of computing resources in processing data through register multiplexing. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] Figure 1 It is a flow chart of a CPU butterfly network computing method provided by one or more embodiments of the present invention.

[0106] Figure 2 It is a structural diagram of a CPU butterfly network computing device provided by one or more embodiments of the present invention.

[0107] Figure 3 A schematic diagram of data sequence division according to a specific embodiment of the present invention.

[0108] Figure 4 A schematic diagram of a butterfly operation according to a specific embodiment of the present invention.

[0109] Figure 5 A schematic diagram of a radix-14 FFT calculation process according to a specific embodiment of the present invention.

[0110] Figure 6 A schematic diagram of a Stockham butterfly network according to a specific embodiment of the present invention.

[0111] Figure 7 A schematic diagram of SIMD instruction optimization according to a specific embodiment of the present invention.

[0112] Figure 8 A schematic diagram of instruction reordering according to a specific embodiment of the present invention.

[0113] Fig. 9 A structural block diagram of an electronic device of a CPU butterfly network computing method provided by one or more embodiments of the present invention. DETAILED DESCRIPTION

[0114] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0115] Figure 1 It is a flow chart of a CPU butterfly network computing method provided by one or more embodiments of the present invention.

[0116] like Figure 1 As shown, based on the ARM architecture CPU, the CPU butterfly network calculation method includes:

[0117] The steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization;

[0118] Step S1, the butterfly network optimization step includes: based on the iterative Stockham FFT calculation framework, merging the calculation kernels with the Cooley-Tukey FFT algorithm to improve the butterfly network performance;

[0119] Step S2, the step of butterfly algorithm optimization includes extracting common terms of butterfly calculation formulas, simplifying large-base butterfly calculations, and using them for butterfly algorithm optimization;

[0120] Step S3, SIMD optimization includes optimizing SIMD assembly instructions, designing register reuse strategies and stack memory usage, and using memory to alleviate memory access pressure of large-radix butterfly calculations.

[0121] Specifically, in this embodiment, a butterfly network computing framework is designed to efficiently decompose the problem scale. The framework is based on the iterative Stockham FFT computing framework, and the computing kernels are merged according to the Cooley-Tukey FFT algorithm to reduce the number of butterfly network levels, reduce memory access and improve the performance of the butterfly network; the DFT matrix properties are used to extract the common items of butterfly computing, and the large-based butterfly computing is simplified to facilitate CPU computing. In short, it is to improve computing efficiency and reduce computing time.

[0122] The butterfly calculation is implemented and optimized at the assembly level, and SIMD assembly instructions are optimized, register reuse strategies and stack memory usage are designed, and the memory characteristics are used to alleviate the memory access pressure caused by butterfly operations and solve the problem of insufficient registers for large base algorithms. The above steps improve the parallelism of the FFT algorithm and make full use of various storage resources to support special FFT operations.

[0123] Special operations include multi-stage butterfly operations, other similar stride memory access, bit reversal, Wing operation (complex multiplication), parallel processing, etc.

[0124] In this embodiment, the butterfly network optimization steps include: based on the iterative Stockham FFT calculation framework, merging the calculation kernels with the Cooley-Tukey FFT algorithm to improve the butterfly network performance, including:

[0125] The butterfly network is fed with natural sequence data;

[0126] Input natural sequence data into the butterfly network to obtain output data of the natural sequence;

[0127] Among them, the rotation factor of the first-level butterfly network is 1;

[0128] Among them, during the assembly stage, optimization is performed through data reorganization and transposition.

[0129] Specifically, according to the Cooley-Tukey FFT algorithm, there is a "bit reversal" operation on the input data, which not only increases the read and write operations of all data, but also is not conducive to the establishment of a mixed basis and is even less friendly to SIMD.

[0130] Figure 6 A schematic diagram of a Stockham butterfly network according to a specific embodiment of the present invention.

[0131] In this embodiment, a new butterfly network, the Stockham butterfly network, is introduced. Figure 6 shown.

[0132] The Stockham butterfly network does not change the definition of FFT itself or the way the butterfly network is generated, but is implemented by recalculating the address of the required data. The input and output data of the butterfly network are both natural sequences, the input eliminates the "bit reversal" permutation operation, and reduces the operation of memory order adjustment.

[0133] Optimizing the first-level butterfly network separately can achieve better performance. The rotation factor of the first-level butterfly network is 1, and there is no need to read and calculate from the memory, which effectively reduces the overhead of memory access and calculation. The writing of the first-level output results is not continuous, and data reorganization and transposition are required during assembly optimization.

[0134] In addition, by applying the Single Instruction Multiple Data (SIMD) optimization technology, the butterfly operations in the same level are processed in parallel. In the assembly implementation, four butterfly operations can be calculated at the same time, thanks to the continuous storage of input data and rotation factors can be directly mapped to vector registers, to achieve efficient data parallel processing. SIMD optimization not only reduces the size of the code, but also significantly improves the data processing throughput of the processor.

[0135] Considering the clear structure of the butterfly network, the input data and rotation factors in the same level can be stored in the cache, thereby taking advantage of the basic properties of FFT and implementing the FFT program efficiently. This approach avoids calling resource-intensive large-scale FFT functions, thus providing an effective strategy for performance optimization in specific application scenarios.

[0136] In this embodiment, the steps of butterfly algorithm optimization include extracting common terms of butterfly calculation formulas, simplifying large-base butterfly calculations, and using the butterfly algorithm optimization to include:

[0137] Applications based on radix-14FFT calculations;

[0138]

[0139] Among them, the rotation factors of the butterfly network have symmetry and periodicity;

[0140] According to the symmetry and periodicity of the rotation factor, we can calculate Three rotation factors, the remaining rotation factors are The real or imaginary part of the rotation factor is negated to obtain:

[0141]

[0142] Simplified, the butterfly network calculation formula of Radix-14 is:

[0143] X(0)=(x0-x7)+S0+S4+S8

[0144] X(7)=(x0+x7)+S5-S1-S9

[0145] X(1)=A+B

[0146] X(13)=AB

[0147] X(3)=C+D

[0148] X(11)=CD

[0149] X(5)=E+F

[0150] X(9)=EF

[0151] X(2)=G+H

[0152] X(12)=GH

[0153] X(4)=IJ

[0154] X(10)=I+J

[0155] X(6)=K+L

[0156] X(8) = KL;

[0157] Among them, the time complexity of butterfly network calculation is reduced by extracting and pre-calculating common factors, reducing floating-point calculations and code redundancy.

[0158] Specifically, in this embodiment, taking radix-14FFT calculation as an example, the rotation factor has symmetry and periodicity. When calculating radix-14FFT, it is not necessary to calculate all 14 rotation factors. Three rotations, the remaining rotation factors can be obtained by negating the real or imaginary parts of these three rotation factors.

[0159]

[0160] in,

[0161]

[0162] The simplified Radix-14 butterfly calculation formula is as follows:

[0163] X(0)=(x0-x7)+S0+S4+S8

[0164] X(7)=(x0+x7)+S5-S1-S9

[0165] X(1)=A+B

[0166] X(13)=AB

[0167] X(3)=C+D

[0168] X(11)=CD

[0169] X(5)=E+F

[0170] X(9)=EF

[0171] X(2)=G+H

[0172] X(12)=GH

[0173] X(4)=IJ

[0174] X(10)=I+J

[0175] X(6)=K+L

[0176] X(8) = KL;

[0177] By extracting and pre-calculating common factors, floating-point calculations and code redundancy can be reduced, and the time complexity of butterfly calculations can be minimized.

[0178] In this embodiment, the butterfly network calculation includes:

[0179] Read the input sequence, according to the preset step length r, read the input sequence x1~x with a length of r r-1 ;

[0180] Multiply by the rotation factor;

[0181] Among them, since the rotation factor of the first-level butterfly network is 1, the multiplication of the rotation factor in this stage is skipped;

[0182] Calculate the common factors of the butterfly network calculation formula and store A~L in the register;

[0183] Calculating the output sequence, including obtaining the output results in sequence according to the common factors and the calculation formula and storing them in the register;

[0184] Writes the output sequence and stores the results according to the output step size.

[0185] Specifically, Figure 5 A schematic diagram of a radix-14 FFT calculation process according to a specific embodiment of the present invention.

[0186] In this embodiment, if Figure 5 As shown, the calculation of the butterfly can be roughly summarized into 5 steps:

[0187] 1) Read the input sequence, and read the input sequence x1~x with a step length of r r-1 .

[0188] 2) Multiply by the rotation factor.

[0189] Since the rotation factors in the first stage are all 1, there is no need to perform multiplication, and this step is skipped in the first stage of the butterfly network calculation.

[0190] 3) Calculate the butterfly common factors and store A~L in the register.

[0191] 4) Calculate the output sequence, obtain the output results in sequence according to the common factors and calculation formula, and store them in the register.

[0192] 5) Write the output sequence and store the results according to the output step size.

[0193] In this embodiment, it also includes:

[0194] Based on the CPU having 32 128-bit floating-point registers, each floating-point register stores 4 32-bit single-precision floating-point numbers or 2 64-bit double-precision floating-point numbers. One instruction processes 4 data in parallel at the same time. Each butterfly calculation is independent of each other. SIMD optimization processes 4 butterfly calculations at the same time.

[0195] Among them, the optimization of registers is divided into two parts: register multiplexing and stack storage of temporary data;

[0196] Among them, the register-based optimization includes register multiplexing, which realizes independent processing of input data and rotation factor data by multiplexing the temporary register tmptw of the rotation factor;

[0197] When register resources are limited, a strategy of loading twiddle factors in batches is adopted, and the tmptw registers are continued to be used for data storage after the complex multiplication is completed.

[0198] Specifically, ARMv8 is an ARM architecture CPU that supports 64-bit computing and is also compatible with the 32-bit ARM instruction set. ARMv8 provides 32 double-precision general registers and 32 quad-precision floating-point registers. Double-precision and quad-precision registers need to be aligned on appropriate address boundaries to ensure efficient access and processing. Specifically, 32 128-bit floating-point registers are provided, each of which can store 4 32-bit single-precision floating-point numbers or 2 64-bit double-precision floating-point numbers. One instruction can process up to 4 data in parallel at the same time. Each butterfly calculation is independent of each other.

[0199] Figure 7 A schematic diagram of SIMD instruction optimization according to a specific embodiment of the present invention.

[0200] like Figure 7 As shown, SIMD optimization can process four butterfly calculations simultaneously.

[0201] In this embodiment, register optimization is divided into two parts: register multiplexing and stack storage of temporary data.

[0202] Among them, in the register reuse strategy, the temporary register tmptw of the twiddle factor is reused to achieve independent processing of input data and twiddle factor data. When register resources are limited, the strategy of loading twiddle factors in batches is adopted, and the tmptw register is continued to be used after the complex multiplication is completed.

[0203] In this embodiment, it also includes:

[0204] Register-based optimizations include stack storage of temporary data;

[0205] Among them, by reusing the temporary input register tmpin, after loading part of the input data and calculating the intermediate variables, the register tmpin is released in time for reuse;

[0206] Among them, during the multiplication operation, the temporary register tmpout is reused in time, the data is immediately stored in the memory after the output result is calculated, and the temporary register tmpout is released for reuse.

[0207] Specifically, in this embodiment, by reusing the temporary input register tmpin, after loading part of the input data and calculating the intermediate variable, tmpin is released in time for reuse. In the multiplication and other operations, the temporary register tmpout is reused in time, the data is immediately stored in the memory after the output result is calculated, and the tmpout register is released for reuse.

[0208] In this embodiment, it also includes:

[0209] Filter instructions with low latency and high throughput;

[0210] Among them, based on the ARMv8 platform under the ARM architecture, select the multiplication and addition, multiplication and subtraction instructions of fmla and fmls;

[0211] Among them, based on the support of ld2 and st2 load access instructions in ARM NEON, the ARMv8 platform under the ARM architecture uses ld2, faddp, and st2 instructions to perform complex arithmetic operations.

[0212] Specifically, in this embodiment, instructions with low latency and high throughput are selected. Based on the ARMv8 platform, fmla and fmls multiply-add and multiply-subtract instructions can be selected. In ARM NEON, ld2 and st2 efficient load and access instructions are supported, and ld2, faddp, st2 and other instructions are used for complex arithmetic operations on the ARMv8 platform.

[0213] In this embodiment, it also includes:

[0214] Determine whether there is a dependency relationship between adjacent instructions;

[0215] If,None, then instruction reordering is allowed;

[0216] Among them, according to the instruction reordering, the order of loading data is adjusted and the intermediate results are calculated in time;

[0217] After the intermediate results are calculated, the occupancy of register tmpin is released for reuse in outputting the intermediate results.

[0218] Specifically, in this embodiment, if there is no dependency relationship between adjacent instructions, the instructions can be reordered, thereby avoiding pipeline stall.

[0219] The order of loading data is adjusted by instruction reordering, and the intermediate results are calculated in time. After the intermediate results are calculated, the input registers are released for output result reuse.

[0220] Figure 8 A schematic diagram of instruction reordering according to a specific embodiment of the present invention.

[0221] like Figure 8 As shown, the sequentially executed instructions are reordered.

[0222] In this embodiment, it also includes:

[0223] According to the steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization, multi-level butterfly operation is realized;

[0224] Multi-stage butterfly operations include stride memory access, bit reversal, Wing operation and parallel processing.

[0225] Specifically, in this embodiment, through the steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization, multi-level butterfly operations are implemented step by step, including stride memory access, bit reversal, Wing operation (complex multiplication) and parallel processing.

[0226] In this embodiment, it also includes:

[0227] Application based on radix-14FFT calculation, temporarily store common factors in stack, calculate output results and load them into registers;

[0228] Among them, the real and imaginary parts of the intermediate result scratch occupy 26 floating-point registers respectively;

[0229] Input data and rotation factors are loaded in pairs;

[0230] Among them, the input data is multiplied by the rotation factor and then loaded into the next pair of data to calculate the intermediate result, and the rotation factor and the input data reuse the same register;

[0231] Among them, after calculating the intermediate results, the registers occupied by the intermediate results are reused in the calculation process;

[0232] Among them, the butterfly calculation results are output in time and the occupied registers are released.

[0233] Specifically, in this embodiment, taking the Radix-14 FFT calculation as an example, in the case of a large base, while the ARM architecture registers are reasonably reused, there is a situation where they are not enough. The common factors need to be temporarily stored in the stack and loaded into the registers when the output results are calculated. The real and imaginary parts of the intermediate result scratch require 26 floating-point registers respectively. The input data and the rotation factors are loaded in pairs, and the intermediate results are calculated when the input data is multiplied by the rotation factors and the next pair of data is loaded, and the registers of the rotation factors and input data are reused; after calculating the intermediate results, the intermediate result registers can be reused for calculation; the butterfly calculation results are output in time to release the multiplexed output registers.

[0234] Figure 2 It is a structural diagram of a CPU butterfly network computing device provided by one or more embodiments of the present invention.

[0235] like Figure 2 The CPU butterfly network computing device shown includes: a step module, a butterfly network optimization module, a butterfly algorithm optimization module, and a SIMD optimization module;

[0236] The step module is used to set the steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization;

[0237] The butterfly network optimization module includes the following steps for butterfly network optimization: based on the iterative Stockham FFT calculation framework, the Cooley-Tukey FFT algorithm is used to merge the calculation kernels to improve the butterfly network performance;

[0238] The butterfly algorithm optimization module is used for the butterfly algorithm optimization steps including extracting the common items of the butterfly calculation formula, simplifying the large-base butterfly calculation, and using it for the butterfly algorithm optimization;

[0239] SIMD optimization module, the steps for SIMD optimization include optimizing SIMD assembly instructions, designing register reuse strategies and stack memory usage, and using memory to alleviate the memory access pressure of large-radix butterfly calculations.

[0240] It is worth noting that although the system only discloses the step module, butterfly network optimization module, butterfly algorithm optimization module, and SIMD optimization module, it does not mean that the device is limited to the above basic functional modules. Rather, what the present invention wants to express is that, based on the above basic functional modules, those skilled in the art can arbitrarily add one or more functional modules in combination with the prior art to form an infinite number of embodiments or technical solutions. In other words, the system is open rather than closed. Just because the present embodiment only discloses individual basic functional modules, it cannot be considered that the scope of protection of the claims of the present invention is limited to the above-disclosed basic functional modules.

[0241] Through the above scheme, the following beneficial technical effects are obtained:

[0242] This application optimizes the performance of the butterfly network by merging the computing kernels with the Cooley-Tukey FFT algorithm based on the iterative Stockham FFT computing framework. The input data and output data of the butterfly network are both natural sequences. The input eliminates the "bit reversal" permutation operation, reduces the memory order adjustment operation, and improves the computing efficiency.

[0243] This application uses the symmetry and periodicity of the rotation factor to calculate Three rotation factors, the remaining rotation factors are The real or imaginary part of the rotation factor is inverted, which simplifies the calculation of the data.

[0244] This application accelerates instruction processing speed by screening instructions with low latency and high throughput, and improves the efficiency of computing resources in processing data through register multiplexing.

[0245] Fig. 9 A structural block diagram of an electronic device of a CPU butterfly network computing method provided by one or more embodiments of the present invention.

[0246] like Fig. 9As shown, the present application provides an electronic device, including: a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;

[0247] A computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the steps of a CPU butterfly network computing method.

[0248] The present application also provides a computer-readable storage medium storing a computer program executable by an electronic device. When the computer program runs on the electronic device, the electronic device executes the steps of a CPU butterfly network computing method.

[0249] The present application also provides a data platform, including:

[0250] An electronic device for implementing the steps of a CPU butterfly network computing method;

[0251] A processor, wherein the processor runs a program, and when the program runs, the steps of the CPU butterfly network calculation method are executed from the data output by the electronic device;

[0252] The storage medium is used to store a program, and when the program is running, the program executes the steps of the CPU butterfly network calculation method for the data output from the electronic device.

[0253] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0254] The electronic device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and a memory. The operating system can be any one or more computer operating systems that implement electronic device control through a process, such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a Windows operating system. In addition, in an embodiment of the present invention, the electronic device can be a handheld device such as a smart phone or a tablet computer, or can be an electronic device such as a desktop computer or a portable computer, which is not particularly limited in the embodiment of the present invention.

[0255] The execution subject of the electronic device control in the embodiment of the present invention may be an electronic device, or a functional module in the electronic device that can call and execute a program. The electronic device may obtain the firmware corresponding to the storage medium. The firmware corresponding to the storage medium is provided by the supplier. The firmware corresponding to different storage media may be the same or different, which is not limited here. After the electronic device obtains the firmware corresponding to the storage medium, the firmware corresponding to the storage medium may be written into the storage medium, specifically, the firmware corresponding to the storage medium may be burned into the storage medium. The process of burning the firmware into the storage medium may be implemented using existing technology, which will not be described in detail in the embodiment of the present invention.

[0256] The electronic device may also obtain a reset command corresponding to the storage medium. The reset command corresponding to the storage medium is provided by the supplier. The reset commands corresponding to different storage media may be the same or different, and are not limited here.

[0257] At this time, the storage medium of the electronic device is a storage medium in which the corresponding firmware is written, and the electronic device can respond to the reset command corresponding to the storage medium in the storage medium in which the corresponding firmware is written, so that the electronic device resets the storage medium in which the corresponding firmware is written according to the reset command corresponding to the storage medium. The process of resetting the storage medium according to the reset command can be implemented by the existing technology and will not be described in detail in the embodiments of the present invention.

[0258] For the convenience of description, the above devices are described in terms of functions and are divided into various units and modules. Of course, when implementing the present application, the functions of each unit and module can be implemented in the same or multiple software and / or hardware.

[0259] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0260] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0261] It can be known from the description of the above implementation modes that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute the methods described in the various implementation modes of the present application or certain parts of the implementation modes.

[0262] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A CPU butterfly network computing method, characterized in that: Based on the ARM architecture CPU, the CPU butterfly network calculation method includes: The steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization; The butterfly network optimization steps include: based on the iterative Stockham FFT calculation framework, merging the calculation kernels with the Cooley-TukeyFFT algorithm to improve the butterfly network performance; The steps of butterfly algorithm optimization include extracting common items of butterfly calculation formulas, simplifying large-base butterfly calculations, and using them for butterfly algorithm optimization; The SIMD optimization steps include optimizing SIMD assembly instructions, designing register reuse strategies and stack memory usage, and using memory to alleviate the memory access pressure of large-radix butterfly calculations.

2. The CPU butterfly network computing method according to claim 1, characterized in that: The butterfly network optimization steps include: based on the iterative Stockham FFT calculation framework, merging the calculation kernels with the Cooley-Tukey FFT algorithm to improve the butterfly network performance, including: The butterfly network is fed with natural sequence data; Input natural sequence data into the butterfly network to obtain output data of the natural sequence; Among them, the rotation factor of the first-level butterfly network is 1; Among them, during the assembly stage, optimization is performed through data reorganization and transposition.

3. The CPU butterfly network computing method according to claim 2, characterized in that: The steps of butterfly algorithm optimization include extracting common items of butterfly calculation formulas, simplifying large-base butterfly calculations, and using the butterfly algorithm optimization to include: Applications based on radix-14FFT calculations; Among them, the rotation factors of the butterfly network have symmetry and periodicity; According to the symmetry and periodicity of the rotation factor, we can calculate Three rotation factors, the remaining rotation factors are The real or imaginary part of the rotation factor is negated to obtain: Simplified, the butterfly network calculation formula of Radix-14 is: X(0)=(x0-x7)+S0+S4+S8 X(7)=(x0+x7)+S5-S1-S9 X(1)=A+B X(13)=AB X(3)=C+D X(11)=CD X(5)=E+F X(9)=EF X(2)=G+H X(12)=GH X(4)=IJ X(10)=I+J X(6)=K+L X(8) = KL; Among them, the time complexity of butterfly network calculation is reduced by extracting and pre-calculating common factors, reducing floating-point calculations and code redundancy.

4. The CPU butterfly network computing method according to claim 3, characterized in that: The butterfly network calculation includes: Read the input sequence, according to the preset step length r, read the input sequence x1~x with a length of r r-1 ; Multiply by the rotation factor; Among them, since the rotation factor of the first-level butterfly network is 1, the multiplication of the rotation factor in this stage is skipped; Calculate the common factors of the butterfly network calculation formula and store A~L in the register; Calculating the output sequence, including obtaining the output results in sequence according to the common factors and the calculation formula and storing them in the register; Writes the output sequence and stores the results according to the output step size.

5. The CPU butterfly network computing method according to claim 4, characterized in that: Also includes: Based on the CPU having 32 128-bit floating-point registers, each floating-point register stores 4 32-bit single-precision floating-point numbers or 2 64-bit double-precision floating-point numbers. One instruction processes 4 data in parallel at the same time. Each butterfly calculation is independent of each other. SIMD optimization processes 4 butterfly calculations at the same time. Among them, the optimization of registers is divided into two parts: register multiplexing and stack storage of temporary data; Among them, the register-based optimization includes register multiplexing, which realizes independent processing of input data and rotation factor data by multiplexing the temporary register tmptw of the rotation factor; When register resources are limited, a strategy of loading twiddle factors in batches is adopted, and the tmptw registers are continued to be used for data storage after the complex multiplication is completed.

6. The CPU butterfly network computing method according to claim 5, characterized in that: Also includes: Register-based optimizations include stack storage of temporary data; Among them, by reusing the temporary input register tmpin, after loading part of the input data and calculating the intermediate variables, the register tmpin is released in time for reuse; Among them, during the multiplication operation, the temporary register tmpout is reused in time, the data is immediately stored in the memory after the output result is calculated, and the temporary register tmpout is released for reuse.

7. The CPU butterfly network computing method according to claim 6, characterized in that: Also includes: Filter instructions with low latency and high throughput; Among them, based on the ARMv8 platform under the ARM architecture, select the multiplication and addition, multiplication and subtraction instructions of fmla and fmls; Among them, based on the support of ld2 and st2 load access instructions in ARM NEON, the ARMv8 platform under the ARM architecture uses ld2, faddp, and st2 instructions to perform complex arithmetic operations.

8. The CPU butterfly network computing method according to claim 7, characterized in that: Also includes: Determine whether there is a dependency relationship between adjacent instructions; If,None, then instruction reordering is allowed; Among them, according to the instruction reordering, the order of loading data is adjusted and the intermediate results are calculated in time; After the intermediate results are calculated, the occupancy of register tmpin is released for reuse in outputting the intermediate results.

9. The CPU butterfly network computing method according to claim 8, characterized in that: Also includes: According to the steps of butterfly network optimization, butterfly algorithm optimization and SIMD optimization, multi-level butterfly operation is realized; The multi-stage butterfly operation includes stride memory access, bit reversal, Wing operation and parallel processing.

10. The CPU butterfly network computing method according to claim 9, characterized in that: Also includes: Application based on radix-14FFT calculation, temporarily store common factors in stack, calculate output results and load them into registers; Among them, the real and imaginary parts of the intermediate result scratch occupy 26 floating-point registers respectively; Input data and rotation factors are loaded in pairs; Among them, the input data is multiplied by the rotation factor and then loaded into the next pair of data to calculate the intermediate result, and the rotation factor and the input data reuse the same register; Among them, after calculating the intermediate results, the registers occupied by the intermediate results are reused in the calculation process; Among them, the butterfly calculation results are output in time and the occupied registers are released.

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