Control method and device for power factor correction circuit, intelligent household electrical appliance and storage medium

Abstract

The invention relates to the technical field of intelligent household appliances, and discloses a control method for a power factor correction circuit, and the method comprises the steps: obtaining a starting state of an inverter load; if the inverter load is not started, determining the input voltage of the phase-locked loop according to the current input voltage and the current input current of the power factor correction circuit; and if the inverter load is started, determining the input voltage of the phase-locked loop according to the current input voltage of the power factor correction circuit. By acquiring the starting state of the inverter load, the phase-locked loop input voltage corresponding to the starting state of the inverter load is obtained, so that the phase-locked loop input information is more accurate and reliable, the accuracy of phase-locked loop control is improved, and the power factor of the power factor correction circuit is improved. The invention further discloses a control device for the power factor correction circuit, an intelligent household appliance and a storage medium.

Description

Technical Field

[0001] The present application relates to the technical field of smart home appliances, for example, to a control method and device for a power factor correction circuit, a smart home appliance, and a storage medium. Background Art

[0002] At present, in order to reduce the harmonic pollution brought to the power grid, the AC power from the power grid in household air conditioners and other similar systems is rectified by a rectifier bridge and then passed through a PFC (Power Factor Correction) circuit to suppress current harmonics, improve the power factor, and reduce pollution to the power grid.

[0003] In the use of variable frequency air conditioners, as the frequency increases and the load increases, the DC bus voltage will drop. At the same time, the bus voltage fluctuates significantly and the current waveform is greatly distorted. In order to stabilize the DC bus voltage and improve the power factor, PFC control technology is often used. The PFC control frequency has been gradually increased from 10Hz to 40Hz, or even 80Hz. In order to ensure that the input side power factor PF = 1, that is, the grid side current and grid side voltage are in phase, the final PFC setting is generally the product of the duty cycle output and the grid side voltage fundamental phase of the sine wave. Therefore, it is necessary to identify the phase of the grid side voltage fundamental wave. The general identification method is to sample the input side voltage and perform phase-locked loop identification through the sampling resistor voltage divider method.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] There is a certain deviation in the grid-side voltage phase determined after passing through the filter inductor and filter capacitor, which leads to a deviation in the phase-locked loop identification result. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a control method and device for a power factor correction circuit, a smart home appliance, and a storage medium to improve the accuracy of phase-locked loop control and thereby improve the accuracy of the obtained phase information.

[0008] In some embodiments, the control method for the power factor correction circuit includes: obtaining the startup status of the inverter load; if the inverter load is not started, determining the input voltage of the phase-locked loop according to the current input voltage and current input current of the power factor correction circuit; if the inverter load is started, determining the input voltage of the phase-locked loop according to the current input voltage of the power factor correction circuit.

[0009] Optionally, determining the input voltage of the phase-locked loop according to the current input voltage and the current input current of the power factor correction circuit includes:

[0010] An input voltage of the phase-locked loop is determined according to the product of the current input voltage and the current input current.

[0011] Optionally, determining the input voltage of the phase-locked loop according to the product of the current input voltage and the current input current includes:

[0012] calculate Determine the input voltage of the phase-locked loop _ ;

[0013] Among them, U PLL_in is the input voltage of the phase-locked loop, U s is the current input voltage of the power factor correction circuit, I rec is the current input current of the power factor correction circuit, I rec_pp is the peak value of the current input current of the power factor correction circuit; a 0 is the first calculation factor, b 0 is the second calculation factor, a 0 +b 0 =1, a 0 <b 0 .

[0014] Optionally, after determining the input voltage phase of the phase-locked loop according to the current input voltage of the power factor correction circuit, the method further includes:

[0015] In a set period, the current input voltage of the phase-locked loop is transitioned to the input voltage of the phase-locked loop determined according to the current input voltage of the power factor correction circuit.

[0016] Optionally, transitioning a current input voltage of a phase-locked loop to determining an input voltage of the phase-locked loop according to a current input voltage of the power factor correction circuit comprises:

[0017] Get the current input voltage operation cycle n, n<n s ;

[0018] calculate Obtaining the input voltage of the phase-locked loop of the nth operating cycle;

[0019] Among them, n s To set the number of cycles, U PLL_in is the input voltage of the phase-locked loop, U s is the current input voltage of the power factor correction circuit, I rec is the current input current of the power factor correction circuit, Irec_pp is the peak value of the current input current of the power factor correction circuit; a n is the first calculation factor of the nth input voltage operation cycle, b n is the second calculation factor of the nth input voltage operation cycle, a n +b n =1, a ns =1, a n <a n+1 , b n >b n+1 .

[0020] Optionally, after determining the input voltage of the phase-locked loop, the method further includes:

[0021] According to the phase-locked loop input voltage, filtering and phase locking are performed in the phase-locked loop to determine the input voltage phase value of the power factor correction circuit;

[0022] The operation of the switch tube is controlled according to the input voltage phase value.

[0023] In some embodiments, the control device for a power factor correction circuit includes:

[0024] A detection module is configured to obtain a startup state of an inverter load;

[0025] The control module is configured to determine the input voltage of the phase-locked loop according to the current input voltage and current input current of the power factor correction circuit if the inverter load is not started; and to determine the input voltage of the phase-locked loop according to the current input voltage of the power factor correction circuit if the inverter load is started.

[0026] In some embodiments, the control device for a power factor correction circuit includes:

[0027] The invention comprises a processor and a memory storing program instructions, wherein the processor is configured to execute the control method for a power factor correction circuit as described above when running the program instructions.

[0028] In some embodiments, the smart home appliance includes the above-mentioned control device for the power factor correction circuit.

[0029] In some embodiments, the storage medium stores program instructions, and when the program instructions are run, the control method for the power factor correction circuit as described above is executed.

[0030] The control method and device for a power factor correction circuit, smart home appliance, and storage medium provided in the embodiments of the present disclosure can achieve the following technical effects:

[0031] By obtaining the startup state of the inverter load and then obtaining the phase-locked loop input voltage corresponding to the startup state of the inverter load, the phase-locked loop input information can be made more accurate and reliable. Before the inverter load is started, the input voltage waveform of the power factor correction circuit has a large phase error in recognition, and the input current of the power factor correction circuit has a waveform with a peak position consistent with it. Therefore, the input voltage of the phase-locked loop is determined according to the input voltage and input current of the power factor correction circuit, which can improve the accuracy of the acquired phase-locked loop input voltage information. After the inverter load is started, it gradually transitions to the phase-locked loop input voltage determined according to the input voltage of the power factor correction circuit. In this way, the accuracy of the phase-locked loop control is improved, and then the accuracy of the obtained phase information is improved, thereby improving the power factor of the power factor correction circuit.

[0032] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0034] Figure 1 is a structural schematic diagram of a PFC circuit provided by an embodiment of the present disclosure;

[0035] Figure 2 is a structural schematic diagram of a control system of a PFC circuit provided by an embodiment of the present disclosure;

[0036] Figure 3 is a schematic diagram of a control method for a power factor correction circuit provided by an embodiment of the present disclosure;

[0037] Figure 4 is a schematic diagram of a control method for a power factor correction circuit provided by an embodiment of the present disclosure;

[0038] Figure 5 is a schematic diagram of another control method for a power factor correction circuit provided by an embodiment of the present disclosure;

[0039] Figure 6 is a schematic diagram of another control method for a power factor correction circuit provided by an embodiment of the present disclosure;

[0040] Figure 7 is a schematic diagram of a control device for a power factor correction circuit provided by an embodiment of the present disclosure;

[0041] Figure 8It is a schematic diagram of a control device for a power factor correction circuit provided in an embodiment of the present disclosure.

[0042] Reference numerals:

[0043] 10: power supply; 20: rectifier circuit module; 30: power factor correction circuit module; 40: inverter; 50: control circuit; 51: AD sampling module; 52: calculation module; 53: PWM signal output module;

[0044] 101: the first output terminal of the power supply; 102: the second output terminal of the power supply; 201: the first input terminal of the rectifier circuit; 202: the second input terminal of the rectifier circuit; 211: the first output terminal of the rectifier circuit; 212: the second output terminal of the rectifier circuit; 301: the first input terminal of the boost circuit; 302: the second input terminal of the boost circuit; 303: the third input terminal of the boost circuit: 311: the first output terminal of the boost circuit; 312: the second output terminal of the boost circuit; 401: the first input terminal of the inverter; 402: the second input terminal of the inverter. DETAILED DESCRIPTION

[0045] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0046] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0047] Unless otherwise stated, the term "plurality" means two or more.

[0048] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0049] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0050] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0051] Figure 1 A schematic diagram of a PFC circuit is shown, wherein the PFC circuit includes a power supply 10 , a rectifier circuit module 20 , a power factor correction circuit module 30 , an inverter 40 and a control module 50 .

[0052] The first output terminal 101 of the power supply 10 is connected to the first input terminal 201 of the rectifier circuit module 20, and the second output terminal 102 of the power supply 10 is connected to the second input terminal 202 of the rectifier circuit module 20. The first output terminal 211 of the rectifier circuit module 20 is connected to the first input terminal 301 of the power factor correction circuit module 30. The second output terminal 212 of the rectifier circuit module 20 is connected to the second input terminal 302 of the power factor correction circuit module 30. The output terminal of the control module 50 is connected to the third input terminal 303 of the power factor correction circuit module 30. The first output terminal 311 of the power factor correction circuit module 30 is connected to the first input terminal 401 of the inverter 40, and the second output terminal 312 of the power factor correction circuit module 30 is connected to the second output terminal 402 of the inverter 40.

[0053] The PFC circuit also includes: a first inductor L1, a first capacitor C1, and a second capacitor C2. The first inductor L1 is connected in series between the power supply 10 and the rectifier circuit module 20. It cooperates with other components to reduce the phase difference between the current and voltage of the AC input. The first capacitor C1 is connected in parallel between the power supply 10 and the rectifier circuit module 20. The second capacitor C2 is connected in parallel between the rectifier circuit module 20 and the power factor correction circuit module 30. In this way, it can play a certain filtering role.

[0054] The power supply 10 is an AC power supply with an output voltage of 220V.

[0055] The rectifier circuit module 20 is a bridge rectifier circuit, including a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4 connected in sequence. The first input terminal 201 of the rectifier circuit module 20 is specifically located between the first diode D1 and the fourth diode D4, and the second input terminal 202 is located between the second diode D2 and the third diode D3. When the current output by the power supply is positive, the first diode D1 and the second diode D2 are turned on. When the current is reversed, the third diode D3 and the fourth diode D4 are turned on. In this way, the input alternating current can be rectified and direct current can be output.

[0056] The power factor correction circuit module 30 includes a power tube, a fifth diode D5, a second inductor L2 and a third capacitor C3. The power tube includes an IGBT (Insulated Gate Bipolar Transistor) and a sixth diode D6 connected in reverse parallel to the IGBT. When switching, the current in the IGBT is transferred to the sixth diode D6 to maintain the continuous flow of current.

[0057] Among them, the power tube is connected in parallel with the third capacitor C3, the input end of the second inductor L2 is the first input end 301 of the power factor correction circuit module 30, and the output end of the second inductor L2 is the input end of the fifth diode D5. The output end of the fifth diode D5 is connected to one end of the third capacitor C3, which is equivalent to the first output end 311 of the power factor correction circuit module 30. The collector of the IGBT is connected between the second inductor L2 and the fifth diode D5, and the base serves as the third input end 303 of the power factor correction circuit module 30. The emitter is connected to the other end of the third capacitor C3, and together they serve as the second output end 312 of the power factor correction circuit module 30.

[0058] The PFC circuit also includes: a first sampling resistor R1, a second sampling resistor R2 and a third sampling resistor R3. The first sampling resistor R1 is connected in parallel between the rectifier circuit module 20 and the power factor correction circuit module 30, and is configured to detect the input voltage U s The second sampling resistor R2 is connected in series between the rectifier circuit module 20 and the power factor correction circuit module 30, and is configured to detect the input current I rec The third sampling resistor R3 is connected in parallel between the power factor correction circuit module 30 and the inverter 40 and is configured to detect the output voltage U o .

[0059] The control module 50 includes: an AD sampling module 51, a calculation module 52 and a PWM (Pulse Width Modulation) signal output module 53. The AD sampling module 53 is configured to obtain the input voltage U detected by the sampling resistor. s 、Input current I rec And the output voltage U o The analog signal is converted into a digital signal for subsequent calculation. The calculation module 52 is configured to perform calculations based on the data of the AD sampling module 53 to obtain a suitable PWM signal. The PWM signal output module 53 then inputs the PWM signal into the power tube.

[0060] Combination Figure 1 The PFC circuit shown in the figure, the embodiment of the present disclosure provides a control system for the PFC circuit. Figure 2 As shown, in the process of determining the switch tube drive signal, according to the output voltage u o And the output voltage reference value u ref The voltage loop output is determined by voltage loop proportional integration (PI) control. L The effective value of the current output by the effective value operation is used to determine the duty cycle of the switch tube drive signal according to the input voltage phase value output by the phase-locked loop and the sine (sin) operation. The duty cycle to be adjusted is reversed with 1 to obtain the target duty cycle of the switch tube drive signal. The target duty cycle of the switch tube drive signal is generated by the pulse width modulation (PWM, Pulse Width Modulation) generation module of the control circuit, and the switch tube drive signal is output. The control system is used to determine the duty cycle in the switch tube drive signal to adjust the output voltage to avoid the duty cycle of the switch tube drive signal failing to reach 1 at the zero point of the input voltage, resulting in large interference from harmonic current. For the PFC positive circuit that does not include the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, the input voltage phase value is obtained by the input current i L Determined after phase-locked loop and sinusoidal operation.

[0061] Combination Figure 3 As shown, the present disclosure provides a control method for a power factor correction circuit, which is applied to Figure 1 In the PFC circuit shown in FIG. 1 , the control method includes:

[0062] Step S301, obtaining the startup state of the inverter load.

[0063] Step S302: if the inverter load is not started, determine the input voltage of the phase-locked loop according to the current input voltage and current input current of the power factor correction circuit.

[0064] Step S303: if the inverter load has been started, the input voltage of the phase-locked loop is determined according to the current input voltage of the power factor correction circuit.

[0065] Here, the current input voltage and current input current of the power factor correction circuit refer to the input voltage U of the power factor correction circuit module after the rectifier module. s , and the input current I rec .

[0066] By obtaining the startup state of the inverter load and then obtaining the phase-locked loop input voltage corresponding to the startup state of the inverter load, the phase-locked loop input information can be made more accurate and reliable. Before the inverter load is started, the input voltage waveform of the power factor correction circuit has a large phase error in recognition, and the input current of the power factor correction circuit has a waveform with a peak position consistent with it. Therefore, the input voltage of the phase-locked loop is determined according to the input voltage and input current of the power factor correction circuit, which can improve the accuracy of the acquired phase-locked loop input voltage information. After the inverter load is started, it gradually transitions to the phase-locked loop input voltage determined according to the input voltage of the power factor correction circuit. In this way, the accuracy of the phase-locked loop control is improved, and then the accuracy of the obtained phase information is improved, thereby improving the power factor of the power factor correction circuit.

[0067] After the duty cycle of the switch tube drive signal is determined by the input voltage phase value, only the voltage loop single loop control is required without the current loop control, avoiding the deviation caused by the input current reference value in the current loop to reduce the interference of the harmonic current on the power factor correction circuit near the input voltage zero crossing point. At the same time, by reducing the interference of the harmonic current in the power factor correction circuit and using the input voltage phase value to reduce the phase difference between the input voltage and the input current, the power factor of the power factor correction circuit is improved.

[0068] Combination Figure 4 As shown, the embodiment of the present disclosure provides a control method for a power factor correction circuit. The control method includes:

[0069] Step S401, obtaining the startup state of the inverter load.

[0070] Step S402: if the inverter load is not started, determine the input voltage of the phase-locked loop according to the product of the current input voltage and the current input current.

[0071] Here, when the inverter load is not started, the pulse waveforms of the current input voltage and current input current of the power factor correction circuit have consistent waveform positions; and because the inverter load is not started, the voltage waveform does not pass through the zero point, so it is difficult to obtain an accurate phase through the phase-locked loop. Accordingly, the zero-crossing pulse waveform is obtained by multiplying the current input voltage and current input current of the power factor correction circuit, and the input voltage and phase information of the phase-locked loop are determined based on the pulse waveform to improve the accuracy of the phase-locked loop control.

[0072] Optionally, determining the input voltage of the phase-locked loop according to the product of the current input voltage and the current input current includes:

[0073] calculate Determine the input voltage U of the phase-locked loop PLL_in ;

[0074] Among them, UPLL_in is the input voltage of the phase-locked loop, U s is the current input voltage of the power factor correction circuit, I rec is the current input current of the power factor correction circuit, I rec_pp is the peak value of the current input current of the power factor correction circuit; a 0 is the first calculation factor, b 0 is the second calculation factor, a 0 +b 0 =1, a 0 <b 0 ).

[0075] In this way, the current input voltage U s The current input current I of the power factor correction circuit rec The product determines the input voltage of the phase-locked loop.

[0076] Optionally, in the embodiment of the present disclosure, a 0 <0.1, b 0 >0.9. Thus, according to U s with I rec The product of determines U PLL_in When a 0 and b 0 The value of the input current I rec The relatively large amplitude improves the accuracy of phase recognition of the phase-locked loop input voltage.

[0077] Optionally, a 0 =0, b 0 =1.

[0078] Step S403: if the inverter load has been started, the input voltage of the phase-locked loop is determined according to the current input voltage of the power factor correction circuit.

[0079] By adopting the control method for a power factor correction circuit provided by an embodiment of the present disclosure, the startup state of the inverter load is obtained, and then the phase-locked loop input voltage corresponding to the startup state of the inverter load is obtained, so that the phase-locked loop input information can be made more accurate and reliable. Before the inverter load is started, the input voltage waveform of the power factor correction circuit has a large phase error in recognition, and the input current of the power factor correction circuit has a waveform with a peak position consistent with it. Therefore, the input voltage of the phase-locked loop is determined according to the product of the input voltage and input current of the power factor correction circuit, which can improve the accuracy of the acquired phase-locked loop input voltage information. In this way, by improving the accuracy of the phase-locked loop control, and then improving the accuracy of the obtained phase information, the power factor of the power factor correction circuit is improved.

[0080] Combination Figure 5As shown, the embodiment of the present disclosure provides a control method for a power factor correction circuit, which is applied to Figure 1 In the PFC circuit shown in FIG. 1 , the control method includes:

[0081] Step S501, obtaining the startup state of the inverter load.

[0082] Step S502: if the inverter load is not started, determine the input voltage of the phase-locked loop according to the current input voltage and current input current of the power factor correction circuit.

[0083] Step S503: if the inverter load has been started, the input voltage of the phase-locked loop is determined according to the current input voltage of the power factor correction circuit.

[0084] Step S504, within a set period, the current input information of the phase-locked loop is transitioned to determining the input information of the phase-locked loop according to the current input voltage of the power factor correction circuit.

[0085] Here, by setting the current weight transition strategy within the cycle, the phase-locked loop input voltage is gradually transitioned to U s .

[0086] Specifically, the current input information of the phase-locked loop is transitioned to the input information of the phase-locked loop determined according to the current input voltage of the power factor correction circuit, including:

[0087] Get the current input voltage operation cycle n, n<n s ;

[0088] calculate Obtaining the input voltage of the phase-locked loop of the nth operating cycle;

[0089] Among them, n s To set the number of cycles, U PLL_in is the input voltage of the phase-locked loop, U s is the current input voltage of the power factor correction circuit, I rec is the current input current of the power factor correction circuit, I rec_pp is the peak value of the current input current of the power factor correction circuit; a n is the first calculation factor of the nth input voltage operation cycle, b n is the second calculation factor of the nth input voltage operation cycle, a n +b n =1, a ns =1, a n <a n+1 , b n >b n+1 .

[0090] In the embodiment of the present disclosure, the number of cycles n is sets =10, that is, after 10 sinusoidal cycles of the input voltage, the phase-locked loop input voltage is gradually transitioned to U s .

[0091] Table 1 provides a first calculation factor a for the nth input voltage operation cycle n The second calculation factor b of the nth input voltage operation cycle n The value selection strategy.

[0092] Current input voltage operation cycle n <![CDATA[First calculation factor a n > <![CDATA[Second calculation factor b n > 1 0.1 1 2 0.2 0.9 3 0.3 0.8 4 0.4 0.7 5 0.5 0.6 6 0.6 0.5 7 0.7 0.4 8 0.8 0.3 9 0.9 0.2 10 1 0.1

[0093] By adopting the control method for a power factor correction circuit provided by the embodiment of the present disclosure, the startup state of the inverter load is obtained, and then the phase-locked loop input voltage corresponding to the startup state of the inverter load is obtained, so that the phase-locked loop input information can be made more accurate and reliable. After the inverter load is started, the phase-locked loop input voltage determined according to the product of the input voltage and input current of the power factor correction circuit is gradually transitioned to the input voltage of the power factor correction circuit through the current weight transition strategy, thereby improving the accuracy of the phase-locked loop control, thereby improving the accuracy of the obtained phase information, and thus improving the power factor of the power factor correction circuit.

[0094] Combination Figure 6 As shown, the present disclosure provides a control method for a power factor correction circuit, which is applied to Figure 1 In the PFC circuit shown in FIG. 1 , the control method includes:

[0095] Step S601, obtaining the startup state of the inverter load.

[0096] Step S602: If the inverter load is not started, the input voltage of the phase-locked loop is determined according to the current input voltage and current input current of the power factor correction circuit.

[0097] Step S603: if the inverter load has been started, the input voltage of the phase-locked loop is determined according to the current input voltage of the power factor correction circuit.

[0098] Step S604, within a set period, the current input information of the phase-locked loop is transitioned to determining the input information of the phase-locked loop according to the current input voltage of the power factor correction circuit.

[0099] Step S605, performing filtering and phase locking in the phase-locked loop according to the phase-locked loop input voltage, and determining the input voltage phase value of the power factor correction circuit.

[0100] Step S606, controlling the operation of the switch tube according to the input voltage phase value.

[0101] Here, the input voltage is input into the phase-locked loop so that the phase of the phase-locked loop output tracks the input voltage phase. The result of the input voltage phase after sinusoidal operation is determined as the input voltage phase value, and the position of the instantaneous value of the input voltage is determined to determine the direction of duty cycle adjustment. The duty cycle is determined by adjusting the degree and direction of adjustment to control the switch tube so that the output voltage meets the requirements of the load under different input voltages, thereby improving the stability of load operation. At the same time, since the duty cycle of the switch tube drive signal only needs to be controlled through a single voltage loop when determining it, the deviation caused by the input reference current value is avoided to reduce the interference of harmonic current on the power factor correction circuit near the zero point of the input voltage.

[0102] Figure 7 Schematic diagram of a control device for a power factor correction circuit provided in an embodiment of the present application. The indoor air conditioning device can be implemented in the form of software, hardware or a combination of the two.

[0103] Combination Figure 7 As shown, an embodiment of the present disclosure provides a control device for a power factor correction circuit, including a detection module 71 and a control module 72 .

[0104] The detection module 71 is configured to obtain the startup state of the inverter load;

[0105] The control module 72 is configured to determine the input voltage of the phase-locked loop according to the current input voltage and current input current of the power factor correction circuit if the inverter load is not started; and to determine the input voltage of the phase-locked loop according to the current input voltage of the power factor correction circuit if the inverter load is started.

[0106] Figure 8 Schematic diagram of a control device for a power factor correction circuit provided by an embodiment of the present application. Figure 8 As shown, the control device for the power factor correction circuit includes:

[0107] Processor 800 and memory 801. Optionally, the device may also include a communication interface 802 and a bus 803. The processor 800, the communication interface 802, and the memory 801 may communicate with each other through the bus 803. The communication interface 802 may be used for information transmission. The processor 800 may call the logic instructions in the memory 801 to execute the control method for the power factor correction circuit of the above embodiment.

[0108] In addition, the logic instructions in the memory 801 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0109] The memory 801 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 800 executes the function application and data processing by running the program instructions / modules stored in the memory 801, that is, the control method for the power factor correction circuit in the above embodiment is implemented.

[0110] The memory 801 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 801 may include a high-speed random access memory and may also include a non-volatile memory.

[0111] The embodiment of the present disclosure provides a smart home appliance, comprising the control device for a power factor correction circuit as described above. The smart home appliance may be a home appliance device using a motor device, such as an air conditioner and a washing machine.

[0112] An embodiment of the present disclosure provides a storage medium storing computer executable instructions, wherein the computer executable instructions are configured to execute the control method for a power factor correction circuit.

[0113] An embodiment of the present disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the above-mentioned control method for a power factor correction circuit.

[0114] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0115] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0116] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0117] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0118] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0119] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A control method for a power factor correction circuit, It is characterized in that include: Get the startup status of the inverter load; If the inverter load is not started, the input voltage of the phase-locked loop is determined according to the current input voltage and current input current of the power factor correction circuit; If the inverter load is started, the input voltage of the phase-locked loop is determined according to the current input voltage of the power factor correction circuit.

2. The control method according to claim 1, It is characterized in that The step of determining the input voltage of the phase-locked loop according to the current input voltage and the current input current of the power factor correction circuit comprises: An input voltage of the phase-locked loop is determined according to the product of the current input voltage and the current input current.

3. The control method according to claim 2, It is characterized in that Determining the input voltage of the phase-locked loop according to the product of the current input voltage and the current input current includes: calculate Determine the input voltage U of the phase-locked loop PLL_in ; Among them, U PLL_in is the input voltage of the phase-locked loop, U s is the current input voltage of the power factor correction circuit, I rec is the current input current of the power factor correction circuit, I rec_pp is the peak value of the current input current of the power factor correction circuit; a 0 is the first calculation factor, b 0 is the second calculation factor, a 0 +b 0 =1,a 0 <b 0 .

4. The control method according to claim 1, It is characterized in that After determining the input voltage phase of the phase-locked loop according to the current input voltage of the power factor correction circuit, the method further includes: In a set period, the current input voltage of the phase-locked loop is transitioned to the input voltage of the phase-locked loop determined according to the current input voltage of the power factor correction circuit.

5. The control method according to claim 4, It is characterized in that Transitioning a current input voltage of a phase-locked loop to an input voltage of the phase-locked loop determined according to the current input voltage of the power factor correction circuit, comprising: Get the current input voltage operation cycle n, n<n s ; calculate Obtaining the input voltage of the phase-locked loop of the nth operating cycle; Among them, n s To set the number of cycles, U PLL_in is the input voltage of the phase-locked loop, U s is the current input voltage of the power factor correction circuit, I rec is the current input current of the power factor correction circuit, I rec_pp is the peak value of the current input current of the power factor correction circuit; a n is the first calculation factor of the nth input voltage operation cycle, b n is the second calculation factor of the nth input voltage operation cycle, a n +b n =1,a ns =1,a n <a n+1 , b n >b n+1 .

6. The control method according to any one of claims 1 to 5, It is characterized in that After determining the input voltage of the phase-locked loop, it also includes: According to the phase-locked loop input voltage, filtering and phase locking are performed in the phase-locked loop to determine the input voltage phase value of the power factor correction circuit; The operation of the switch tube is controlled according to the input voltage phase value.

7. A control device for a power factor correction circuit, It is characterized in that include: A detection module is configured to obtain a startup state of an inverter load; The control module is configured to determine the input voltage of the phase-locked loop according to the current input voltage and current input current of the power factor correction circuit if the inverter load is not started; and to determine the input voltage of the phase-locked loop according to the current input voltage of the power factor correction circuit if the inverter load is started.

8. A control device for a power factor correction circuit, comprising a processor and a memory storing program instructions, It is characterized in that The processor is configured to execute the control method for a power factor correction circuit according to any one of claims 1 to 6 when running the program instructions.

9. A smart home appliance, It is characterized in that Comprising a control device for a power factor correction circuit as described in claim 7 or 8.

10. A storage medium storing program instructions, It is characterized in that When the program instructions are executed, the control method for a power factor correction circuit according to any one of claims 1 to 6 is executed.

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