Patterned semiconductor substrate, preparation method thereof and micro-nano photoelectric / photonic device

Abstract

The invention discloses a patterned semiconductor substrate, a preparation method thereof and a micro-nano photoelectric / photonic device, the semiconductor substrate comprises at least one of a lithium niobate substrate and a lithium tantalate substrate, and the method comprises the following steps: forming a patterned mask layer on the surface of the semiconductor substrate; performing ion implantation treatment on the semiconductor substrate with the mask layer on the surface so as to form a damaged layer in an area, which is not covered by the mask layer, of the semiconductor substrate; and removing the mask layer, and carrying out wet etching treatment on the damaged layer to obtain a patterned semiconductor substrate. Therefore, according to the preparation method, the lithium niobate substrate or the lithium tantalate substrate can be damaged, then the damaged layer is selectively removed through wet etching, and the preparation method is beneficial for eliminating the isotropic etching problem easily occurring in the traditional wet etching process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a patterned semiconductor substrate and a preparation method thereof, and micro-nano optoelectronic / photonic devices. Background Art

[0002] Lithium niobate (LiNbO3, LN) and lithium tantalate (LiTaO3, LT) have been widely used in sensors and detectors due to their excellent piezoelectric and ferroelectric effects. Their acoustic properties are widely used in surface acoustic wave devices and thin film bulk acoustic wave resonator devices. Their electro-optical and nonlinear optical effects are widely used in optical devices such as optical waveguides, electro-optic modulators, optical phase modulators, and electro-optic Q-switches. In particular, single-crystal lithium niobate / lithium tantalate thin films not only possess the performance advantages of bulk materials but also provide strong optical mode confinement and high integration density. They can be used to fabricate ultra-high-performance compact modulators, broadband frequency combs, high-efficiency optical frequency converters, and single-photon sources. Therefore, higher requirements are placed on the processing technology of lithium niobate / lithium tantalate micro- and nanostructures.

[0003] It should be noted that the above statements are only used to provide background technical information related to this application and do not necessarily constitute prior art. Summary of the Invention

[0004] In a first aspect of the present application, a method for preparing a patterned semiconductor substrate is provided, wherein the semiconductor substrate comprises at least one of a lithium niobate substrate and a lithium tantalate substrate, the method comprising the following steps: forming a patterned mask layer on the surface of the semiconductor substrate; performing ion implantation on the semiconductor substrate having the mask layer on its surface to form a damaged layer in areas of the semiconductor substrate not covered by the mask layer; removing the mask layer and wet etching the damaged layer to obtain a patterned semiconductor substrate. Thus, the aforementioned preparation method can damage the lithium niobate substrate or the lithium tantalate substrate, and then selectively remove the damaged layer by wet etching. This preparation method helps to eliminate the isotropic etching problem that is prone to occur in traditional wet etching processes.

[0005] In some embodiments, forming a patterned mask layer on the surface of the semiconductor substrate further includes forming a barrier layer on the surface of the semiconductor substrate, whereby the barrier layer helps the implanted ions to damage the surface of the semiconductor substrate.

[0006] In some embodiments, the barrier layer has a thickness of 10 nm to 500 nm; and / or the barrier layer is formed by at least one of electron beam evaporation, atomic layer deposition, and magnetron sputtering. Thus, selecting an appropriate barrier layer thickness and material can help prevent implanted ions from damaging the semiconductor substrate surface.

[0007] In some embodiments, in the magnetron sputtering method, the barrier layer comprises at least one of aluminum, copper, zinc, nickel, tungsten, titanium, and chromium. Thus, selecting a suitable barrier layer material helps prevent implanted ions from damaging the semiconductor substrate surface.

[0008] In some embodiments, in the atomic layer deposition method, the barrier layer comprises at least one of zirconium oxide, aluminum oxide, titanium oxide, silicon dioxide, and tantalum oxide. Thus, selecting a suitable barrier layer material can help prevent implanted ions from damaging the semiconductor substrate surface.

[0009] In some embodiments, the ion implantation process includes multiple implantation steps with different energies, which helps to control the depth of the damaged layer and the damage uniformity, thereby improving the quality of semiconductor substrate patterning.

[0010] In some embodiments, the ion implantation process satisfies at least one of the following conditions: the ion species of the ion implantation process include at least one of helium, hydrogen, nitrogen, oxygen, and argon; the implantation dose of the ion implantation process is 1×10 15 ions / cm 2 -9×10 16 ions / cm 2 ; The injection energy of the ion implantation process is 10KeV-1000KeV.

[0011] Therefore, selecting appropriate ion implantation process parameters helps to control the depth of the damaged layer and improve the quality of semiconductor substrate patterning.

[0012] In some embodiments, the wet etching solution includes at least one of a dilute hydrofluoric acid solution, a hydrofluoric acid solution, a nitric acid solution, or a mixture of hydrogen peroxide and a strong alkaline solution; and / or the mass fraction of the wet etching solution is 2% to 60%; and / or the wet etching time is 1 minute to 60 minutes. Thus, selecting the appropriate etching solution and etching conditions facilitates removal of damaged layers on the semiconductor substrate while preserving undamaged areas on the semiconductor substrate.

[0013] In some embodiments, the mask layer has a thickness of 200 nm to 5 μm; and / or the mask layer comprises a patterned photoresist layer. Thus, selecting an appropriate mask layer thickness and mask layer pattern facilitates patterning of the semiconductor substrate.

[0014] In a second aspect of the present application, a patterned semiconductor substrate is provided, which is prepared by the above method, so that the semiconductor substrate has a high-quality patterned structure.

[0015] In a third aspect, the present application provides a micro-nano optoelectronic / photonic device, including an optical waveguide structure of an electro-optical modulator, wherein the optical waveguide structure of the electro-optical modulator comprises the aforementioned patterned semiconductor substrate. Thus, the patterned semiconductor substrate can be used to manufacture micro-nano optoelectronic / photonic devices with high precision and high performance, meeting application requirements in various fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0017] Figure 1 This is a process flow chart of a patterned semiconductor substrate preparation process in one embodiment of the present application.

[0018] Figure 2 Schematic diagram of a semiconductor substrate subjected to five ion implantations in one embodiment of the present application.

[0019] Description of reference numerals:

[0020] 1. Semiconductor substrate; 2. Barrier layer; 3. Mask layer; 4. Damaged layer; 5. Etched area. DETAILED DESCRIPTION

[0021] Below, the embodiment of the patterned semiconductor substrate and its preparation method and micro-nano optoelectronic / photonic device of the present application is specifically disclosed in detail with appropriate reference to the accompanying drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there may be cases where detailed descriptions of well-known matters and repeated descriptions of actually the same structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate understanding by those skilled in the art. In addition, the drawings and the following description are provided to enable those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0022] " scope " disclosed in the application is limited in the form of lower limit and upper limit, and given range is limited by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundary of special range. The scope limited in this way can be to include end value or not include end value, and can be arbitrarily combined, that is, any lower limit can form a scope with any upper limit combination. For example, if the scope of 60-120 and 80-110 is listed for specific parameters, it is understood that the scope of 60-110 and 80-120 is also expected. In addition, if the minimum range value 1 and 2 listed, and if the maximum range value 3,4 and 5 are listed, then the following scope can all be expected: 1-3, 1-4, 1-5, 2-3, 2-4 and 2-5. In this application, unless otherwise specified, the numerical range " ab " represents the abbreviation of any real number combination between a and b, wherein a and b are all real numbers. For example, a numerical range of "0-5" indicates that all real numbers between "0-5" are listed herein, and "0-5" is simply an abbreviation for these numerical combinations. Furthermore, when a parameter is expressed as an integer ≥ 2, this is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0023] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0024] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0025] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by technicians in the technical field to which this application belongs; the terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application; unless otherwise specified, the numerical values ​​of the various parameters mentioned in this application can be measured using various measurement methods commonly used in the art (for example, they can be tested according to the methods given in the embodiments of this application).

[0026] In the description of this application, "A and / or B" may include the case of A alone, the case of B alone, or any of the cases of A and B, where A and B are only used for example, and may be any technical feature connected by "and / or" in this application.

[0027] Lithium niobate crystals and lithium tantalate crystals are hard and brittle, and their chemical properties are stable. They are materials that are difficult to etch. The main etching methods at present are wet etching and dry etching. For dry etching, although it is suitable for the precision processing of lithium niobate crystals and lithium tantalate crystals, its equipment cost is high and the etching rate is relatively slow, which makes it unsuitable for large-scale industrial production. For wet etching, chromium is mainly used as a mask layer. The lithium niobate crystal or lithium tantalate crystal with a patterned mask layer is directly placed in a hydrofluoric acid solution, and the surface of the lithium niobate crystal or lithium tantalate crystal that is not covered by the chromium mask layer is etched. Due to the flow characteristics of the liquid, it is impossible to etch in only a single direction during the wet etching process. The area below the chromium mask layer will also be corroded, and the etching width and the verticality of the etching side wall cannot be accurately controlled.

[0028] In a first aspect of the present application, a method for preparing a patterned semiconductor substrate is provided, wherein the semiconductor substrate comprises at least one of a lithium niobate substrate and a lithium tantalate substrate, the method comprising the following steps: forming a patterned mask layer on the surface of the semiconductor substrate; performing ion implantation on the semiconductor substrate having the mask layer on the surface to form a damage layer in the area of ​​the semiconductor substrate not covered by the mask layer; removing the mask layer and wet etching the damage layer to obtain the patterned semiconductor substrate. Thus, the aforementioned preparation method can selectively damage the lithium niobate substrate or the lithium tantalate substrate, and then remove the damage layer by wet etching. This preparation method helps to eliminate the isotropic etching problem that is prone to occur in traditional wet etching processes.

[0029] In some embodiments, the lithium niobate substrate comprises at least one of a lithium niobate-on-insulator (LNOI) film and a lithium niobate wafer. Taking the lithium niobate-on-insulator (LNOI) film as an example, the LNOI substrate sequentially comprises a substrate layer, a low-refractive-index oxide layer, and a high-refractive-index device layer. Specifically, the substrate layer may be a silicon layer, the low-refractive-index oxide layer may be a silicon dioxide layer, and the high-refractive-index device layer may be a single-crystalline lithium niobate film.

[0030] The present application does not limit the thickness of the single-crystal lithium niobate film, which can be specifically selected according to actual needs. For example, in some embodiments, the thickness of the single-crystal lithium niobate film is 200nm-1000nm.

[0031] As an example, the thickness of the single crystal lithium niobate thin film may be 200 nm, 400 nm, 600 nm, 800 nm, or 1000 nm.

[0032] In some embodiments, taking a lithium niobate wafer as an example, the diameter of the lithium niobate wafer is 99.8 mm-100.2 mm, and the thickness of the lithium niobate wafer is 0.2 mm-0.7 mm.

[0033] As an example, the diameter of the lithium niobate wafer may be 99.8 mm, 99.9 mm, 100 mm, 100.1 mm, or 100.2 mm.

[0034] As an example, the thickness of the lithium niobate wafer may be 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, or 0.7 mm.

[0035] In some embodiments, the lithium tantalate substrate comprises at least one of a lithium tantalate-on-insulator (LTOI) film and a lithium tantalate wafer. Taking the lithium tantalate-on-insulator (LTOI) film as an example, the LTOI film sequentially comprises a substrate layer, a low-refractive-index oxide layer, and a high-refractive-index device layer. Specifically, the substrate layer may be a silicon layer, the low-refractive-index oxide layer may be a silicon dioxide layer, and the high-refractive-index device layer may be a single-crystalline lithium tantalate film. This application does not impose any restrictions on the thickness of the single-crystalline lithium tantalate film, and the thickness may be selected based on actual needs.

[0036] In some embodiments, taking a lithium tantalate wafer as an example, the diameter of the lithium tantalate wafer is 99.8 mm-100.2 mm, and the thickness of the lithium tantalate wafer is 0.2 mm-0.7 mm.

[0037] As an example, the diameter of the lithium tantalate wafer may be 99.8 mm, 99.9 mm, 100 mm, 100.1 mm, or 100.2 mm.

[0038] As an example, the thickness of the lithium tantalate wafer may be 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, or 0.7 mm.

[0039] In some embodiments, reference Figure 1 In step (1), the semiconductor substrate 1 needs to be cleaned before use to remove contaminants attached to the surface of the semiconductor substrate.

[0040] In some embodiments, in the cleaning step, the cleaning solvent used includes at least one of acetone, ethanol, and deionized water.

[0041] In some embodiments, the cleaning step comprises, in sequence, acetone cleaning, ethanol cleaning, and deionized water cleaning, whereby the acetone cleans away contaminants on the surface of the semiconductor substrate, the ethanol cleans away residual acetone on the surface of the semiconductor substrate, and the deionized water cleans away residual ethanol on the surface of the semiconductor substrate.

[0042] In some embodiments, the washing step is included at least once.

[0043] In some embodiments, the semiconductor substrate needs to be dried after cleaning.

[0044] In some embodiments, the surface moisture of the semiconductor substrate needs to be dried before drying to prevent water stains from forming on the surface of the semiconductor substrate.

[0045] In some embodiments, the semiconductor substrate is baked at 80° C.-100° C.

[0046] As an example, the drying temperature may be 80°C, 85°C, 90°C, 95°C or 100°C.

[0047] In some embodiments, reference Figure 1 In step (2) of the present invention, a barrier layer 2 is formed on the surface of the semiconductor substrate 1. Thus, during the ion implantation process, the implanted ions can just pass through the barrier layer and reach the surface of the semiconductor substrate, thereby achieving the purpose of damaging the surface of the semiconductor substrate.

[0048] In some embodiments, the barrier layer has a thickness of 10 nm to 500 nm. For example, the barrier layer may have a thickness of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm.

[0049] In some embodiments, a method of forming the barrier layer includes at least one of electron beam evaporation, atomic layer deposition, and magnetron sputtering.

[0050] In some embodiments, in the magnetron sputtering method, the material of the barrier layer includes at least one of aluminum, copper, zinc, nickel, tungsten, titanium, and chromium.

[0051] In some embodiments, in the atomic layer deposition method, the material of the barrier layer includes at least one of zirconium oxide, aluminum oxide, titanium oxide, silicon dioxide, and tantalum oxide.

[0052] In some embodiments, reference Figure 1 Step (3) in the above step forms a patterned mask layer 3 on the surface of the barrier layer 2. This forms a protective region on the semiconductor substrate covering the mask layer to prevent ion damage; while allowing ions to precisely process the region not covered by the mask layer, forming a damaged layer.

[0053] In some embodiments, the mask layer has a thickness of 200 nm to 5 μm.

[0054] As an example, the thickness of the mask layer may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0055] In some embodiments, the mask layer includes a patterned photoresist layer.

[0056] In some embodiments, the photoresist includes a negative photoresist. Specifically, the negative photoresist may be AZ5214E. Therefore, the choice of photoresist not only affects the masking effect of the mask layer, but also may affect the stability of the ion implantation process. High-quality photoresist can also improve production efficiency.

[0057] In some embodiments, a method for preparing a mask layer comprises the following steps:

[0058] A photoresist is spin-coated on the surface of the barrier layer using a spin coating method; the photoresist is then dried to form a photoresist layer; after the photoresist layer is cooled, the photoresist layer is patterned using a photolithography process to form a mask layer.

[0059] In some embodiments, the drying temperature is 80°C-100°C.

[0060] As an example, the drying temperature may be 80°C, 85°C, 90°C, 95°C or 100°C.

[0061] In some embodiments, the drying time is 5 min to 30 min.

[0062] As an example, the drying time may be 5 min, 10 min, 15 min, 20 min, 25 min or 30 min.

[0063] In some embodiments, the photolithography process includes at least one of ultraviolet exposure and electron beam exposure.

[0064] In some embodiments, reference Figure 1 In step (4), ion implantation is performed on the semiconductor substrate 1 having the mask layer 3 on its surface to form a damaged layer 4 in an area of ​​the semiconductor substrate 1 not covered by the mask layer 3.

[0065] The ion implantation process accelerates charged ions in a vacuum and then directs them toward the material to be modified. These ions penetrate the material's surface and embed themselves within it. The ions collide with atoms within the material, altering the chemical composition and physical properties of the implanted region. Ion implantation causes numerous point defects within the material, such as vacancies and interstitial atoms, as well as compound defects formed by vacancies combining with other impurities. This is called implantation damage, forming a damaged layer within the material. High-energy ions can penetrate deeper into the material, so the implantation depth is determined by the implantation energy. Adjusting the implantation depth can adjust the thickness of the damaged layer.

[0066] In some embodiments, the ion implantation process includes multiple implantation steps at varying energies. A single ion implantation may create a region with a steeper concentration gradient at a certain depth, known as ion accumulation. This can lead to uneven material damage and affect the efficiency of subsequent wet etching. Therefore, multiple implantation steps with varying energies help control the depth and uniformity of the damaged layer, improving the quality of semiconductor substrate patterning.

[0067] In some embodiments, the ion implantation energy is gradually increased during multiple implantation steps at different energies during the ion implantation process. Therefore, when a barrier layer is provided on the semiconductor substrate, an implantation energy can be selected so that the ions just penetrate the barrier layer, reaching the surface of the semiconductor substrate and damaging the semiconductor substrate surface. The ion implantation energy is then increased to damage the internal materials of the semiconductor substrate. The entire ion implantation process involves the ions slowly penetrating the lithium niobate or lithium tantalate material, which helps promote uniformity of the damaged layer and improve the quality of semiconductor substrate patterning.

[0068] In some embodiments, the number of implantations is at least one. As an example, the number of implantations may be 1, 2, 3, 4, 5, 6, 7, 8, or 9. Thus, the number of implantations in the ion implantation process is selected based on the desired depth of the damaged layer.

[0069] In some embodiments, the ion implantation process satisfies at least one of the following conditions:

[0070] The ion species used in the ion implantation process include at least one of helium, hydrogen, nitrogen, oxygen, and argon;

[0071] The implantation dose of the ion implantation process is 1×10 15 ions / cm 2 -9×10 16 ions / cm 2 ;

[0072] The implantation energy of the ion implantation process is 10KeV-1000KeV.

[0073] Therefore, selecting appropriate ion implantation process parameters can help control the depth of the damaged layer, achieve customized modification of the semiconductor substrate, and improve the quality of semiconductor substrate patterning.

[0074] In some embodiments, the ion implantation process has an implantation dose of 1×10 15 ions / cm 2 -9×10 16 ions / cm 2 .

[0075] As an example, the implantation dose of the ion implantation process may be 1×1015 ions / cm 2 , 5×10 15 ions / cm 2 , 1×10 16 ions / cm 2 , 2×10 16 ions / cm 2 , 3×10 16 ions / cm 2 , 4×10 16 ions / cm 2 , 5×10 16 ions / cm 2 , 6×10 16 ions / cm 2 , 7×10 16 ions / cm 2 , 8×10 16 ions / cm 2 or 9×10 16 ions / cm 2 .

[0076] In some embodiments, the implantation energy of the ion implantation process is 10 KeV-1000 KeV.

[0077] As an example, the implantation energy of the ion implantation process may be 10 KeV, 100 KeV, 200 KeV, 300 KeV, 400 KeV, 500 KeV, 600 KeV, 700 KeV, 800 KeV, 900 KeV, or 1000 KeV.

[0078] In some embodiments, the ion implantation process must meet the following conditions: the ion species of the ion implantation process include at least one of helium, hydrogen, nitrogen, oxygen, and argon; the implantation dose of the ion implantation process is 1×10 15 ions / cm 2 -9×10 16 ions / cm 2 ; The injection energy of the ion implantation process is 10KeV-1000KeV.

[0079] In some embodiments, reference Figure 1 Step (5) in the embodiment of the present invention is to remove the mask layer 3 and / or the barrier layer 2.

[0080] In some embodiments, the solution for removing the mask layer includes at least one of acetone, 1-methyl-2-pyrrolidone, ethylpyrrolidone, dimethyl sulfoxide, and tetrahydrofuran.

[0081] In some embodiments, the solution for removing the barrier layer includes a mixed solution of a strong oxidizing agent and an acidic substance.

[0082] In some embodiments, the acidic substance includes at least one of sulfuric acid and hydrofluoric acid.

[0083] In some embodiments, the barrier layer is exemplified by a chromium layer, and the strong oxidant comprises chromate.

[0084] In some embodiments, the solvent of the mixed solution includes at least one of water, ethanol, and acetone.

[0085] In some embodiments, reference Figure 1 In step (6), the damaged layer 4 is wet-etched to eliminate the damaged layer 4 and obtain an etched area 5, thereby obtaining a patterned semiconductor substrate 1.

[0086] In some embodiments, the wet etching solution includes at least one of a dilute hydrofluoric acid solution, a hydrofluoric acid solution, a nitric acid solution, or a mixture of hydrogen peroxide and a strong alkaline solution. Thus, the wet etching solution can remove the damaged layer while leaving undamaged areas of the semiconductor substrate.

[0087] In some embodiments, the mass fraction of the wet etching solution is 2%-60%.

[0088] As an example, the mass fraction of the etching solution for wet etching can be 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 20%, 30%, 40%, 50% or 60%.

[0089] In some embodiments, the wet etching time is 1 min to 60 min.

[0090] As an example, the etching time of the wet etching may be 1 min, 2 min, 4 min, 6 min, 8 min, 10 min, 20 min, 30 min, 40 min, 50 min, or 60 min.

[0091] In some embodiments, the etching temperature of the wet etching is 20°C-40°C.

[0092] As an example, the etching temperature of the wet etching may be 20°C, 25°C, 30°C, 35°C, or 40°C.

[0093] Therefore, selecting the appropriate type of etching solution and etching conditions helps to remove the damaged layer while retaining the undamaged area of ​​the semiconductor substrate.

[0094] In some embodiments, step (6) further includes polishing the surface of the etched semiconductor substrate 1 .

[0095] In some embodiments, the polishing process includes at least one of chemical mechanical polishing, mechanical polishing, wet chemical polishing, ion beam polishing, and electrochemical polishing, thereby helping to improve the smoothness and flatness of the semiconductor substrate surface.

[0096] In some embodiments, a method of preparing a patterned semiconductor substrate, such as Figure 1 As shown, the method comprises the following steps: step (1) cleaning a semiconductor substrate 1, wherein the material of the area to be patterned of the semiconductor substrate 1 is lithium niobate or lithium tantalate; step (2) forming a barrier layer 2 on the surface of the semiconductor substrate 1, i.e., the surface of the lithium niobate material or the lithium tantalate material; step (3) forming a mask layer 3 on the surface of the barrier layer 2, and then performing photolithography on the mask layer 3 to form a patterned mask layer 3; step (4) performing at least one ion implantation treatment on the semiconductor substrate 1 having the mask layer 3 on the surface to form a damaged layer 4 in the area of ​​the semiconductor substrate 1 not covered by the mask layer 3; step (5) removing the mask layer 3 and the barrier layer 2; step (6) performing a wet etching treatment on the damaged layer 4 to form an etched area 5 on the surface of the semiconductor substrate 1, and polishing the surface to obtain a patterned semiconductor substrate 1.

[0097] In a second aspect of the present application, a patterned semiconductor substrate is provided, which is prepared by the aforementioned method, thereby patterning the surface of the semiconductor substrate, and the etched region of the semiconductor substrate has a high aspect ratio and good sidewall smoothness.

[0098] In the third aspect of the present application, the present application provides a micro-nano optoelectronic / photonic device, including an optical waveguide structure of an electro-optical modulator, and the optical waveguide structure of the electro-optical modulator includes the aforementioned patterned semiconductor substrate. Thus, the patterned semiconductor substrate can be used to manufacture micro-nano optoelectronic / photonic devices with high precision and high performance to meet the application needs of different fields. Thus, the patterned semiconductor substrate can be used to manufacture micro-nano optoelectronic / photonic devices with high precision and high performance to meet the application needs of different fields. In addition, the present application can realize batch etching of lithium niobate / lithium tantalate wafers or thin films, with low processing costs, and is suitable for large-scale production and commercialization of lithium niobate / lithium tantalate micro-nano devices.

[0099] The present invention will be described below by way of specific examples. It should be noted that the following examples are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Where specific techniques or conditions are not specified in the examples, they are determined according to the techniques or conditions described in the literature in this area or according to the product specifications. Reagents or instruments not specified by manufacturer are all commercially available conventional products.

[0100] Example 1

[0101] In this embodiment, lithium niobate wafer is selected for etching, with a thickness of 500 μm and a tangential direction X. A method for preparing a patterned semiconductor substrate comprises the following steps:

[0102] (1) Chromium plating: The clean surface of the lithium niobate substrate is subjected to magnetron sputtering treatment to grow a 100 nm thick chromium metal layer on the surface of the lithium niobate, which serves as a barrier layer.

[0103] (2) Photolithography. Spin-coat the negative photoresist AZ5214E ​​on the chromium metal surface with a thickness of 500 nm. Then, bake the lithium niobate substrate in a 90°C oven for 20 minutes and then take it out to cool. Then, use ultraviolet exposure to achieve patterning of the photoresist layer.

[0104] (3) Ion implantation. The ion implantation machine is set to inject hydrogen ions, and the implantation dose is set to 5×10 15 ions / cm 2 , set five groups of injection energies: 20keV, 30keV, 40keV, 50keV and 60keV, and inject the injection energy from the least to the most into the lithium niobate substrate processed in step 2, where the maximum energy corresponds to a depth of 400nm, such as Figure 2 As shown in the figure, during the ion implantation process, the incident direction of the sample was offset by 7° to prevent channeling. After the ion implantation, the photoresist layer and barrier layer were removed. The residual photoresist on the surface of the lithium niobate substrate was washed with acetone solution, and then the chromium metal layer was removed with a chromium etching solution (a mixture of potassium chromate and sulfuric acid).

[0105] (4) Etching. The lithium niobate substrate processed in step 3 is immersed in an etching solution, wherein the etching solution is a hydrofluoric acid solution with a mass fraction of 44.1%. After the lithium niobate substrate is immersed at 25°C for 5 minutes, the damaged layer on the lithium niobate substrate is corroded to form an etched area. Finally, the etching solution remaining on the surface of the lithium niobate substrate is removed; the surface of the lithium niobate substrate is polished using a chemical mechanical polishing process to obtain a smooth lithium niobate substrate.

[0106] Example 2

[0107] A lithium niobate on insulator (LNOI) thin film was prepared, cut in the X direction. The LNOI thin film comprises, in sequence, a substrate layer, a low-refractive-index oxide layer, and a high-refractive-index device layer. Specifically, the substrate layer is a 400μm-thick silicon layer; the low-refractive-index oxide layer is a 4.7μm-thick silicon dioxide layer; and the high-refractive-index device layer is a 600nm-thick lithium niobate single-crystal thin film.

[0108] Specifically, the etching method of this embodiment includes the following steps:

[0109] (1) Chromium plating: The clean surface of the lithium niobate film is subjected to magnetron sputtering treatment to grow a 100 nm thick chromium metal layer on the surface of the lithium niobate, which serves as a barrier layer.

[0110] (2) Photolithography. Spin-coat the negative photoresist AZ5214E ​​on the surface of the metallic chromium with a thickness of 500 nm. Then, bake the lithium niobate film in a 90°C oven for 20 minutes and then take it out to cool. Then, use ultraviolet exposure to achieve patterning of the photoresist layer.

[0111] (3) Ion implantation. The ion implantation machine is set to inject hydrogen ions, and the implantation dose is set to 5×10 15 ions / cm 2 Four implantation energies were set: 20keV, 30keV, 40keV, and 50keV, with a maximum depth of 300nm. During the ion implantation process, the incident direction of the sample was offset by 7° to prevent channeling. After the ion implantation, the residual photoresist on the surface of the lithium niobate film was washed away with acetone solution, and the chromium metal layer was then removed using a chromium etching solution.

[0112] (4) Etching. The lithium niobate film processed in step 3 is immersed in an etching solution, wherein the etching solution is a hydrofluoric acid solution with a mass fraction of 44.1%. The lithium niobate film is immersed at 25°C for 5 minutes to remove the etching solution remaining on the surface of the lithium niobate film and polish it to obtain a smooth rectangular optical waveguide structure.

[0113] Example 3

[0114] The difference between Example 3 and Example 2 is that no barrier layer is provided, and the injected ions are not lost by the barrier layer and directly pass through the surface of the lithium niobate film. That is, the surface of the lithium niobate film is not damaged by the ions and cannot be directly etched by the hydrofluoric acid solution of Example 2. Therefore, the etching solution of Example 3 is a solution composed of a mixture of a 40% by mass HF solution and a 68% by mass HNO3 solution in a volume ratio of 1:3. The lithium niobate film of Example 3 is etched at room temperature for 1.5 hours, and the intermediate product of the wiping etching reaction (i.e., the reaction product of hydrofluoric acid and lithium niobate, which will hinder the etching process) is removed every 0.5 hours. The internal structure of the lithium niobate film is damaged by the ion damage, while the surface is not damaged. After the surface of the lithium niobate film is completely etched, due to the etching action of the high-efficiency etching solution of Example 3, the etching rate of the lithium niobate film gradually increases, and the etched cross section gradually increases. After the etching is completed, a trapezoidal optical waveguide structure is obtained.

[0115] It should be noted that the present application is not limited to the above-mentioned embodiments. The above-mentioned embodiments are merely examples, and any embodiments having substantially the same structure and effect as the technical concept within the scope of the present application are all included in the technical scope of the present application. In addition, without departing from the scope of the present application, any other embodiments that can be conceived by those skilled in the art and that combine some of the constituent elements in the embodiments are also included in the scope of the present application.

Claims

1. A method for preparing a patterned semiconductor substrate, characterized in that: The semiconductor substrate comprises at least one of a lithium niobate substrate and a lithium tantalate substrate, and the method comprises the following steps: forming a patterned mask layer on the surface of the semiconductor substrate; Performing ion implantation on the semiconductor substrate having the mask layer on its surface to form a damaged layer in an area of ​​the semiconductor substrate not covered by the mask layer; The mask layer is removed, and the damaged layer is wet-etched to obtain a patterned semiconductor substrate.

2. The method according to claim 1, characterized in that: The step of forming a patterned mask layer on the surface of the semiconductor substrate further includes forming a blocking layer on the surface of the semiconductor substrate.

3. The method according to claim 2, characterized in that The thickness of the barrier layer is 10nm-500nm; and / or, The method of forming the barrier layer includes at least one of electron beam evaporation, atomic layer deposition and magnetron sputtering.

4. The method according to claim 3, characterized in that In the magnetron sputtering method, the material of the barrier layer includes at least one of aluminum, copper, zinc, nickel, tungsten, titanium and chromium; and / or, In the atomic layer deposition method, the material of the barrier layer includes at least one of zirconium oxide, aluminum oxide, titanium oxide, silicon dioxide, and tantalum oxide.

5. The method according to any one of claims 1 to 4, characterized in that: The ion implantation process includes multiple implantation steps with different energies.

6. The method according to claim 5, characterized in that The ion implantation process satisfies at least one of the following conditions; The ion type of the ion implantation process includes at least one of helium, hydrogen, nitrogen, oxygen and argon; The implantation dose of the ion implantation process is 1×10 15 ions / cm 2 -9×10 16 ions / cm 2 ; The implantation energy of the ion implantation process is 10KeV-1000KeV.

7. The method according to any one of claims 1 to 4, characterized in that: The wet etching solution includes at least one of a dilute hydrofluoric acid solution, a hydrofluoric acid solution, a nitric acid solution, a mixed solution of hydrogen peroxide and a strong alkali solution; and / or, The mass fraction of the wet etching solution is 2%-60%; and / or, The etching time of the wet etching is 1 min-60 min.

8. The method according to any one of claims 1 to 4, characterized in that: The thickness of the mask layer is 200 nm-5 μm; and / or the mask layer includes a patterned photoresist layer.

9. A patterned semiconductor substrate, characterized in that: The method is prepared by any one of claims 1 to 8.

10. A micro-nano optoelectronic / photonic device, characterized in that: An optical waveguide structure comprising an electro-optic modulator, wherein the optical waveguide structure of the electro-optic modulator comprises the patterned semiconductor substrate according to claim 9.

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