Dynamic on-resistance test circuit of GaN high electron mobility transistor

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a dynamic on-resistance test circuit of a GaN high electron mobility transistor. The circuit comprises a UIS test circuit, a DPT test circuit, a clamping circuit and a driving circuit, and is characterized in that two semiconductor switches can gate the UIS test circuit and the DPT test circuit, UIS test and subsequent DPT test can be carried out under the condition that a device is not moved, and the introduced clamping circuit can indirectly test the conduction voltage drop of the tested device. The test circuit can be used for testing package-level device products, provides a basis for production, research and development, characteristic characterization, mass production test, reliability evaluation and application evaluation of GaN HEMT, integrates UIS and DPT test circuits together compared with a traditional test circuit, improves the test efficiency and reduces the test cost. Meanwhile, errors caused by the influence of the process and the environment on the result when the device is transferred due to the fact that the time from the application of the electric pressure to the DPT test is too long are reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a dynamic on-resistance test circuit for a GaN high electron mobility transistor. Background Art

[0002] GaN HEMT power devices have the advantages of high operating frequency, low loss and high temperature resistance. They can effectively improve the efficiency and power density of power electronic systems. Therefore, they have broad application prospects in data centers, motor drives, aerospace and other fields. With the continuous improvement of the commercialization of GaN HEMT, the study of device robustness has become one of the research hotspots in the industry. In actual power electronic systems, under high-speed switching, high di / dt and dv / dt will couple with parasitic components in the circuit to generate electrical stress, affecting the performance of the device. Under electrical stress conditions such as gate voltage and drain voltage, the internal traps of GaN HEMT devices will capture and emit carriers, resulting in device parameter degradation, increased dynamic on-resistance and other problems, and significantly increasing device losses.

[0003] Since Si-based power devices have parasitic PN junctions and withstand voltage through PN junctions, when unclamped inductive load switching (UIS) occurs, if the induced electromotive force generated by the inductive load exceeds the PN junction avalanche voltage, the energy stored in the inductor will be dissipated through the parasitic PN junction in the form of avalanche overcurrent. However, GaN HEMTs have no parasitic PN junctions and cannot dissipate the energy stored in the inductor through avalanche overcurrent like Si-based power devices. Therefore, the UIS robustness test method and degradation mechanism based on Si-based power devices cannot be directly applied to GaN HEMTs. Studying the degradation of GaN HEMT device characteristics after single or repeated UIS electrical stress is of great significance to revealing the robustness of GaN HEMT devices in the process of unclamped inductive load switching. It is necessary to propose a dynamic on-resistance test circuit for GaN HEMT devices under UIS electrical stress conditions to realize the dynamic on-resistance degradation test of devices within microseconds to milliseconds after the UIS electrical stress ends. Summary of the invention

[0004] In view of the above problems, the present invention proposes a dynamic on-resistance test circuit for a gallium nitride high electron mobility transistor under unclamped inductive load switching conditions. Compared with the traditional test circuit, the circuit integrates two functions: applying unclamped inductive load switch (UIS) electrical stress to the device under test and a double pulse (DPT) test for measuring the dynamic on-resistance of the device.

[0005] The technical solution adopted by the present invention is:

[0006] A dynamic on-resistance test circuit for a GaN high electron mobility transistor, comprising a UIS test circuit, a DPT test circuit, a clamp circuit and a drive circuit;

[0007] The UIS test circuit is used to apply an unclamped inductive load switch (UIS) electrical stress to the device under test, and includes a first DC power supply, a first capacitor, a first inductor and a first semiconductor switch, wherein the first capacitor is connected in parallel with the first DC power supply, one end of the first semiconductor switch is connected to the positive electrode of the first DC power supply through the first inductor, and the other end of the first semiconductor switch is connected to the drain of the GaN device under test; the negative electrode of the first DC power supply is grounded;

[0008] The DPT test circuit is used to measure the double pulse (DPT) of the dynamic on-resistance of the device, and includes a second DC power supply, a second capacitor, a second inductor, a first diode, and a second semiconductor switch. The second capacitor is connected in parallel with the second DC power supply, one end of the second semiconductor switch is connected to the anode of the first diode and one end of the second inductor, the other end of the second inductor is connected to the cathode of the first diode and the positive electrode of the second DC power supply, and the other end of the second semiconductor switch is connected to the drain of the GaN device under test; the negative electrode of the second DC power supply is grounded;

[0009] The clamping circuit is used to maintain a stable forward voltage when the device under test is turned off, and includes a third DC power supply, a resistor, a second diode, and a Zener diode. The anode of the second diode and the cathode of the Zener diode are connected to the positive electrode of the third DC power supply through the resistor, and the cathode of the second diode is connected to the drain of the GaN device under test; the negative electrode of the third DC power supply and the anode of the Zener diode are grounded;

[0010] The driving circuit is connected to the gate of the GaN device under test and is used to drive the GaN device under test;

[0011] The source of the GaN device under test is grounded.

[0012] The working mode of the circuit of the present invention is as follows: first, after adjusting the pulse width, pulse frequency, duty cycle, DC power supply voltage, gate drive voltage, single test time of continuous pulses, and inductance value, the DC power supply of the UIS test circuit, the semiconductor switch of the UIS test circuit, and the DC power supply of the clamping circuit are turned on, and the control circuit drives the gate signal of the device under test to turn on the transistor, and the circuit enters the UIS test mode. The gate signal is controlled to turn off the transistor and the DC power supply of the UIS test circuit are turned off at the same time, and the UIS test is performed. When performing the UIS test, the DC power supply of the UIS test circuit, the semiconductor switch of the UIS test circuit, and the DC power supply of the clamping circuit are first turned off, and the control circuit drives the gate signal of the device under test to turn on the transistor. Then, the gate signal is controlled to turn off the transistor and the DC power supply of the UIS test circuit are turned off at the same time, and a UIS test is completed at this time.

[0013] After applying UIS electrical stress, DPT test can be performed. Turn off the DC power supply of UIS test circuit and the semiconductor switch of UIS test circuit, set the on / off pulse width, gate turn-off voltage, gate drive voltage, pulse frequency, duty cycle, voltage reverse bias stress time, DC power supply voltage, and inductance value, turn on the DC power supply of DPT test circuit and the semiconductor switch of DPT test circuit, and control the circuit to drive the gate signal of the device under test to turn on the transistor, and the circuit enters the DPT test mode. In the second pulse, when the drain conduction current rises to the set value, the voltage at the anode of the clamping circuit diode and the drain current of the device under test are measured at the same time, and the dynamic on-resistance can be calculated.

[0014] The beneficial effects of the present invention are that the present invention can be used for packaging-level device product testing, and provide a basis for the production research and development, characteristic characterization, mass production testing, reliability evaluation and application evaluation of GaN HEMT. Compared with traditional test circuits, the present invention integrates UIS and DPT test circuits together, thereby improving test efficiency and reducing errors caused by the long time from applying voltage pressure to DPT testing and the influence of the process and environment on the results when transferring devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the circuit structure in the present invention;

[0016] Figure 2 A schematic diagram of the working timing of the circuit for testing the system's ability to survive (robustness) of the gallium nitride high electron mobility transistor non-clamped inductive load switch under abnormal and dangerous conditions in the present invention;

[0017] Figure 3 The present invention is a schematic diagram of the working principle of the clamping circuit of the GaN high electron mobility transistor non-clamped inductive load switch in abnormal and dangerous situations. The figure (a) shows the current path in the clamping circuit when the DUT is turned off; the figure (b) shows the current path in the clamping circuit when the DUT is turned on.

[0018] Figure 4 A simplified flow chart of stress test for testing the system survival capability (robustness) of the GaN high electron mobility transistor non-clamped inductive load switch in abnormal and dangerous situations in the present invention: (a) is a single / multiple UIS stress test; (b) is a single / multiple DPT test after completing UIS electrical stress;

[0019] Figure 5 A schematic diagram of single / repeated UIS stress test waveforms of a test circuit for the ability (robustness) of the system to survive abnormal and dangerous situations of a non-clamped inductive load switch of a gallium nitride high electron mobility transistor in the present invention;

[0020] Figure 6The single / repeated DPT stress test waveform diagram of the GaN high electron mobility transistor unclamped inductive load switch in the present invention is a test circuit for the system's ability to survive (robustness) under abnormal and dangerous conditions. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is described in detail below in conjunction with the attached drawings.

[0022] like Figure 1 The figure shows the robustness test circuit of the gallium nitride high electron mobility transistor non-clamped inductive load switch of the present invention, wherein the UIS test circuit is gated when the semiconductor switch SW1 is turned on, and the DPT test circuit is gated when the semiconductor switch SW2 is turned on, so that the two circuits will not interfere with each other during the test. Figure 2 The figure shows the working sequence diagram of the test circuit of the present invention. In the UIS test stage, that is, when SW1 is turned on and SW2 is turned off, the UIS test circuit controls the on and off of the device under test through the function generator. When the device under test is turned on, the power supply V DC1 To inductor L UIS When the device is turned off, the inductor L UIS A pulse greater than the charging voltage is generated and applied to the device under test. ON ) is the inductor charging time to change the inductor storage energy when the circuit is turned on. High voltage DC power supply V DC1 To inductor L UIS Charging makes the current reach the preset value, I DS The device turns off and the UIS process occurs. The energy in the inductor rushes to the device, generating V at both ends of the device drain. PEAK UIS electrical stress, energy in the inductor and on-state pulse width (T ON After the UIS electrical stress ends, an adjustable recovery time t REC , the circuit enters the DPT test phase, that is, SW1 is turned off and SW2 is turned on, completing the test of dynamic on-resistance after UIS electrical stress. The DPT test circuit controls the on and off of the device under test through a function generator. When the device is turned on for the first time, V DC2 To inductor L DPT The device is then turned off, and the inductor current forms a current loop through the freewheeling diode D. After a set interval, the device is turned on for the second time, and the inductor current starts to increase from the preset value obtained at the first turn-on (the decrease during the turn-off can be ignored).

[0023] During UIS and DPT tests, when the device under test is turned off, a high voltage is generated at the drain of the device. DS >V M , diode D SIn the reverse bias state, the current path in the clamp circuit is as follows Figure 3 As shown, V M D is clamped to the same order of magnitude as the on-state voltage drop of the device under test. Z When the device under test is turned on, V M >V DS , V DC3 To D S The junction capacitance is charged until D S Forward conduction, the current path is as follows Figure 3 As shown, at this time V M D S Forward conduction voltage drop V F and the DUT conduction voltage drop V DS(ON) The dynamic on-resistance of the device can be obtained by dividing the on-voltage drop when the device is turned on for the second time by the current flowing through the device.

[0024] The simplified flow chart of the stress test for testing the system's ability to survive (robustness) of the gallium nitride high electron mobility transistor non-clamped inductive load switch under abnormal and dangerous conditions in the present invention is as follows: Figure 4 As shown, the circuit single / repetitive UIS stress test waveform is as follows Figure 5 As shown, the single / repeated DPT stress test waveform is as follows Figure 6 shown.

Claims

1. A dynamic on-resistance test circuit for a GaN high electron mobility transistor, characterized in that: Including UIS test circuit, DPT test circuit, clamp circuit and drive circuit; The UIS test circuit includes a first DC power supply, a first capacitor, a first inductor and a first semiconductor switch. The first capacitor is connected in parallel with the first DC power supply. One end of the first semiconductor switch is connected to the positive electrode of the first DC power supply through the first inductor, and the other end of the first semiconductor switch is connected to the drain of the GaN device under test. The negative electrode of the first DC power supply is grounded. The DPT test circuit includes a second DC power supply, a second capacitor, a second inductor, a first diode, and a second semiconductor switch. The second capacitor is connected in parallel with the second DC power supply. One end of the second semiconductor switch is connected to the anode of the first diode and one end of the second inductor. The other end of the second inductor is connected to the cathode of the first diode and the positive electrode of the second DC power supply. The other end of the second semiconductor switch is connected to the drain of the GaN device under test. The negative electrode of the second DC power supply is grounded. The clamping circuit includes a third DC power supply, a resistor, a second diode, and a Zener diode. The anode of the second diode and the cathode of the Zener diode are connected to the positive electrode of the third DC power supply through the resistor, and the cathode of the second diode is connected to the drain of the GaN device under test; the negative electrode of the third DC power supply and the anode of the Zener diode are grounded; The driving circuit is connected to the gate of the GaN device under test and is used to drive the GaN device under test; The source of the GaN device under test is grounded.

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