SBD integrated silicon carbide MOSFET capable of improving reverse freewheeling capability and preparation method of SBD integrated silicon carbide MOSFET

Abstract

The invention discloses an SBD integrated silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) capable of improving reverse freewheeling capability and a preparation method thereof. The device sequentially comprises a silicon carbide substrate, an N-type drift layer and an N-type carrier storage layer from bottom to top, the N + regions and the P + regions are alternately distributed at the upper part of the N-type carrier storage layer; the deep groove penetrates through the N + region and the P + region, and the bottom of the deep groove is located in the N-type carrier storage layer; the P-type buried layer is formed in the N-type carrier storage layer at the bottom of the deep trench; the source electrode is used for filling the deep grooves on the two sides of the central N + region and realizing a Schottky contact barrier with the N-type carrier storage layer on the side wall; the gate oxide layer covers the side wall and the bottom of the deep trench on the outermost side; the grid electrode covers the gate oxide layer and fills the deep groove on the outermost side; the P-type base region is formed in the N + region between the grid electrode and the source electrode and in the N-type carrier storage layer below the P + region; the passivation layer covers the surface of the grid electrode; and a source ohmic contact covering the surface of the device.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit device structure design, and in particular relates to an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability and a preparation method thereof. Background Art

[0002] SiC MOSFET devices are one of the excellent candidates for the next generation of power semiconductor device structures in many power conversion systems. Silicon carbide (SiC) is a compound semiconductor material composed of Si (silicon) and C (carbon). Its breakdown field strength is 10 times that of Si, and its bandgap width is 3 times that of Si. At the same withstand voltage level, SiC MOSFET devices have a much smaller specific on-resistance than Si-based devices. At the same time, SiC can achieve a high withstand voltage of more than 3KV through higher doping and thinner drift region thickness, so it is considered to be a power device material that exceeds the limit of Si. At the same time, SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), which is the same insulator as the oxide formed by Si oxidation. SiO2 has good performance as a passivation film in Si-based power devices, making it possible to manufacture the entire MOS-based device with SiC.

[0003] The reverse conduction capability of SiC device power transistors is very important in the actual switching process. Since the SiC body diode turn-on voltage is as high as about 2.7V, which seriously affects the switching performance, it is a reliable choice to integrate a unipolar diode with a low reverse conduction voltage into the SiC MOSFET to inactivate the body pin diode, such as SiC MOSFET with JBS diode, SiC-MOSFET with built-in SBD and SiC Switch-MOS. On the other hand, the p + Heterojunction diodes composed of polycrystalline silicon and n-type SiC have been experimentally proven to have the unipolar effect of SBDs.

[0004] In the current SiC integrated SBD solution, the use of high work function metals is the main option to reduce SBD leakage current, but this will result in a higher turn-on voltage for the SBD, thereby increasing switching losses. How to improve the third quadrant conduction capability of the SBD integrated MOSFET is the future development direction of SiC-MOS. Summary of the invention

[0005] The present invention discloses an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability, which comprises a silicon carbide substrate, an N-type drift layer and an N-type carrier storage layer in order from bottom to top;

[0006] N + Area and P +regions, alternately distributed on the upper part of the N-type carrier storage layer; deep trenches, penetrating the N + Area and P + region, the bottom of which is located in the N-type carrier storage layer; a P-type buried layer, formed in the N-type carrier storage layer at the bottom of the deep trench; a source, filling the central N + The deep trenches on both sides of the region realize the Schottky contact barrier with the N-type carrier storage layer on the sidewalls; the gate oxide layer covers the sidewalls and bottom of the outermost deep trench; the gate covers the gate oxide layer and fills the outermost deep trench; the P-type base region is formed between the gate and the source. + Area and P + In the N-type carrier storage layer below the region; a passivation layer covering the surface of the gate; a source ohmic contact covering the surface of the device, wherein the ohmic contact and the Schottky contact simultaneously serve as a reverse conduction mechanism, and during reverse continuous current flow, the ohmic contact part of the device source is first turned on at a low voltage, and then the Schottky diode is turned on, thereby achieving a lower reverse turn-on voltage of the device; in the blocking state, the ohmic contact source is pinched off by the Schottky barrier, so that the device has a lower reverse leakage current.

[0007] In the SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the source is a high work function metal, P + Polysilicon layer.

[0008] In the SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the gate is N + Polysilicon layer.

[0009] In the SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the doping concentration of the P-type buried layer is 1e18 / cm 3 Magnitude.

[0010] The present invention also discloses a method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability, comprising the following steps: epitaxially growing an N-type drift layer and an N-type carrier storage layer on a silicon carbide substrate; and then forming alternatingly distributed N-type carrier storage layers on the upper part of the N-type carrier storage layer by two times of photolithography and corresponding ion implantation. + Area, P + area; finally, N + Area and P +A P-type base region is formed in the N-type carrier storage layer below the region; deep trenches are formed with intervals, and the bottom of the trench is located in the N-type carrier storage layer; a continuously distributed oxide layer is deposited, the oxide layer is etched back, the oxide layer at the bottom of the trench is removed, and a sidewall and source ion implantation barrier layer is formed; ion implantation is performed to form a P-type buried layer at the bottom of the trench; all oxide layers are removed, and high-temperature annealing is performed to activate all implanted ions; in the central N + The deep trenches on both sides of the region form a source; a gate oxide layer is formed on the sidewall and bottom of the outermost deep trench; a gate is formed to cover the gate oxide layer and completely fill the outermost deep trench, and a Schottky contact barrier with the N-type carrier storage layer is realized on the sidewall; a passivation layer is deposited, and the source metal contact area is defined by photolithography and etching, and only the passivation layer on the surface of the gate on both sides is retained; a source ohmic contact is formed to cover the device surface, and then chemical mechanical polishing is performed, wherein the ohmic contact and the Schottky contact are simultaneously used as a reverse conduction mechanism, and the ohmic contact part of the source of the device is first turned on at a low voltage during reverse freewheeling, and then the Schottky diode is turned on, thereby realizing a lower reverse turn-on voltage of the device; in the blocking state, the ohmic contact source is pinched off by the Schottky barrier, so that the device has a lower reverse leakage current.

[0011] In the method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the source electrode is a high work function metal, P + Polysilicon layer.

[0012] In the method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the gate is N + Polysilicon layer.

[0013] In the method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the doping concentration of the P-type buried layer is 1e18 / cm 3 Magnitude.

[0014] Beneficial effects:

[0015] SiC double trench structure filled with high work function metals such as nickel (work function is about 5.1eV) / p + Polysilicon realizes a higher Schottky contact barrier with the N-type carrier storage layer on the SiC side wall. During reverse withstand voltage, the structure uses the MESFET depletion principle to pinch off; during reverse turn-on, the side wall Schottky barrier is lowered, providing a channel for the conduction of electrons in the source region.

[0016] The top of the polysilicon-SiC heterojunction diode structure is designed as an ohmic contact, which has a stronger reverse turn-on capability and can effectively reduce the switching loss of the device; during the longitudinal withstand voltage, the higher Schottky barrier of the heterojunction ensures the low leakage current of the device.

[0017] The heterojunction depletion region formed by the contact between the p+ polysilicon structure and SiC changes significantly with the bias voltage. Therefore, compared with the traditional SBD, this structure utilizes the combined effect of the ohmic contact and the Schottky contact during reverse conduction to achieve a lower diode reverse turn-on voltage.

[0018] The source double trench structure is adopted, and the gate and source trenches are defined by one-time photolithography and directional etching, and the process is relatively simple. The polysilicon used as the source trench effectively alleviates the electric field crowding of the gate trench, protects the gate oxide layer, and makes the device have better voltage resistance characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flow chart of a method for preparing an SBD-integrated silicon carbide MOSFET with improved reverse freewheeling capability.

[0020] Figure 2 to Figure 20 It is a structural schematic diagram of each stage of the SBD integrated silicon carbide MOSFET preparation method with improved reverse freewheeling capability. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0023] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, the various parts of the device can be made of materials known to those skilled in the art, or can be made of materials with similar functions developed in the future.

[0024] Figure 1 This is a flow chart of a method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability. Figure 1 As shown, the preparation method of the SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability comprises the following steps:

[0025] Step S1: epitaxially doping the silicon carbide substrate 100 at a concentration of 6e15 / cm 3 The N-type drift layer (N-Drift) 101 and the doping concentration are 2e16 / cm 3 The N-type carrier storage layer (N-CSL) 102 is formed, and the obtained structure is as follows Figure 2 Then, two photolithography steps and corresponding ion implantation steps are performed to form alternating heavily doped N-type carrier storage layers on the upper portion of the N-type carrier storage layer 102. + Area 103, P + Region 104, the resulting structure is as Figure 3 Finally, through one lithography and corresponding ion implantation, N + Area 103 and P + The N-type carrier storage layer 102 below the region 104 is doped with a concentration of 2e17 / cm 3 The P-base region (P-base) 105, the resulting structure is as follows Figure 4 As shown. Among them, N + The depth of region 103 is controlled to be about 0.2 μm to ensure a sufficient ohmic contact area above the SBD.

[0026] Step S2, defining the groove area by photolithography, etching to form deep grooves with a depth of 1.3 μm and a spacing distribution, the grooves penetrate N + Area 103, P + The region 104 and the P-type base region 105 are located at the bottom of the N-type carrier storage layer 102. The resulting structure is as follows Figure 5 As shown. The two deep trenches in the central area are used as source trenches, and the deep trenches on both sides of the periphery are used as gate trenches. The width of the source trench is about 0.2 μm, which is slightly narrower than the gate trench. Then, a continuously distributed oxide layer 106 is deposited, and the resulting structure is as shown. Figure 6 The oxide layer 106 is etched back to remove the oxide layer 106 at the bottom of the trench to form a sidewall and a source ion implantation barrier layer. The resulting structure is as shown in FIG. Figure 7 shown.

[0027] Step S3, forming a doping concentration of 1e18 / cm at the bottom of the trench by ion implantation 3 The P-type buried layer (P-well) 107 of the order of magnitude, the resulting structure is as follows Figure 8As shown. This concentration of buried layer implantation can effectively reduce the peak electric field of the device under withstand voltage, protect the gate oxide and the subsequent filled polysilicon heterojunction, and at the same time will not affect the reverse turn-on of the device. After that, all oxide layers 106 are removed, and annealing is performed at 1700℃ for 30 minutes to activate all implanted ions. The resulting structure is shown in Fig. 9 shown.

[0028] Step S4, depositing a doping concentration of 1e19 / cm 3 P + The polysilicon layer 108 fills each deep trench, and the resulting structure is as follows Fig.10 As shown, in the central N + The source trenches on both sides of region 103 form P + The polysilicon layer is used as the source to form a double trench source structure. + The polysilicon realizes a higher Schottky contact barrier with the N-type carrier storage layer on the SiC side wall. During reverse withstand voltage, the structure is pinched off using the MESFET depletion principle; during reverse turn-on, the sidewall Schottky barrier is lowered, providing a channel for the conduction of electrons in the source region. In addition, high work function metals with a work function of about 5.1eV, such as nickel, platinum and other high work function metals, can also be filled as the source. Then a layer of silicon nitride layer 109 is deposited on the surface of the device as a mask for etching back the polysilicon and subsequent gate oxide oxidation. The resulting structure is as follows: Fig.11 The silicon nitride layer 109 on the top of the gate trench on both sides of the periphery is removed by photolithography, and the resulting structure is as shown in FIG. Fig.12 shown.

[0029] Step S5, wet etching back the gate trench region P + The polysilicon layer 108 has a structure as shown in FIG. Fig.13 Then, the gate oxide is dry-oxidized at 1050°C for 130 minutes to form a 50nm thick gate oxide layer 110 at the bottom and sidewalls of the gate trench. At the same time, the gate oxide layer 110 is deposited at the bottom of the trench. The resulting structure is shown in FIG. Fig.14 As shown. Subsequently, N as the gate electrode is deposited over a large area. + The polysilicon layer 111 covers the device surface, and the resulting structure is as follows Fig.15 shown.

[0030] Step S6, depositing N + The polysilicon layer 111 is then etched back to a portion N + The polysilicon layer 111 exposes the surface of the silicon nitride layer 109 and makes the N + The upper surface of the polysilicon layer 111 is adjacent to the N + Area 103 and P + The upper surface of region 104 is flush with the gate, and the resulting structure is as follows Fig.16Then the silicon nitride barrier layer 109 is removed by etching, and the resulting structure is as shown in FIG. Fig.17 shown.

[0031] Step S7, depositing an oxide layer as a passivation layer 112, the resulting structure is as follows Fig.18 The source metal contact area is defined by photolithography, and the passivation layer 112 is etched, leaving only the passivation layer 112 on the gate surface on both sides. The resulting structure is as shown in FIG. Fig.19 shown.

[0032] Step S8, depositing metal nickel to form a source ohmic contact 113, and then chemically and mechanically polishing the top of the device to form a single cell structure. The resulting structure is as shown in FIG. Fig. 20 shown.

[0033] like Fig. 20 As shown, the SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability includes, from bottom to top, a silicon carbide substrate 100, an N-type drift layer 101 and an N-type carrier storage layer 102; + Area 103 and P + The regions 104 are alternately distributed on the upper portion of the N-type carrier storage layer 102; the deep trenches are alternately distributed and penetrate the N + Area 103 and P + Region 104, the bottom of which is located in the N-type carrier storage layer 102; P-type buried layer 107, formed in the N-type carrier storage layer 102 at the bottom of the deep trench; source 108, filling the central N + The deep trenches on both sides of the region 103 realize Schottky contact barriers with the N-type carrier storage layer on the sidewalls; the gate oxide layer 110 covers the sidewalls and bottom of the outermost deep trench; the gate 111 covers the gate oxide layer 110 and fills the outermost deep trench; the P-type base region 105 is formed between the gate 111 and the source 108 + Area 103 and P + In the N-type carrier storage layer 102 below the region 104; a passivation layer 112 covers the surface of the gate 111; and a source ohmic contact 113 covers the device surface.

[0034] The SiC double trench structure is filled with high work function metal / p+ polysilicon, and a higher Schottky contact barrier with the N-type carrier storage layer is realized on the SiC side wall. During reverse withstand voltage, the structure is pinched off using the MESFET depletion principle; during reverse turn-on, the side wall Schottky barrier is lowered, providing a channel for the conduction of electrons in the source region.

[0035] The top of the polysilicon-SiC heterojunction diode structure is designed as an ohmic contact, which has a stronger reverse turn-on capability and can effectively reduce the switching loss of the device; when the vertical withstand voltage is applied, the higher Schottky barrier of the heterojunction ensures the low leakage current of the device.+ The width W of the SiC platform between the polysilicon trenches mesa It needs to be optimized at around 0.35μm so that the device has good switching characteristics while avoiding the punch-through of reverse withstand voltage at high temperature.

[0036] The entire device adopts a source double trench structure, and the gate and source trenches are defined by one-time photolithography and directional etching, and the process is relatively simple. The polysilicon used as the source trench effectively alleviates the electric field crowding of the gate trench, protects the gate oxide layer, and makes the device have better voltage resistance characteristics. At the same time, the reverse transfer capacitance of the device is also reduced by about 70%, with a lower delay time during switching, further improving the switching efficiency.

[0037] The device designed in this patent uses both ohmic contact and Schottky contact as the reverse conduction mechanism: when the reverse current is flowing, the ohmic contact part of the device source is first turned on at a low voltage, and then the Schottky diode is turned on, achieving a lower reverse turn-on voltage of the device. In the blocking state, the ohmic contact source is pinched off by the Schottky barrier, so that the device has a lower reverse leakage current.

[0038] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. An SBD-integrated silicon carbide MOSFET with improved reverse freewheeling capability, It is characterized in that From bottom to top, it includes a silicon carbide substrate, an N-type drift layer, and an N-type carrier storage layer; N + Area and P + Regions are alternately distributed on the upper part of the N-type carrier storage layer; Deep trenches, running through the N + Area and P + region, the bottom of which is located in the N-type carrier storage layer; A P-type buried layer formed in the N-type carrier storage layer at the bottom of the deep trench; Source, fill the central N + The deep trenches on both sides of the region realize Schottky contact barriers with the N-type carrier storage layer on the sidewalls; A gate oxide layer covering the sidewalls and bottom of the outermost deep trench; A gate electrode, covering the gate oxide layer and filling the outermost deep trench; The P-type base region is formed between the gate and the source. + Area and P + In the N-type carrier storage layer below the region; A passivation layer covering the surface of the gate; The source ohmic contact covers the device surface. Among them, the ohmic contact and Schottky contact serve as reverse conduction mechanisms at the same time. During reverse freewheeling, the ohmic contact part of the device source is first turned on at a low voltage, and then the Schottky diode is turned on, achieving a lower reverse turn-on voltage for the device; in the blocking state, the ohmic contact source is pinched off by the Schottky barrier, making the device have a lower reverse leakage current.

2. The SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 1, It is characterized in that The source is a high work function metal, P + Polysilicon layer.

3. The SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 1, It is characterized in that The gate is N + Polysilicon layer.

4. The SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 1, It is characterized in that The doping concentration of the P-type buried layer is 1e18 / cm 3 Magnitude.

5. A method for preparing an SBD-integrated silicon carbide MOSFET with improved reverse freewheeling capability. It is characterized in that The following steps are involved: epitaxially growing an N-type drift layer and an N-type carrier storage layer on a silicon carbide substrate; Then, two photolithography and corresponding ion implantation are performed to form alternating N-type carrier storage layers on the upper part of the N-type carrier storage layer. + Area, P + area; Finally, N + Area and P + A P-type base region is formed in the N-type carrier storage layer below the region; Forming deep trenches distributed at intervals, with the bottom of the trenches located in the N-type carrier storage layer; Depositing a continuously distributed oxide layer, etching back the oxide layer, removing the oxide layer at the bottom of the trench, and forming a sidewall and source ion implantation barrier layer; Ion implantation forms a P-type buried layer at the bottom of the trench; Remove all oxide layers and activate all implanted ions by high temperature annealing; In the central + The deep trenches on both sides of the region form the source, and the Schottky contact barrier with the N-type carrier storage layer is realized on the sidewall; forming a gate oxide layer on the sidewalls and bottom of the outermost deep trench; forming a gate electrode so as to cover the gate oxide layer and completely fill the outermost deep trench; Deposit the passivation layer, and photolithography and etching to define the source metal contact area, leaving only the passivation layer on the gate surface on both sides; Form a source ohmic contact to cover the device surface, then perform chemical mechanical polishing. Among them, the ohmic contact and Schottky contact serve as reverse conduction mechanisms at the same time. During reverse freewheeling, the ohmic contact part of the device source is first turned on at a low voltage, and then the Schottky diode is turned on, achieving a lower reverse turn-on voltage for the device; in the blocking state, the ohmic contact source is pinched off by the Schottky barrier, making the device have a lower reverse leakage current.

6. The method for preparing an SBD-integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 5, It is characterized in that The source is a high work function metal, P + Polysilicon layer.

7. The method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 5, It is characterized in that The gate is N + Polysilicon layer.

8. The method for preparing an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 5, It is characterized in that The doping concentration of the P-type buried layer is 1e18 / cm 3 Magnitude.

Images