A constant power loss fast output capacitor discharge circuit and method

Abstract

The present invention relates to the technical field of discharge circuit design, and specifically discloses a constant power loss fast output capacitor discharge circuit and method, wherein the discharge circuit is electrically connected to a discharge NMOS tube M1 and a DCDC converter output capacitor, the discharge NMOS tube drain and one end of the output capacitor are electrically connected to the DCDC converter output voltage, and the discharge NMOS tube source and the other end of the output capacitor are electrically connected to the ground, including: an output voltage conversion unit, used to convert the DCDC converter output voltage into a control current; a gate-source voltage control circuit, used to control the gate-source voltage of the discharge NMOS tube based on the control current, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant. The present invention uses the control current generated by the output voltage conversion unit to control the gate-source voltage of the discharge NMOS tube, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant.

Description

Technical Field

[0001] The present invention relates to the technical field of discharge circuit design, and in particular to a constant power loss fast output capacitor discharge circuit and method. Background Art

[0002] Figure 1 It is a commonly used fast output discharge circuit, V O is the output voltage of the DCDC converter, C O is the output capacitor of the DCDC converter. When the DCDC converter is in shutdown mode, the SHDN signal becomes high, turning on the on-chip discharge NMOS tube M1 and storing it in the output capacitor C O The charge on the capacitor is quickly released to the ground through the discharge NMOS tube M1, so that the output voltage V O When the DCDC converter is in shutdown mode, it is 0 volts. For this commonly used fast output discharge circuit, the gate-source voltage of the discharge NMOS tube M1 is a constant Vcc, which is the internal power supply voltage of the chip, such as Figure 2 As shown in Figure (a), the drain-source current of the discharge NMOS tube M1 is a constant I dsat , is the saturation current of the discharge NMOS tube M1, such as Figure 2 As shown in Figure (b), the current when the discharge NMOS tube M1 is turned on is I = I dsat , at this time, the power loss on the discharge NMOS tube M1 is Pm1=I dsat * V O ,like Figure 2 As shown in Figure (c), the power loss is related to the DCDC converter output voltage V O When the DCDC converter output voltage V O When the voltage is greater than 5V or higher, the power loss in the on-chip discharge NMOS tube M1 is too large, causing the on-chip discharge NMOS tube M1 to heat up severely and even be damaged.

[0003] Based on this technical background, the present invention studies a constant power loss fast output capacitor discharge circuit and method. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes a constant power loss fast output capacitor discharge circuit and method. The discharge circuit uses the control current generated by the output voltage conversion unit to control the gate-source voltage of the discharge NMOS tube, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant and is not strongly related to the value of the DCDC converter output voltage, thereby limiting the heat generated by the discharge NMOS tube and protecting the chip from damage when the output capacitor is quickly discharged.

[0005] In order to achieve the above-mentioned object, the first aspect of the present invention provides a constant power loss fast output capacitor discharge circuit, wherein the discharge circuit is electrically connected to a discharge NMOS tube and a DCDC converter output capacitor, wherein the discharge NMOS tube drain and one end of the output capacitor are electrically connected to the DCDC converter output voltage, and the discharge NMOS tube source and the other end of the output capacitor are electrically connected to the ground, comprising:

[0006] An output voltage conversion unit, used to convert the output voltage of the DCDC converter into a control current;

[0007] The gate-source voltage control circuit is used to control the gate-source voltage of the discharge NMOS tube based on the control current, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant and is not strongly related to the value of the output voltage of the DCDC converter.

[0008] A second aspect of the present invention provides a method for fast output capacitor discharge with constant power loss in the above-mentioned discharge circuit, comprising:

[0009] The output voltage of the DCDC converter is converted into a control current by using an output voltage conversion unit;

[0010] Based on the control current, the gate-source voltage of the discharge NMOS tube is controlled by a gate-source voltage control circuit, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant and is not strongly related to the value of the output voltage of the DCDC converter.

[0011] The beneficial effects of the present invention include:

[0012] The constant power loss fast output capacitor discharge circuit proposed by the present invention uses the control current generated by the output voltage conversion unit to control the gate-source voltage of the discharge NMOS tube, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant and is not strongly related to the value of the DCDC converter output voltage, thereby limiting the heat generated by the discharge NMOS tube and protecting the chip from damage when the output capacitor is quickly discharged.

[0013] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0015] Figure 1It is a structural schematic diagram of an existing fast output discharge circuit.

[0016] Figure 2 The figure is a schematic diagram of the output waveform of the discharge NMOS tube M1 in the existing fast output discharge circuit.

[0017] Figure 3 It is a structural schematic diagram of a specific implementation mode of the constant power loss fast output capacitor discharge circuit proposed by the present invention.

[0018] Figure 4 This is a schematic diagram of the output waveform of the discharge NMOS tube M1 in a specific implementation of the constant power loss fast output capacitor discharge circuit proposed by the present invention.

[0019] Description of reference numerals:

[0020] M1-discharge NMOS tube, M2-control PMOS tube, M3-control NMOS tube, M4-third conversion NMOS tube, M5-first conversion NMOS tube, M6-second conversion NMOS tube, R1-control resistor, R2-conversion resistor, Co-DCDC converter output capacitor, INV1-first inverter, INV2-second inverter, Vo-DCDC converter output voltage, Vcc-power supply, SHDN-shutdown signal. DETAILED DESCRIPTION

[0021] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0022] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0023] The present invention provides a constant power loss fast output capacitor discharge circuit, the discharge circuit is electrically connected to a discharge NMOS tube M1 and a DCDC converter output capacitor Co, the discharge NMOS tube M1 drain and one end of the output capacitor Co are electrically connected to the DCDC converter output voltage Vo, the discharge NMOS tube M1 source and the other end of the output capacitor Co are electrically connected to the ground, such as Figure 3 As shown, including:

[0024] An output voltage conversion unit, used to convert the DCDC converter output voltage Vo into a control current;

[0025] The gate-source voltage control circuit is used to control the gate-source voltage of the discharge NMOS tube M1 based on the control current, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 remains basically constant and is not strongly related to the value of the DCDC converter output voltage Vo.

[0026] In the present invention, the gate-source voltage of the discharge NMOS tube M1 is controlled by utilizing the control current generated by the output voltage conversion unit, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 remains substantially constant and is not strongly related to the value of the output voltage Vo of the DCDC converter, thereby limiting the heat generated by the discharge NMOS tube M1 and protecting the chip from damage when the output capacitor Co is rapidly discharged.

[0027] According to the present invention, the gate-source voltage control circuit comprises:

[0028] Control the PMOS tube M2, with the source being electrically connected to the power source Vcc;

[0029] Control NMOS tube M3, the source is electrically connected to the ground;

[0030] A control resistor R1, one end of which is electrically connected to the drain of the control PMOS tube M2, and the other end of which is electrically connected to the drain of the control NMOS tube M3;

[0031] A first inverter INV1, an input end of which is electrically connected to a shutdown signal SHDN, and an output end of which is electrically connected to a gate of a control PMOS tube M2 and a gate of a control NMOS tube M3;

[0032] The second inverter INV2 has an input terminal electrically connected to the output terminal of the first inverter INV1.

[0033] According to the present invention, the output voltage conversion unit comprises:

[0034] The first conversion NMOS tube M5 has a gate electrically connected to its own drain;

[0035] A second conversion NMOS transistor M6, whose gate is electrically connected to the output terminal of the second inverter INV2, whose drain is electrically connected to the source of the first conversion NMOS transistor M5, and whose source is electrically connected to the ground;

[0036] The third conversion NMOS tube M4 has a gate electrically connected to the gate of the first conversion NMOS tube M5, a drain electrically connected to the drain of the control NMOS tube M3 and the gate of the discharge NMOS tube M1, and a source electrically connected to the ground;

[0037] The conversion resistor R2 has one end electrically connected to the DCDC converter output voltage Vo, and the other end electrically connected to the drain of the first conversion NMOS tube M5.

[0038] According to the present invention, when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 is calculated as follows:

[0039] ;

[0040] in, is the power loss of the discharge NMOS tube, β represents the amplification factor of the discharge NMOS tube, which is related to the process parameters and device size, V O is the output voltage of the DCDC converter, K is the proportionality coefficient, V k To define voltage.

[0041] According to the present invention, the calculation formula of the proportionality coefficient is:

[0042] ;

[0043] Among them, R1 is the control resistor and R2 is the conversion resistor;

[0044] The calculation formula for the defined voltage shown is:

[0045] ;

[0046] Among them, V cc is the power supply voltage, V gs5 is the gate-source voltage of the first conversion NMOS tube, V th is the threshold voltage of the discharge NMOS tube;

[0047] The calculation formula of the power loss of the discharge NMOS tube M1 is obtained by simplifying the complete formula;

[0048] The complete formula is:

[0049] ;

[0050] in, is the source-drain current of the discharge NMOS tube.

[0051] Preferably, the calculation formula of the source-drain current of the discharge NMOS tube M1 is:

[0052] ;

[0053] The calculation formula of the source-drain current of the discharge NMOS tube M1 is obtained by substituting the calculation formula of the gate-source voltage of the discharge NMOS tube M1 into the basic calculation formula of the source-drain current of the discharge NMOS tube M1;

[0054] The calculation formula of the gate-source voltage of the discharge NMOS tube M1 is:

[0055] ;

[0056] The basic calculation formula for the source-drain current of the discharge NMOS tube M1 is:

[0057] .

[0058] According to the present invention, the parameters in the calculation formula of the gate-source voltage of the discharge NMOS tube M1 are is the source-drain current of the first conversion NMOS tube, and its expression is:

[0059] ;

[0060] Among them, I ds5 ,I ds4 They are the source-drain current of the first conversion NMOS tube M5 and the source-drain current of the third conversion NMOS tube M4 respectively. Since the first conversion NMOS tube M5 and the third conversion NMOS tube M4 form a set of current mirrors, the two currents are equal.

[0061] According to the present invention, when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 remains substantially constant and is not strongly related to the output voltage Vo of the DCDC converter. After the calculation formula of the power loss of the discharge NMOS tube M1 is derived to obtain the derived formula, the derived formula is analyzed to obtain:

[0062] The derivative formula is:

[0063] ;

[0064] The result of analyzing the derivative formula is:

[0065] when When , the power loss in the discharge NMOS tube M1 increases monotonically with the output voltage;

[0066] when When , the power loss in the discharge NMOS tube M1 decreases monotonically with the output voltage;

[0067] By selecting the values ​​of the conversion resistor R2 and the control resistor R1, It is at two-thirds of the maximum value of the DCDC converter output voltage Vo. At this time, the power loss of the discharge NMOS tube M1 is not strongly related to the value of the DCDC converter output voltage Vo, which limits the heat generated by the discharge NMOS tube M1 and protects the chip from being damaged when the output capacitor Co is discharged quickly.

[0068] The present invention also provides a constant power fast output capacitor Co discharge method performed in the above-mentioned discharge circuit, comprising:

[0069] The output voltage of the DCDC converter is converted into a control current by using an output voltage conversion unit;

[0070] Based on the control current, the gate-source voltage of the discharge NMOS tube M1 is controlled by using the gate-source voltage control circuit, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 remains basically constant and is not strongly related to the value of the DCDC converter output voltage Vo.

[0071] According to the present invention, when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 remains substantially constant and is not strongly related to the output voltage Vo of the DCDC converter. After the calculation formula of the power loss of the discharge NMOS tube M1 is derived to obtain the derived formula, the derived formula is analyzed to obtain:

[0072] The result of analyzing the derivative formula is:

[0073] By selecting the values ​​of the conversion resistor R2 and the control resistor R1, It is at two-thirds of the maximum value of the DCDC converter output voltage Vo. At this time, the power loss of the discharge NMOS tube M1 is not strongly related to the value of the DCDC converter output voltage Vo, which limits the heat generated by the discharge NMOS tube M1 and protects the chip from being damaged when the output capacitor Co is discharged quickly.

[0074] The present invention will be described in more detail below through specific embodiments. Example

[0075] like Figure 3 As shown, this embodiment provides a constant power loss fast output capacitor discharge circuit, wherein the discharge circuit is electrically connected to the discharge NMOS tube M1 and the DCDC converter output capacitor Co, the discharge NMOS tube M1 drain and one end of the output capacitor Co are electrically connected to the DCDC converter output voltage Vo, and the discharge NMOS tube M1 source and the other end of the output capacitor Co are electrically connected to the ground, including:

[0076] An output voltage conversion unit, used to convert the DCDC converter output voltage Vo into a control current;

[0077] The gate-source voltage control circuit is used to control the gate-source voltage of the discharge NMOS tube M1 based on the control current, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube M1 remains substantially constant and is not strongly related to the value of the DCDC converter output voltage Vo;

[0078] In this embodiment, the gate-source voltage control circuit includes:

[0079] Control the PMOS tube M2, with the source being electrically connected to the power source Vcc;

[0080] Control NMOS tube M3, the source is electrically connected to the ground;

[0081] A control resistor R1, one end of which is electrically connected to the drain of the control PMOS tube M2, and the other end of which is electrically connected to the drain of the control NMOS tube M3;

[0082] A first inverter INV1, an input end of which is electrically connected to a shutdown signal SHDN, and an output end of which is electrically connected to a gate of a control PMOS tube M2 and a gate of a control NMOS tube M3;

[0083] A second inverter INV2, an input end of which is electrically connected to an output end of the first inverter INV1;

[0084] In this embodiment, the output voltage conversion unit includes:

[0085] The first conversion NMOS tube M5 has a gate electrically connected to its own drain;

[0086] A second conversion NMOS transistor M6, whose gate is electrically connected to the output terminal of the second inverter INV2, whose drain is electrically connected to the source of the first conversion NMOS transistor M5, and whose source is electrically connected to the ground;

[0087] The third conversion NMOS tube M4 has a gate electrically connected to the gate of the first conversion NMOS tube M5, a drain electrically connected to the drain of the control NMOS tube M3 and the gate of the discharge NMOS tube M1, and a source electrically connected to the ground;

[0088] The conversion resistor R2 has one end electrically connected to the DCDC converter output voltage Vo, and the other end electrically connected to the drain of the first conversion NMOS tube M5.

[0089] In this embodiment, V O is the output voltage of the DCDC converter, C O is the output capacitor of the DCDC converter; when the DCDC converter is in shutdown mode, the shutdown signal SHDN becomes high level, then the second conversion NMOS tube M6 is turned on, and the current in the first conversion NMOS tube M5 is:

[0090] ;

[0091] The third conversion NMOS tube M4 and the first conversion NMOS tube M5 form a set of current mirrors, and the currents in the two are equal, so that:

[0092] ;

[0093] Vcc is the internal power supply voltage of the chip, which is a constant voltage. The current of the third conversion NMOS tube M4 flows through the control resistor R1 to generate a voltage drop, which controls the gate-source voltage of the discharge NMOS tube M1, and obtains:

[0094] (1);

[0095] The discharge NMOS tube M1 works in the saturation region, and the current flowing through it is:

[0096] ;

[0097] Where β represents the gain of the NMOS tube and is related to the process parameters and device size. Substituting (1) into the above formula yields:

[0098] (2);

[0099] The drain-source voltage of the discharge NMOS tube M1 is Vo, and the power loss of the discharge NMOS tube M1 can be obtained as:

[0100] (3);

[0101] definition:

[0102] ;

[0103] Then, the power loss expression (3) of the discharge NMOS tube M1 can be simplified to:

[0104] (4);

[0105] In expression (4), taking the derivative of Vo, we get:

[0106] ;

[0107] From this we can obtain that when When , the power loss in the discharge NMOS tube M1 increases monotonically with the output voltage;

[0108] when When , the power loss in the discharge NMOS tube M1 decreases monotonically with the output voltage;

[0109] By selecting the values ​​of the conversion resistor R2 and the control resistor R1, It is at two-thirds of the maximum value of the DCDC converter output voltage Vo. At this time, the power loss of the discharge NMOS tube M1 is not strongly related to the value of the DCDC converter output voltage Vo, which limits the heat generated by the discharge NMOS tube M1 and protects the chip from being damaged when the output capacitor Co is discharged quickly.

[0110] The relationship between the gate-source voltage of the discharge NMOS tube M1 and the output voltage Vo of the DCDC converter follows expression (1). The relationship between the two is as follows: Figure 4 As shown in the curve of (a); the relationship between the drain-source current of the discharge NMOS tube M1 and the output voltage Vo of the DCDC converter follows expression (2), and the relationship between the two is as follows Figure 4 As shown in the curve of (b); the relationship between the power loss Pm1 of the discharge NMOS tube M1 and the output voltage Vo of the DCDC converter follows the expression (3). Figure 4 As shown in the curve in Figure (c).

[0111] The constant power loss fast output capacitor discharge circuit proposed in the embodiment of the present invention uses the control current generated by the output voltage conversion unit to control the gate-source voltage of the discharge NMOS tube, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant and is not strongly related to the value of the DCDC converter output voltage, thereby limiting the heat generated by the discharge NMOS tube and protecting the chip from damage when the output capacitor is discharged quickly.

[0112] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A constant power loss fast output capacitor discharge circuit, the discharge circuit comprising a discharge NMOS tube and a DCDC converter output capacitor, the discharge NMOS tube drain and one end of the output capacitor are electrically connected to the DCDC converter output voltage, the discharge NMOS tube source and the other end of the output capacitor are electrically connected to the ground, characterized in that: include: An output voltage conversion unit, used to convert the output voltage of the DCDC converter into a control current, the output voltage conversion unit comprising a conversion resistor connected to the output voltage of the DCDC converter; A gate-source voltage control circuit, comprising a control resistor connected to the gate of the discharge NMOS tube, the gate-source voltage control circuit being used to control the gate-source voltage of the discharge NMOS tube based on the control current, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains substantially constant and is not strongly correlated with the value of the output voltage of the DCDC converter; When the DCDC converter is turned off, the power loss of the discharge NMOS tube is calculated as follows: ； in, is the power loss of the discharge NMOS tube, β represents the amplification factor of the discharge NMOS tube, which is related to the process parameters and device size, V O is the output voltage of the DCDC converter, K is the proportionality coefficient, V k To define voltage; The calculation formula of the proportionality coefficient is: ； Among them, R1 is the control resistor and R2 is the conversion resistor; When the DCDC converter is turned off, the power loss of the discharge NMOS tube remains substantially constant and is not strongly correlated with the output voltage value of the DCDC converter. By deriving the calculation formula of the power loss of the discharge NMOS tube, the derived formula is: ； The result obtained by analyzing the derivation formula is: when When , the power loss in the discharge NMOS tube increases monotonically with the output voltage; when When , the power loss in the discharge NMOS tube decreases monotonically with the output voltage; By choosing the values ​​of the switching resistor and the control resistor, At two-thirds of the maximum output voltage, the power loss of the discharge NMOS tube is not strongly correlated with the value of the output voltage of the DCDC converter.

2. The discharge circuit according to claim 1, characterized in that: The gate-source voltage control circuit comprises: Control the PMOS tube, the source is electrically connected to the power supply; Control the NMOS tube, the source is electrically connected to the ground; A control resistor, one end of which is electrically connected to the drain of the control PMOS tube, and the other end of which is electrically connected to the drain of the control NMOS tube; A first inverter, an input end of which is electrically connected to the shutdown signal, and an output end of which is electrically connected to the control PMOS tube gate and the control NMOS tube gate at the same time; The second inverter has an input terminal electrically connected to the output terminal of the first inverter.

3. The discharge circuit according to claim 2, characterized in that: The output voltage conversion unit comprises: A first conversion NMOS tube, the gate of which is electrically connected to its own drain; A second conversion NMOS transistor, whose gate is electrically connected to the output terminal of the second inverter, whose drain is electrically connected to the source of the first conversion NMOS transistor, and whose source is electrically connected to the ground; A third conversion NMOS tube, whose gate is electrically connected to the gate of the first conversion NMOS tube, whose drain is electrically connected to the drain of the control NMOS tube and the gate of the discharge NMOS tube, and whose source is electrically connected to the ground; A conversion resistor, one end of which is electrically connected to the output voltage of the DCDC converter, and the other end of which is electrically connected to the drain of the first conversion NMOS tube.

4. The discharge circuit according to claim 3, characterized in that: The calculation formula for the defined voltage shown is: ； in, is the power supply voltage, is the gate-source voltage of the first conversion NMOS tube, is the threshold voltage of the discharge NMOS tube; The calculation formula of the power loss of the discharge NMOS tube is obtained by simplifying the complete formula; The complete formula is: ； in, is the source-drain current of the discharge NMOS tube.

5. The discharge circuit according to claim 4, characterized in that: The calculation formula of the source-drain current of the discharge NMOS tube is: ； The calculation formula of the source-drain current of the discharge NMOS tube is obtained by substituting the calculation formula of the gate-source voltage of the discharge NMOS tube into the basic calculation formula of the source-drain current of the discharge NMOS tube; The calculation formula of the gate-source voltage of the discharge NMOS tube is: ； The basic calculation formula for the source-drain current of the discharge NMOS tube is: 。 6. The discharge circuit according to claim 5, characterized in that: The parameters in the calculation formula of the gate-source voltage of the discharge NMOS tube are is the first conversion NMOS tube source-drain current, and its expression is: ； in, , They are the source-drain current of the first conversion NMOS tube and the source-drain current of the third conversion NMOS tube respectively. Since the first conversion NMOS tube and the third conversion NMOS tube form a group of current mirrors, the two currents are equal.

7. A method for fast output capacitor discharge with constant power loss in the discharge circuit according to any one of claims 1 to 6, characterized in that: include: The output voltage of the DCDC converter is converted into a control current by using an output voltage conversion unit; Based on the control current, the gate-source voltage of the discharge NMOS tube is controlled by a gate-source voltage control circuit, so that when the DCDC converter is turned off, the power loss of the discharge NMOS tube remains basically constant and is not strongly related to the value of the output voltage of the DCDC converter.

8. The discharge method according to claim 7, characterized in that: When the DCDC converter is turned off, the power loss of the discharge NMOS tube remains substantially constant and is not strongly correlated with the output voltage value of the DCDC converter. After the calculation formula of the power loss of the discharge NMOS tube is derived to obtain a derivative formula, the derivative formula is analyzed to obtain; By choosing the values ​​of the switching resistor and the control resistor, At two-thirds of the maximum output voltage, the power loss of the discharge NMOS tube is not strongly correlated with the value of the output voltage of the DCDC converter.

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