Broadband Doherty power amplification circuit based on coupler balun active load modulation network

Abstract

The invention provides a broadband Doherty power amplification circuit based on a coupler balun active load modulation network, which belongs to the field of radio frequency integrated circuits and comprises an input matching network, a self-adaptive biasing circuit, a main power amplifier, an auxiliary power amplifier and an output matching network. And the output matching network consists of two pairs of differential couplers and a section of 30-degree transmission line, so that the Doherty power amplifier has a broadband active load modulation function. Under a 65-nanometer CMOS (complementary metal-oxide-semiconductor transistor) process, in a working frequency range of 40% of relative bandwidth, the power back-off characteristic is good, and the back-off efficiency is high in a broadband range.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency integrated circuits, and in particular relates to a broadband Doherty power amplifier circuit based on a coupler balun active load modulation network. Background Art

[0002] Millimeter-wave (mm-Wave) spectrum is crucial for the development of fifth-generation (5G) wireless communication systems, but at the same time, it places more stringent requirements on power amplifiers in mm-wave communication systems. On the one hand, in order to support high data rate scenarios such as enhanced mobile broadband, future 5G systems will widely adopt complex modulation schemes such as high-order QAM, orthogonal frequency division multiplexing (OFDM), and carrier aggregation (CA). Due to the high peak-to-average power ratio (PAPR) of these signals, power amplifiers are usually operated at power back-off (PBO) of their peak output power. In order to achieve efficiency improvement of mm-wave PAs at the PBO level, recent research has focused on two classic architectures: Doherty and Chireix (also known as Outphasing). Outphasing PA requires Chireix compensation reactance to achieve PBO efficiency improvement, which limits the bandwidth of PA in practical applications. At the same time, the output matching circuit of the traditional Doherty power amplifier consists of a section of λ / 4 transmission line. Since the λ / 4 transmission line is a single-frequency matching point and has a natural narrowband characteristic, the traditional Doherty power amplifier also has a narrow bandwidth characteristic.

[0003] On the other hand, 5G wireless networks are built using different frequency range 2 (FR2) bands in different countries / regions around the world. Broadband / multi-band millimeter wave systems need to support 5G cross-country / regional roaming. Therefore, broadband power amplifiers are essential in millimeter wave 5G front-end modules (FEMs) and systems.

[0004] Therefore, in millimeter-wave front-end wireless communication systems, Doherty power amplifiers with high back-off efficiency and broadband are of great research significance. Summary of the invention

[0005] The purpose of the present invention is to provide a broadband millimeter-wave Doherty power amplifier circuit based on a coupler balun network proposed in this article, which can improve the broadband power back-off efficiency and load modulation under 65 nanometer CMOS process.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] A broadband Doherty power amplifier circuit based on a coupler balun active load modulation network is characterized in that it includes: an input matching network, an adaptive bias circuit, a main power amplifier, an auxiliary power amplifier and an output matching network; wherein the input matching network converts a radio frequency signal into four signals with a phase difference of 90° and equal amplitude; the adaptive bias circuit controls the driving stage and output stage gate bias of the auxiliary power amplifier; the main power amplifier and the auxiliary power amplifier are responsible for power amplification; and the output matching network is responsible for power synthesis, impedance matching and broadband active load modulation.

[0008] Furthermore, the input matching network, wherein the input matching network includes a single-ended to double-ended balun and an orthogonal coupler, the RF signal enters the single-ended to double-ended balun and is converted into a differential signal with a phase difference of 180°, and then enters the orthogonal coupler, the orthogonal coupler converts the differential signal into four signals with a phase difference of 90° and equal amplitude, which are respectively injected into the main power amplifier and the auxiliary power amplifier paths, wherein the differential signal injected into the auxiliary power amplifier path leads the differential signal injected into the main power amplifier path by 90° in phase.

[0009] Further, the adaptive bias circuit, wherein the adaptive bias circuit includes an envelope detector and two common source amplifier circuits. The input stage of the adaptive bias circuit is connected to the RF input port, injected into the envelope detector, the input end is connected in series with the capacitor C1, the resistor R1 is connected in parallel to the DC voltage, and then connected to the gate of the NMOS transistor M1, the source of the transistor M1 is connected to the ground, the high-frequency filter circuit is connected in parallel by the resistor R2 and the capacitor C2, one end is connected to the drain of the transistor M1, and the other end is connected to the voltage, the output voltage of the envelope detector circuit is drawn from the drain of the transistor M1, and connected to the gates of the two common source amplifier circuits transistors M2 and M3 respectively, the source of the transistor M2 is connected to the ground, the drain is connected to the resistor R3, the other end of R3 is connected to the voltage, the drain output signal of the transistor M2 is connected in parallel with the capacitor C3 to the ground, and then connected to the auxiliary power amplifier driver stage bias circuit, the source of the transistor M3 is connected to the ground, the drain is connected to the resistor R4, the other end of R4 is connected to the voltage, the drain output signal of the transistor M3 is connected in parallel with the capacitor C4 to the ground, and then connected to the auxiliary power amplifier output stage bias circuit.

[0010] Furthermore, the main power amplifier includes an input matching transformer, a driving stage power amplifier circuit, an inter-stage matching transformer and an output stage power amplifier circuit. The differential signal injected into the main power amplifier path lags 90° relative to the differential signal injected into the auxiliary power amplifier path. The differential signals are respectively connected to the input ports of the input matching transformer. After impedance matching, the output ports are connected to the two input ports of the driving stage power amplifier circuit. After power amplification by the driving stage power amplifier, the output ports are output. The differential output ports are connected to the input ports of the inter-stage matching transformer. After the impedance change of the inter-stage matching transformer, the output ports are connected to the input ports of the output stage power amplifier circuit. The signals are output after power amplification by the output stage power amplifier circuit.

[0011] Furthermore, the auxiliary power amplifier includes an input matching transformer, a driving stage power amplifier circuit, an inter-stage matching transformer and an output stage power amplifier circuit. The differential signal injected into the auxiliary power amplifier path leads the differential signal injected into the main power amplifier path by 90°. The differential signals are respectively connected to the input ports of the input matching transformer. After impedance matching, the output ports are connected to the two input ports of the driving stage power amplifier circuit. After power amplification by the driving stage power amplifier, the output ports are output. The differential output ports are connected to the input ports of the inter-stage matching transformer. After the impedance change of the inter-stage matching transformer, the output ports are connected to the input ports of the output stage power amplifier circuit. The signals are output after power amplification by the output stage power amplifier circuit.

[0012] Furthermore, the driving-stage power amplifier circuit adopts a differential structure as a whole, wherein M1 and M2 are common-source NMOS transistors, the positive electrode of the input signal is connected to the gate of transistor M1, and then connected to one end of capacitor C2, the other end of capacitor C2 is connected to the drain of transistor M2, the negative electrode of the input signal is connected to the gate of transistor M2, and then connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of transistor M1, the drain of transistor M1 is the output positive electrode, and the drain of transistor M2 is the output negative electrode.

[0013] Furthermore, the output-stage power amplifier circuit adopts a differential structure as a whole, wherein M1 and M2 are common-source NMOS transistors, M3 and M4 are common-gate NMOS transistors, the positive electrode of the input signal is connected to the gate of transistor M1, and then connected to one end of capacitor C2, the other end of capacitor C2 is connected to the drain of transistor M2, the drain of transistor M1 is connected to the source of transistor M3, the gate of transistor M3 and M4 are commonly connected to the bias voltage, the drain of transistor M3 corresponds to the output positive electrode, the negative electrode of the input signal is connected to the gate of transistor M2, and then connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of transistor M1, the drain of transistor M2 is connected to the source of transistor M4, the gate of transistor M4 and M3 are commonly connected to the bias voltage, and the drain of transistor M4 corresponds to the output negative electrode.

[0014] Further, the output matching network includes a main balun, an auxiliary balun and a 30° transmission line, the positive input end of the main balun is connected to the positive output port of the main power amplifier circuit, and then connected to the 30° transmission line 1, the other end of the 30° transmission line 1 is connected to the power supply voltage, one end of the transmission line 2 is connected to the transmission line 9, and the other end is connected to the transmission line 3, the transmission line 1 and the transmission line 2 form a coupling line, the negative input end of the main balun is connected to the negative output port of the main power amplifier circuit, and then connected to the 30° transmission line 4, the other end of the 30° transmission line 4 is connected to the power supply voltage, one end of the transmission line 3 is connected to the output equivalent transmission line, and the other end is connected to the transmission line 2, the transmission line 3 and the transmission line 4 form a coupling line, and the auxiliary balun input The positive input end is connected to the positive output port of the auxiliary power amplifier circuit, and then connected to the 30° transmission line 5, the other end of the 30° transmission line 5 is connected to the power supply voltage, one end of the transmission line 6 is connected to the ground, and the other end is connected to the transmission line 7, the transmission line 5 and the transmission line 6 form a coupling line, the auxiliary balun input negative end is connected to the negative output port of the auxiliary power amplifier circuit, and then connected to the 30° transmission line 8, the other end of the 30° transmission line 8 is connected to the power supply voltage, one end of the transmission line 7 is connected to the transmission line 9, and the other end is connected to the transmission line 6, the transmission line 7 and the transmission line 8 form a coupling line, one end of the transmission line 9 is connected to the transmission line 7, and the other end is connected to the transmission line 2, and the output equivalent transmission line serves as the output port of the entire output matching network.

[0015] The working principle is as follows: the RF single-ended input signal is converted into differential orthogonal signals with phase differences of 0° and 180°, 90° and 270° through a single-ended to differential transformer and an orthogonal coupler. Then, the 0° and 180° signals are fed into the auxiliary power amplifier path, and the 90° and 270° signals are fed into the main power amplifier path for power amplification respectively. The two paths are composed of the same input matching transformer, driving stage power amplifier circuit, inter-stage matching transformer and output stage power amplifier circuit. The output matching network adopts an active load modulation network based on a coupler balun, including a main balun, an auxiliary balun and a 30° transmission line. It has the functions of broadband active load modulation and power synthesis, and outputs when the signal is matched to a single-ended 50Ω. The bias voltage of the driving stage and the output stage of the auxiliary power amplifier is provided by an adaptive bias circuit. Finally, within the operating frequency range of 40% of the relative bandwidth, the present invention exhibits good power back-off characteristics and has high back-off efficiency within a broadband range.

[0016] The beneficial effects of the present invention are:

[0017] The present invention is different from the traditional Doherty power amplifier. The output matching circuit of the traditional Doherty power amplifier is composed of a section of λ / 4 transmission line. Since the λ / 4 transmission line is a single frequency point matching, it naturally has a narrowband characteristic, so the traditional Doherty power amplifier also has a narrow bandwidth characteristic. The output matching network proposed in the invention adopts a series structure. The parallel Doherty power amplifier converts the voltage into current through an impedance converter. This process depends on the frequency characteristics of the impedance converter. The series Doherty power amplifier directly synthesizes the current without frequency-related impedance conversion. The present invention utilizes the inherent broadband characteristics of the series structure to achieve overall broadband performance. The output matching network adopts a differential structure, which is composed of two 30° differential coupling lines, a 30° compensation transmission line and an output equivalent transmission line. The coupling line transformer of the main power amplifier and the coupling line transformer of the auxiliary power amplifier jointly compensate for the 90° phase delay of the main power amplifier relative to the auxiliary power amplifier. Since the electrical length of the coupling line and the transmission line exhibits inductive characteristics when it is less than 90°, they can be used to offset the parasitic capacitance of the power amplifier output stage to achieve impedance matching. At the same time, the matching network does not require an additional impedance inverter because the coupler itself has the characteristics of an impedance inverter and can achieve impedance transformation. This overcomes the narrowband limitation of the traditional Doherty power amplifier due to the use of a quarter-wavelength transmission line. The proposed [Z] matrix network is shown in the figure below:

[0018]

[0019] The impedance Z1 on the main power amplifier side can be solved as follows:

[0020]

[0021] Finally, within the operating frequency range of 40% of the relative bandwidth, the present invention exhibits good power back-off characteristics and has high back-off efficiency within a wide bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of a broadband millimeter-wave series Doherty power amplifier based on a coupler balun network in the present invention.

[0023] Figure 2 This is a circuit schematic diagram of a driving-stage power amplifier according to Embodiment 1 of the present invention.

[0024] Figure 3 This is a circuit schematic diagram of the output stage power amplifier of Example 1 of the present invention.

[0025] Figure 4 It is a schematic diagram of the structure of the active load modulation network based on the coupler balun in the present invention.

[0026] Figure 5 It is a schematic diagram of the structure of the adaptive bias circuit in the present invention.

[0027] Figure 6 The impedance parameter Z21 of the active load modulation network based on the coupler balun in Example 1 of the present invention varies with frequency.

[0028] Figure 7 The output voltage of the adaptive bias circuit in Example 1 of the present invention varies with input power.

[0029] Figure 8 This is a comparison chart of the power back-off efficiency between the broadband millimeter-wave series Doherty power amplifier based on the coupler balun network in Example 1 of the present invention and the traditional Class-B power amplifier. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in conjunction with the following specific embodiments and with reference to the accompanying drawings.

[0031] The following non-limiting embodiments may enable a person skilled in the art to more fully understand the present invention, but are not intended to limit the present invention in any way.

[0032] Example 1

[0033] In this embodiment, the broadband millimeter wave Doherty power amplifier circuit based on the coupler balun network is shown in FIG. Figure 1 .

[0034] Working principle: The RF single-ended input signal is converted into differential orthogonal signals with phase differences of 0° and 180°, 90° and 270° through a single-ended to differential transformer and an orthogonal coupler. Then, the 0° and 180° signals are fed into the auxiliary power amplifier path, and the 90° and 270° signals are fed into the main power amplifier path for power amplification. These two paths are composed of the same input matching transformer, driver stage power amplifier circuit, interstage matching transformer and output stage power amplifier circuit. The circuit structure of the driver stage power amplifier circuit can be found in Figure 2 The overall structure adopts a differential structure, where M1 and M2 are common source NMOS transistors, the positive electrode of the input signal is connected to the gate of transistor M1, and then connected to one end of capacitor C2, the other end of capacitor C2 is connected to the drain of transistor M2, the negative electrode of the input signal is connected to the gate of transistor M2, and then connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of transistor M1, the drain of transistor M1 is the output positive electrode, and the drain of transistor M2 is the output negative electrode. See the output stage power amplifier circuit Figure 3, the overall structure adopts a differential structure, in which M1 and M2 are common-source NMOS transistors, M3 and M4 are common-gate NMOS transistors, the positive pole of the input signal is connected to the gate of transistor M1, and then connected to one end of capacitor C2, the other end of capacitor C2 is connected to the drain of transistor M2, the drain of transistor M1 is connected to the source of transistor M3, the gate of transistor M3 and M4 are connected to the bias voltage, the drain of transistor M3 corresponds to the positive output, the negative pole of the input signal is connected to the gate of transistor M2, and then connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of transistor M1, the drain of transistor M2 is connected to the source of transistor M4, the gate of transistor M4 and M3 are connected to the bias voltage, and the drain of transistor M4 corresponds to the negative output. See the output matching network Figure 4 , using an active load modulation network based on a coupler balun, including a main balun, an auxiliary balun and a 30° transmission line. It has the functions of broadband active load modulation and power synthesis, and outputs when the signal is matched to a single-ended 50Ω. Figure 6 The impedance parameter Z21 of the active load modulation network based on the coupler balun in Example 1 of the present invention varies with frequency. It can be seen that in the frequency range of 23 GHz to 42 GHz, the functions of broadband active load modulation and impedance matching are realized. The bias voltage of the driving stage and the output stage of the auxiliary power amplifier is provided by the adaptive bias circuit, see Figure 5 , wherein the adaptive bias circuit includes an envelope detector and two common source amplifier circuits. The input stage of the adaptive bias circuit is connected to the RF input port and injected into the envelope detector. The input end is connected in series with the capacitor C1, and the resistor R1 is connected in parallel to the DC voltage, and then connected to the gate of the NMOS transistor M1. The source of the transistor M1 is connected to the ground. The high-frequency filter circuit is connected in parallel with the resistor R2 and the capacitor C2, one end of which is connected to the drain of the transistor M1 and the other end is connected to the voltage. The output voltage of the envelope detector circuit is drawn from the drain of the transistor M1 and connected to the gates of the two common source amplifier circuits, the transistor M2 and the M3 respectively. The source of the transistor M2 is connected to the ground, the drain is connected to the resistor R3, and the other end of R3 is connected to the voltage. The output signal of the transistor M2 drain is connected in parallel with the capacitor C3 to the ground, and then connected to the auxiliary power amplifier driver stage bias circuit. The source of the transistor M3 is connected to the ground, the drain is connected to the resistor R4, and the other end of R4 is connected to the voltage. The output signal of the transistor M3 drain is connected in parallel with the capacitor C4 to the ground, and then connected to the auxiliary power amplifier output stage bias circuit. Figure 7 The output voltage of the adaptive bias circuit in Example 1 of the present invention changes with the input power. When the input power is 6 dB, the adaptive bias circuit starts to output voltage, and the auxiliary power amplifier gradually turns on, realizing the working characteristics of the Doherty power amplifier. Figure 8, simulation results were performed under 65nm CMOS process, and at an operating frequency of 29GHz, the power amplifier achieved a saturated power of 24.3dBm and a peak power added efficiency of 32.4%. The efficiency at 7.5dB power back-off is 24.5%. The simulated power added efficiency performance shows that compared with the traditional Class-B power amplifier with the same peak PAE at 1dB saturated power, the efficiency at 7.5dB power back-off is increased by 1.68 times. Compared with the traditional Class-B power amplifier, the present invention exhibits good power back-off characteristics. In the frequency range of 24GHz to 36GHz, the relative bandwidth reaches 40%, which achieves the advantage of bandwidth indicators compared with the traditional Doherty power amplifier. In summary, the broadband millimeter-wave Doherty power amplifier circuit based on the coupler balun network proposed in the present invention has high back-off efficiency in a broadband range, and realizes the high back-off efficiency characteristics of the Doherty power amplifier circuit under broadband.

Claims

1. A broadband Doherty power amplifier circuit based on a coupler balun active load modulation network, characterized in that: include: An input matching network, an adaptive bias circuit, a main power amplifier, an auxiliary power amplifier and an output matching network; wherein the input matching network converts the radio frequency signal into four signals with a phase difference of 90° and equal amplitude; the adaptive bias circuit controls the driving stage and output stage gate bias of the auxiliary power amplifier; the main power amplifier and the auxiliary power amplifier are responsible for power amplification; the output matching network is responsible for power synthesis, impedance matching and broadband active load modulation.

2. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 1, characterized in that: The input matching network described therein includes a single-ended to double-ended balun and an orthogonal coupler. The RF signal enters the single-ended to double-ended balun and is converted into a differential signal with a phase difference of 180°, and then enters the orthogonal coupler. The orthogonal coupler converts the differential signal into four signals with a phase difference of 90° and equal amplitude, which are respectively injected into the main power amplifier and auxiliary power amplifier paths, wherein the differential signal injected into the auxiliary power amplifier path leads the differential signal injected into the main power amplifier path by 90° in phase.

3. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 2, characterized in that: Among them, adaptive The bias circuit includes an envelope detector and two common source amplifier circuits. The input stage of the adaptive bias circuit is connected to the RF input port and injected into the envelope detector. The input end is connected in series with the capacitor C1, and the resistor R1 is connected in parallel to the DC voltage, and then connected to the gate of the NMOS transistor M1. The source of the transistor M1 is connected to the ground. The high-frequency filter circuit is connected in parallel with the resistor R2 and the capacitor C2, one end of which is connected to the drain of the transistor M1 and the other end is connected to the voltage. The output voltage of the envelope detector circuit is drawn from the drain of the transistor M1 and connected to the gates of the transistors M2 and M3 of the two common-source amplifier circuits respectively. The source of the transistor M2 is connected to the ground, and the drain is connected to the resistor R3, and the other end of R3 is connected to the voltage. The drain output signal of the transistor M2 is connected in parallel with the capacitor C3 to the ground, and then connected to the auxiliary power amplifier driving stage bias circuit. The source of the transistor M3 is connected to the ground, and the drain is connected to the resistor R4, and the other end of R4 is connected to the voltage. The drain output signal of the transistor M3 is connected in parallel with the capacitor C4 to the ground, and then connected to the auxiliary power amplifier output stage bias circuit.

4. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 3, characterized in that: The main power amplifier includes an input matching transformer, a driving stage power amplifier circuit, an inter-stage matching transformer and an output stage power amplifier circuit. The differential signal injected into the main power amplifier path lags behind the differential signal injected into the auxiliary power amplifier path by 90°. The differential signals are respectively connected to the input ports of the input matching transformer. After impedance matching, the output ports are connected to the two input ports of the driving stage power amplifier circuit. After power amplification by the driving stage power amplifier, the differential output port is connected to the input port of the inter-stage matching transformer. After the impedance change of the inter-stage matching transformer, the output port is connected to the input port of the output stage power amplifier circuit. The signal is output after power amplification by the output stage power amplifier circuit.

5. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 4, characterized in that: The auxiliary power amplifier includes an input matching transformer, a driving stage power amplifier circuit, an inter-stage matching transformer and an output stage power amplifier circuit. The differential signal injected into the auxiliary power amplifier path leads the differential signal injected into the main power amplifier path by 90°. The differential signals are respectively connected to the input ports of the input matching transformer. After impedance matching, the output ports are connected to the two input ports of the driving stage power amplifier circuit. After power amplification by the driving stage power amplifier, the differential output port is connected to the input port of the inter-stage matching transformer. After the impedance change of the inter-stage matching transformer, the output port is connected to the input port of the output stage power amplifier circuit. The signal is output after power amplification by the output stage power amplifier circuit.

6. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 5, characterized in that: The driving-stage power amplifier circuit adopts a differential structure as a whole, wherein M1 and M2 are common-source NMOS transistors, the positive electrode of the input signal is connected to the gate of the transistor M1, and then connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the drain of the transistor M2, the negative electrode of the input signal is connected to the gate of the transistor M2, and then connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the transistor M1, the drain of the transistor M1 is the output positive electrode, and the drain of the transistor M2 is the output negative electrode.

7. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 6, characterized in that: The output stage power amplifier circuit adopts a differential structure as a whole, wherein M1 and M2 are common source NMOS transistors, M3 and M4 are common gate NMOS transistors, the positive electrode of the input signal is connected to the gate of transistor M1, and then connected to one end of capacitor C2, the other end of capacitor C2 is connected to the drain of transistor M2, the drain of transistor M1 is connected to the source of transistor M3, the gate of transistor M3 and M4 are commonly connected to the bias voltage, the drain of transistor M3 corresponds to the output positive electrode, the negative electrode of the input signal is connected to the gate of transistor M2, and then connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of transistor M1, the drain of transistor M2 is connected to the source of transistor M4, the gate of transistor M4 and M3 are commonly connected to the bias voltage, and the drain of transistor M4 corresponds to the output negative electrode.

8. The broadband Doherty power amplifier circuit based on a coupler balun active load modulation network according to claim 7, characterized in that: The output matching network includes a main balun, an auxiliary balun and a 30° transmission line. The positive input end of the main balun is connected to the positive output port of the main power amplifier circuit, and then connected to the 30° transmission line 1. The other end of the 30° transmission line 1 is connected to the power supply voltage. One end of the transmission line 2 is connected to the transmission line 9, and the other end is connected to the transmission line 3. The transmission line 1 and the transmission line 2 form a coupling line. The negative input end of the main balun is connected to the negative output port of the main power amplifier circuit, and then connected to the 30° transmission line 4. The other end of the 30° transmission line 4 is connected to the power supply voltage. One end of the transmission line 3 is connected to the output equivalent transmission line, and the other end is connected to the transmission line 2. The transmission line 3 and the transmission line 4 form a coupling line. The positive input end of the auxiliary balun is connected to the positive output port of the main power amplifier circuit, and then connected to the 30° transmission line 4. The other end of the 30° transmission line 4 is connected to the power supply voltage. The positive end is connected to the positive output port of the auxiliary power amplifier circuit, and then connected to the 30° transmission line 5, the other end of the 30° transmission line 5 is connected to the power supply voltage, one end of the transmission line 6 is connected to the ground, and the other end is connected to the transmission line 7, transmission line 5 and transmission line 6 form a coupling line, the auxiliary balun input negative end is connected to the negative output port of the auxiliary power amplifier circuit, and then connected to the 30° transmission line 8, the other end of the 30° transmission line 8 is connected to the power supply voltage, one end of the transmission line 7 is connected to the transmission line 9, and the other end is connected to the transmission line 6, transmission line 7 and transmission line 8 form a coupling line, one end of the transmission line 9 is connected to the transmission line 7, and the other end is connected to the transmission line 2, and the output equivalent transmission line serves as the output port of the entire output matching network.

Images