GPU video processing load balancing system based on CXL technology

Abstract

The invention discloses a GPU video processing load balancing system based on the CXL technology, and relates to the technical field of video processing, the GPU video processing load balancing system comprises a user cluster terminal, a GPU video processing center, n distributed GPU computing cards and a CXL Switch, the terminal is responsible for sending a video processing task demand to the GPU video processing center and receiving a video processing result fed back by the GPU video processing center; the GPU video processing center is responsible for receiving a video processing task, evaluating time loss of the video processing task, then directly processing the task or issuing the task to the distributed GPU computing card through a CXL Switch, and feeding back a processing result to the terminal in time; and the distributed GPU computing card is responsible for receiving and processing the issued task and sending a processing result back to the GPU video processing center. According to the invention, the calculation load of the GPU video processing center server can be reduced, and the video processing efficiency is improved.

Description

Technical Field

[0001] The invention relates to the technical field of video processing, in particular to a GPU video processing load balancing system based on CXL technology. Background Art

[0002] GPU (Graphics Processing Unit) is a hardware accelerator specially designed for processing graphics and image computing. With the rise of artificial intelligence in recent years, the number of GPUs used by scholars in scientific research and industrial production has increased day by day. The application of GPU has far exceeded the traditional field of graphics rendering and expanded to a wider range of high-quality video processing tasks.

[0003] Load balancing: Load balancing is a method of distributing user requests among multiple node devices in order to improve the overall performance, availability, and reliability of the system. It achieves these goals by optimizing resource usage, maximizing throughput, minimizing response time, and avoiding overloading any one node.

[0004] At present, GPU video processing centers usually adopt the "CPU collaborative GPU joint processing" mode for large-scale video processing tasks. Limited by the performance barriers of the GPU, this mode cannot guarantee the real-time processing needs of massive high-standard videos in a single period of time, and cannot balance the load with the optimal solution, resulting in low video processing efficiency and high latency; and the existing method requires the CPU to collaborate to complete some tasks that should be performed by the GPU, which will inevitably cause CPU computing power loss and increased load, thereby affecting the execution process of other important applications on the video processing center server. Summary of the invention

[0005] In view of the needs and shortcomings of current technological development, the present invention provides a GPU video processing load balancing system based on CXL technology, which is used to meet the needs of large-scale and high-efficiency video processing in GPU video processing centers under the background of the artificial intelligence era.

[0006] The GPU video processing load balancing system based on CXL technology of the present invention solves the above technical problems by adopting the following technical solutions:

[0007] A GPU video processing load balancing system based on CXL technology includes a user cluster terminal, a GPU video processing center, n distributed GPU computing cards and a CXL Switch, wherein:

[0008] The user cluster terminal is responsible for sending video processing task requirements to the GPU video processing center through the network, and receiving the video processing results fed back by the GPU video processing center;

[0009] The GPU video processing center is responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the distributed GPU computing cards through the CXL Switch, and promptly feeding back the video processing results to the user cluster terminal;

[0010] The distributed GPU computing card is responsible for receiving and processing the video processing tasks sent down, and sending the video processing results back to the GPU video processing center.

[0011] Optionally, the GPU video processing center involved includes a GPU video processing terminal server and a GPU video processing distributed control device connected via a PCIe interface, wherein:

[0012] The GPU video processing terminal server deploys software APIs with relevant functions, allowing managers to coordinate the control system from the software level and exchange data with user cluster terminals. The GPU video processing terminal server is also responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the GPU video processing distributed control device through the PCIe interface;

[0013] The GPU video processing distributed control device is responsible for packaging video processing tasks, allocating and sending the packaged video processing tasks to the CXL address of the target distributed GPU computing card through the CXL Switch, and timely collecting the video processing results and sending them to the GPU video processing terminal server.

[0014] Further optionally, the GPU video processing terminal server involved includes a terminal server CPU, a server GPU and a cache module, wherein:

[0015] The terminal server CPU is responsible for receiving the video processing task, evaluating the time loss based on the complexity of the video processing task, and then checking whether the server GPU is idle.

[0016] a) If yes, the video processing task is directly assigned to the server GPU, which performs the video processing task and sends the video processing result back to the terminal server CPU.

[0017] b) If not, the video processing task is assigned to the GPU video processing distributed control device through the PCIe interface. The GPU video processing distributed control device polls the working status of n distributed GPU computing cards, and determines whether to split the video processing task according to the time loss of the video processing task. Then, the split or unsplit video processing task is assigned to at least one target distributed GPU computing card in an idle state through the CXL Switch. After the target distributed GPU computing card completes the video processing task, the video processing result is sent back to the GPU video processing distributed control device, and the GPU video processing distributed control device sends the video processing result back to the terminal server CPU.

[0018] Further optionally, the terminal server CPU involved evaluates the time loss according to the complexity of the video processing task, and the evaluation process specifically applies the following algorithm:

[0019] time total =t*24*time 1 (1)

[0020] time 1 =index x *index y *Complexity / f (2),

[0021]

[0022] Among them, time total is the time loss evaluation result of the terminal server CPU for the video processing task; t is the total length of the video to be processed; time 1 is the estimated duration of single-frame video processing; f is the main frequency of the terminal server CPU executing video processing, which is a constant; Complexity is the complexity coefficient of the target video processing method, which is a constant; index x 、index y Res are the single-order index parameters of each frame of video in the x and y directions respectively; x 、Res y Respectively, they are the pixel values ​​of each frame of video in the x and y directions; refx 、Res refy are the reference pixel values ​​of each frame of video in the x and y directions, which are set by the user; s x 、s y are the GPU processing strides in the x and y directions for each frame of video, which are set by the user; k is the GPU processing element width of the video, which is a fixed value; α x , α y They are the single-order reference values ​​of each frame of video in the x and y directions, respectively, and are preset by the user.

[0023] Preferably, after the server GPU involved executes the video processing task and sends the video processing result back to the terminal server CPU, the terminal server CPU generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network;

[0024] Alternatively, after the target distributed GPU computing card completes the video processing task, it sends the video processing result back to the GPU video processing distributed control device, which verifies the video processing result and then sends the verified video processing result to the terminal server CPU through the PCIe interface. The terminal server CPU generates a video processing log and saves it to the cache module, and finally sends the video processing result to the user cluster terminal through the network.

[0025] Optionally, the GPU video processing distributed control device includes an FPGA chip and a DDR5 memory;

[0026] The FPGA chip is responsible for allocating and scheduling the video processing tasks issued by the terminal server CPU, and sends the task instructions and original video data to the target distributed GPU computing card through CXLSwitch. It also collects the video processing results fed back by the target distributed GPU computing card in a timely manner and sends them to the user cluster terminal through the GPU video processing terminal server.

[0027] The DDR5 memory is responsible for receiving and storing the video processing tasks issued by the GPU video processing terminal server, and sending the video processing tasks to each target distributed GPU computing card according to the FPGA chip scheduling requirements.

[0028] Further optionally, after receiving the video processing task, the target distributed GPU computing card processes the video through six steps of data input and decoding, color space conversion, video analysis and processing, special effects application and synthesis, video data encoding, data output and optimization, and sends the video processing results back to the FPGA chip.

[0029] Further optionally, the FPGA chip involved includes an input data cache module, a GPU execution device polling module, a request decoding module, a video processing demand confirmation module, a data header verification module, a MIG module, a task splitting scheme confirmation module, a splitting scheme data transceiver FSM state machine, a non-split scheme data transceiver FSM state machine, a data receiving merge cache module, a video processing result data verification log generation module, a BRAM storage module and an output data cache module;

[0030] The FPGA chip receives the video processing task sent by the terminal server CPU and performs allocation and scheduling, including:

[0031] The input data cache module caches the task instructions and the original video data, and sends the task instructions to the request decoding module. At the same time, the input data cache module sends a polling instruction to the GPU execution device polling module, and starts polling the working idle state of the distributed GPU computing card through CXL;

[0032] The request decoding module decodes the task instruction, obtains the universal identification code for the FPGA chip to identify the video processing method, and sends the universal identification code and the original video data to the video processing requirement confirmation module;

[0033] The video processing requirement confirmation module confirms whether the video processing task corresponds to the original video data format. If so, the universal identification code of the video processing method and the header of the video to be processed are sent to the MIG module and temporarily stored by the DDR5 memory. Subsequently, the video processing method identification code and the original video data are sent to the task splitting scheme confirmation module;

[0034] The task splitting scheme confirmation module receives the polling results of the GPU execution device polling module through CXL and confirms the idle distributed GPU computing cards;

[0035] Based on the time loss evaluation data of the terminal server CPU for the video processing task, confirm whether the video processing task needs to be split and the specific number of splits, and the number of splits does not exceed the number of idle distributed GPU computing cards. a) If the current video processing task does not need to be split, the task splitting scheme confirmation module directly sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card and the original video data to the splitting scheme data transceiver FSM state machine, and the splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data to the target distributed GPU through CXL. The CXL address of the computing card; b) if the current video processing task needs to be split, the task splitting scheme confirmation module sequentially splits the original video data into several parts, allocates the CXL address of the idle distributed GPU computing card to each original video data, and sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card and the corresponding original video data to the non-splitting scheme data transceiver FSM state machine, and the non-splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data split into several parts to the CXL addresses of multiple target distributed GPU computing cards through CXL;

[0036] After the target distributed GPU computing card completes the calculation, it writes the video processing results back to the corresponding split scheme data receiving and sending FSM state machine / non-split scheme data receiving and sending FSM state machine through CXL, and sends the video processing results to the data receiving and merging cache module;

[0037] The data receiving and merging buffer module directly sends the video processing result to the video processing result data verification log generation module and the header verification module, or the data receiving and merging buffer module splices the video processing results of multiple video processing subtasks and sends them to the video processing result data verification log generation module and the header verification module;

[0038] The header verification module reads the video processing mode universal identification code and the video header data to be processed stored in the DDR5 memory through the MIG module, and after confirming that the video processing result corresponds to the video processing task requirement, informs the video processing result data verification log generation module;

[0039] The video processing result data verification log generation module verifies the video processing result. After verifying that the video processing result executed by the distributed GPU is accurate, the video processing log is generated and stored in the BRAM memory. Subsequently, the video processing result data verification log generation module sends the verified video processing result to the output data cache module.

[0040] The output data cache module sends the verified video processing results to the terminal server CPU via the PCIe interface.

[0041] Further optionally, the workflow of the GPU video processing load balancing system involved is as follows:

[0042] S1, the user cluster terminal sends the video processing task requirements to the GPU video processing center through the network;

[0043] S2, the terminal server CPU of the GPU video processing center first receives the video processing task and then evaluates the time loss according to the complexity of the video processing task;

[0044] S3, the terminal server CPU checks whether the server GPU is in an idle state, if not, jumps to step S4, if so, jumps to step S8;

[0045] S4, the terminal server CPU distributes the video processing task to the GPU video processing distributed control device through the PCIe interface;

[0046] S5, the FPGA chip of the GPU video processing distributed control device polls the working status of n distributed GPU computing cards, and determines whether split processing is required based on the time loss evaluation of the current video processing task, and then distributes the corresponding task to at least one target distributed GPU computing card in an idle state through CXLSwitch;

[0047] S6, the target distributed GPU computing card completes the corresponding video processing task and sends the video processing result back to the GPU video processing distributed control device;

[0048] S7, the GPU video processing distributed control device receives the video processing result, verifies the video processing result and generates a video processing log, then sends the verified video processing result back to the terminal server CPU through the PCIe interface, and jumps to step S9;

[0049] S8, the terminal server CPU directly assigns the task to the server GPU, the server GPU executes the current video processing task, and sends the video processing result back to the terminal server CPU;

[0050] S9. The terminal server CPU receives the video processing result, generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network.

[0051] The GPU video processing load balancing system based on CXL technology of the present invention has the following beneficial effects compared with the prior art:

[0052] 1. The present invention adopts the new core design concept of "GPU video processing center uniformly controls distributed GPU computing cards", takes CXL high-speed interconnection technology as the architecture carrier, and uses the terminal server CPU of the video processing center as the video processing control terminal to achieve centralized management and overall coordination of multiple distributed GPU computing cards to complete large-scale video processing tasks in parallel in a single period of time;

[0053] 2. The present invention constructs a GPU video processing load balancing system composed of a user cluster terminal, a GPU video processing center, multiple distributed GPU computing cards, and the CXL Switch equipped with them. By distributing the large-scale video processing requirements that need to be collaboratively executed by the CPU and GPU of the video processing center server to multiple distributed GPU computing cards to achieve single-time large-scale video parallel processing, the computing load of the GPU video processing center server is greatly reduced, the video processing efficiency of the system is significantly improved, and the unified scheduling control of large-scale GPU video processing is better realized, which significantly improves the system performance;

[0054] 3. The present invention uses CXL technology to realize communication between the video processing center and multiple distributed GPU computing cards, which makes data transmission and communication more efficient and more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Attached Figure 1 is a system architecture diagram of the present invention;

[0056] Attached Figure 2 is a specific architecture diagram of the first embodiment of the present invention;

[0057] Attached Figure 3It is a module connection block diagram of the FPGA chip in the first embodiment of the present invention;

[0058] Attached Figure 4 It is a flow chart of the GPU video processing load balancing system described in the present invention. DETAILED DESCRIPTION

[0059] In order to make the technical solution, the technical problem solved and the technical effect of the present invention more clearly understood, the technical solution of the present invention is clearly and completely described below in conjunction with specific embodiments.

[0060] The English words involved in the following embodiments are now explained:

[0061] CXL technology is a new interconnect technology standard, the full name is Compute Express Link, which is designed to achieve high-speed and efficient interconnection between CPU and accelerators such as GPU and FPGA. CXL technology achieves memory sharing and consistency between devices through high-bandwidth, low-latency connections, thereby significantly improving computing performance and memory scalability. Moreover, CXL is not only based on the PCIe specification, but also has major functional expansions, such as memory pooling and memory sharing, which enables multiple devices to access the same memory address space.

[0062] CXL Switch is a high-performance switch based on Compute Express Link (CXL) technology, designed to achieve high-speed interconnection and memory sharing between CPU and various acceleration devices (such as GPU, FPGA, etc.). CXL Switch provides a more flexible and scalable way to manage computing resources by supporting multiple ports and complex topologies such as CLOS or Mesh types. This switch not only improves the processing power and memory scalability within the data center, but also provides a solid foundation for future computing needs.

[0063] A GPU computing card is a hardware device specifically designed for high-performance computing tasks. Its main features are powerful parallel processing capabilities and high-speed graphics rendering capabilities. GPU computing cards usually contain multiple cores, each of which can execute commands independently, which makes them perform well when processing large-scale data sets. Compared with traditional graphics cards, GPU computing cards focus more on computing performance rather than just image output. This design makes them widely used in scientific computing, artificial intelligence, deep learning and other fields. In addition, mainstream GPU manufacturers such as NVIDIA and AMD provide a variety of computing cards to meet the needs of different application scenarios.

[0064] Embodiment 1:

[0065] Combined with Figure 1 , this embodiment proposes a GPU video processing load balancing system based on CXL technology, which includes a user cluster terminal, a GPU video processing center, n distributed GPU computing cards and a CXL Switch.

[0066] (i) The user cluster terminal is responsible for sending video processing task requirements to the GPU video processing center through the network, and receiving the video processing results fed back by the GPU video processing center.

[0067] (2) The GPU video processing center is responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the distributed GPU computing cards through the CXL Switch, and promptly feeding back the video processing results to the user cluster terminal.

[0068] 1. The GPU video processing center of this embodiment includes a GPU video processing terminal server and a GPU video processing distributed control device connected via a PCIe interface, wherein:

[0069] The GPU video processing terminal server deploys software APIs with relevant functions, allowing managers to coordinate the control system from the software level and exchange data with user cluster terminals. The GPU video processing terminal server is also responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the GPU video processing distributed control device through the PCIe interface;

[0070] The GPU video processing distributed control device is responsible for packaging video processing tasks, allocating and sending the packaged video processing tasks to the CXL address of the target distributed GPU computing card through the CXL Switch, and timely collecting the video processing results and sending them to the GPU video processing terminal server.

[0071] Specifically, the terminal server CPU is responsible for receiving the video processing task and evaluating the time loss according to the complexity of the video processing task. The evaluation process specifically applies the following algorithm:

[0072] time total =t*24*time 1 (1)

[0073] time 1 =index x *index y *Complexity / f (2),

[0074]

[0075] Among them, time total is the time loss evaluation result of the terminal server CPU for the video processing task; t is the total length of the video to be processed; time 1 is the estimated duration of single-frame video processing; f is the main frequency of the terminal server CPU executing video processing, which is a constant; Complexity is the complexity coefficient of the target video processing method, which is a constant; index x 、index y Res are the single-order index parameters of each frame of video in the x and y directions respectively; x 、Res y Respectively, they are the pixel values ​​of each frame of video in the x and y directions; refx 、Res refy are the reference pixel values ​​of each frame of video in the x and y directions, which are set by the user; s x 、s y are the GPU processing strides in the x and y directions for each frame of video, which are set by the user; k is the GPU processing element width of the video, which is a fixed value; α x , α y They are the single-order reference values ​​of each frame of video in the x and y directions, respectively, and are preset by the user.

[0076] Specifically, combined with the Figure 2 ,The GPU video processing terminal server includes a terminal server CPU, a server GPU and a cache module.

[0077] The terminal server CPU evaluates the time loss based on the complexity of the video processing task and checks whether the server GPU is idle.

[0078] a) If yes, the video processing task is directly assigned to the server GPU, which executes the video processing task and sends the video processing result back to the terminal server CPU. The terminal server CPU generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network;

[0079] b) If not, the video processing task is assigned to the GPU video processing distributed control device through the PCIe interface. The GPU video processing distributed control device polls the working status of n distributed GPU computing cards, and determines whether to split the video processing task according to the time loss of the video processing task. Then, the split or unsplit video processing task is assigned to at least one target distributed GPU computing card in an idle state through the CXL Switch. After the target distributed GPU computing card completes the video processing task, the video processing result is sent back to the GPU video processing distributed control device. The GPU video processing distributed control device verifies the video processing result, and then sends the verified video processing result to the terminal server CPU through the PCIe interface. The terminal server CPU generates a video processing log and saves it to the cache module. Finally, the video processing result is sent to the user cluster terminal through the network.

[0080] 2. Combined with attachment Figure 2 , the GPU video processing distributed control device of this embodiment includes an FPGA chip and a DDR5 memory.

[0081] The FPGA chip is responsible for allocating and scheduling the video processing tasks issued by the terminal server CPU, and sends the task instructions and original video data to the target distributed GPU computing card through CXLSwitch. It also collects the video processing results fed back by the target distributed GPU computing card in a timely manner and sends them to the user cluster terminal through the GPU video processing terminal server.

[0082] The DDR5 memory is responsible for receiving and storing the video processing tasks issued by the GPU video processing terminal server, and sending the video processing tasks to each target distributed GPU computing card according to the FPGA chip scheduling requirements.

[0083] Specifically, combined with the Figure 3 The FPGA chip includes an input data cache module, a GPU execution device polling module, a request decoding module, a video processing demand confirmation module, a data header verification module, a MIG module, a task splitting scheme confirmation module, a splitting scheme data transceiver FSM state machine, a non-split scheme data transceiver FSM state machine, a data receiving merge cache module, a video processing result data verification log generation module, a BRAM storage module and an output data cache module.

[0084] The FPGA chip receives the video processing task sent by the terminal server CPU and performs allocation and scheduling, including:

[0085] The input data cache module caches the task instructions and the original video data, and sends the task instructions to the request decoding module. At the same time, the input data cache module sends a polling instruction to the GPU execution device polling module, and starts polling the working idle state of the distributed GPU computing card through CXL;

[0086] The request decoding module decodes the task instruction, obtains the universal identification code for the FPGA chip to identify the video processing method, and sends the universal identification code and the original video data to the video processing requirement confirmation module;

[0087] The video processing requirement confirmation module confirms whether the video processing task corresponds to the original video data format. If so, the universal identification code of the video processing method and the header of the video to be processed are sent to the MIG module and temporarily stored by the DDR5 memory. Subsequently, the video processing method identification code and the original video data are sent to the task splitting scheme confirmation module;

[0088] The task splitting scheme confirmation module receives the polling results of the GPU execution device polling module through CXL and confirms the idle distributed GPU computing cards;

[0089] Based on the time loss evaluation data of the terminal server CPU for the video processing task, confirm whether the video processing task needs to be split and the specific number of splits, and the number of splits does not exceed the number of idle distributed GPU computing cards. a) If the current video processing task does not need to be split, the task splitting scheme confirmation module directly sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card and the original video data to the splitting scheme data transceiver FSM state machine, and the splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data to the target distributed GPU through CXL. The CXL address of the computing card; b) if the current video processing task needs to be split, the task splitting scheme confirmation module sequentially splits the original video data into several parts, allocates the CXL address of the idle distributed GPU computing card to each original video data, and sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card and the corresponding original video data to the non-splitting scheme data transceiver FSM state machine, and the non-splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data split into several parts to the CXL addresses of multiple target distributed GPU computing cards through CXL;

[0090] After the target distributed GPU computing card completes the calculation, it writes the video processing results back to the corresponding split scheme data receiving and sending FSM state machine / non-split scheme data receiving and sending FSM state machine through CXL, and sends the video processing results to the data receiving and merging cache module;

[0091] The data receiving and merging buffer module directly sends the video processing result to the video processing result data verification log generation module and the header verification module, or the data receiving and merging buffer module splices the video processing results of multiple video processing subtasks and sends them to the video processing result data verification log generation module and the header verification module;

[0092] The header verification module reads the video processing mode universal identification code and the video header data to be processed stored in the DDR5 memory through the MIG module, and after confirming that the video processing result corresponds to the video processing task requirement, informs the video processing result data verification log generation module;

[0093] The video processing result data verification log generation module verifies the video processing result. After verifying that the video processing result executed by the distributed GPU is accurate, the video processing log is generated and stored in the BRAM memory. Subsequently, the video processing result data verification log generation module sends the verified video processing result to the output data cache module.

[0094] The output data cache module sends the verified video processing results to the terminal server CPU via the PCIe interface.

[0095] (3) The distributed GPU computing card is responsible for receiving the video processing tasks sent down, and processes the video through six steps: data input and decoding, color space conversion, video analysis and processing, special effects application and synthesis, video data encoding, data output and optimization, and then sends the video processing results back to the GPU video processing center.

[0096] Embodiment 2:

[0097] Reference Figure 4 This embodiment proposes a GPU video processing load balancing system based on CXL technology, which is based on the structure described in the first embodiment and executes the following workflow to achieve GPU video processing load balancing:

[0098] S1, the user cluster terminal sends the video processing task requirements to the GPU video processing center through the network;

[0099] S2, the terminal server CPU of the GPU video processing center first receives the video processing task and then evaluates the time loss according to the complexity of the video processing task;

[0100] S3, the terminal server CPU checks whether the server GPU is in an idle state, if not, jumps to step S4, if so, jumps to step S8;

[0101] S4, the terminal server CPU distributes the video processing task to the GPU video processing distributed control device through the PCIe interface;

[0102] S5, the FPGA chip of the GPU video processing distributed control device polls the working status of n distributed GPU computing cards, and determines whether split processing is required based on the time loss evaluation of the current video processing task, and then distributes the corresponding task to at least one target distributed GPU computing card in an idle state through CXLSwitch;

[0103] S6, the target distributed GPU computing card completes the corresponding video processing task and sends the video processing result back to the GPU video processing distributed control device;

[0104] S7, the GPU video processing distributed control device receives the video processing result, verifies the video processing result and generates a video processing log, then sends the verified video processing result back to the terminal server CPU through the PCIe interface, and jumps to step S9;

[0105] S8, the terminal server CPU directly assigns the task to the server GPU, the server GPU executes the current video processing task, and sends the video processing result back to the terminal server CPU;

[0106] S9. The terminal server CPU receives the video processing result, generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network.

[0107] In summary, it can be seen that the GPU video processing load balancing system based on CXL technology of the present invention can reduce the computing load of the GPU video processing center server and improve the video processing efficiency.

[0108] The above specific examples are used to explain the principles and implementation methods of the present invention in detail. These examples are only used to help understand the core technical content of the present invention. Based on the above specific embodiments of the present invention, any improvements and modifications made by technicians in this technical field without departing from the principles of the present invention should fall within the scope of patent protection of the present invention.

Claims

1. A GPU video processing load balancing system based on CXL technology, characterized in that: It includes user cluster terminals, GPU video processing center, n distributed GPU computing cards and CXL Switch, among which: The user cluster terminal is responsible for sending video processing task requirements to the GPU video processing center through the network, and receiving the video processing results fed back by the GPU video processing center; The GPU video processing center is responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the distributed GPU computing cards through the CXL Switch, and promptly feeding back the video processing results to the user cluster terminal; The distributed GPU computing card is responsible for receiving and processing the video processing tasks sent down, and sending the video processing results back to the GPU video processing center.

2. The GPU video processing load balancing system based on CXL technology according to claim 1, characterized in that: The GPU video processing center includes a GPU video processing terminal server and a GPU video processing distributed control device connected via a PCIe interface, wherein: The GPU video processing terminal server deploys software APIs with relevant functions, allowing managers to coordinate the control system from the software level and exchange data with user cluster terminals. The GPU video processing terminal server is also responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the GPU video processing distributed control device through the PCIe interface; The GPU video processing distributed control device is responsible for packaging video processing tasks, allocating and sending the packaged video processing tasks to the CXL address of the target distributed GPU computing card through the CXL Switch, and timely collecting the video processing results and sending them to the GPU video processing terminal server.

3. The GPU video processing load balancing system based on CXL technology according to claim 2, characterized in that: The GPU video processing terminal server includes a terminal server CPU, a server GPU and a cache module, wherein: The terminal server CPU is responsible for receiving the video processing task, evaluating the time loss based on the complexity of the video processing task, and then checking whether the server GPU is idle. a) If yes, the video processing task is directly assigned to the server GPU, which performs the video processing task and sends the video processing result back to the terminal server CPU. b) If not, the video processing task is assigned to the GPU video processing distributed control device through the PCIe interface. The GPU video processing distributed control device polls the working status of n distributed GPU computing cards, and determines whether to split the video processing task according to the time loss of the video processing task. Then, the split or unsplit video processing task is assigned to at least one target distributed GPU computing card in an idle state through the CXL Switch. After the target distributed GPU computing card completes the video processing task, the video processing result is sent back to the GPU video processing distributed control device, and the GPU video processing distributed control device sends the video processing result back to the terminal server CPU.

4. The GPU video processing load balancing system based on CXL technology according to claim 3, characterized in that: The terminal server CPU evaluates the time loss based on the complexity of the video processing task. The evaluation process specifically applies the following algorithm: time total =t*24*time1 (1), time1=index x *index y *Complexity / f (2), Among them, time total is the time loss evaluation result of the terminal server CPU for the video processing task; t is the total duration of the video to be processed; time1 is the estimated duration of single-frame video processing; f is the main frequency of the terminal server CPU executing video processing, which is a constant; Complexity is the complexity coefficient of the target video processing method, which is a constant; index x 、index y Res are the single-order index parameters of each frame of video in the x and y directions respectively; x 、Res y Respectively, they are the pixel values ​​of each frame of video in the x and y directions; refx 、Res refy are the reference pixel values ​​of each frame of video in the x and y directions, which are set by the user; s x 、s y are the GPU processing strides in the x and y directions for each frame of video, which are set by the user; k is the GPU processing element width of the video, which is a fixed value; α x , α y They are the single-order reference values ​​of each frame of video in the x and y directions, respectively, and are preset by the user.

5. The GPU video processing load balancing system based on CXL technology according to claim 3, characterized in that: After the server GPU executes the video processing task and sends the video processing result back to the terminal server CPU, the terminal server CPU generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network; Alternatively, after the target distributed GPU computing card completes the video processing task, it sends the video processing result back to the GPU video processing distributed control device, which verifies the video processing result and then sends the verified video processing result to the terminal server CPU through the PCIe interface. The terminal server CPU generates a video processing log and saves it to the cache module, and finally sends the video processing result to the user cluster terminal through the network.

6. The GPU video processing load balancing system based on CXL technology according to claim 5, characterized in that: The GPU video processing distributed control device includes an FPGA chip and a DDR5 memory; The FPGA chip is responsible for allocating and scheduling the video processing tasks issued by the terminal server CPU, and sends the task instructions and original video data to the target distributed GPU computing card through CXLSwitch. It also collects the video processing results fed back by the target distributed GPU computing card in a timely manner and sends them to the user cluster terminal through the GPU video processing terminal server. The DDR5 memory is responsible for receiving and storing the video processing tasks issued by the GPU video processing terminal server, and sending the video processing tasks to each target distributed GPU computing card according to the FPGA chip scheduling requirements.

7. The GPU video processing load balancing system based on CXL technology according to claim 6, characterized in that: After receiving the video processing task, the target distributed GPU computing card processes the video through six steps: data input and decoding, color space conversion, video analysis and processing, special effects application and synthesis, video data encoding, data output and optimization, and sends the video processing results back to the FPGA chip.

8. The GPU video processing load balancing system based on CXL technology according to claim 6, characterized in that: The FPGA chip includes an input data cache module, a GPU execution device polling module, a request decoding module, a video processing demand confirmation module, a data header verification module, a MIG module, a task splitting scheme confirmation module, a splitting scheme data transceiver FSM state machine, a non-split scheme data transceiver FSM state machine, a data receiving merge cache module, a video processing result data verification log generation module, a BRAM storage module and an output data cache module; The FPGA chip receives the video processing task sent by the terminal server CPU and performs allocation and scheduling, specifically including: The input data cache module caches the task instructions and the original video data, and sends the task instructions to the request decoding module. At the same time, the input data cache module sends a polling instruction to the GPU execution device polling module to start polling the working idle state of the distributed GPU computing card through CXL; The request decoding module decodes the task instruction to obtain a universal identification code for the FPGA chip to identify the video processing mode, and sends the universal identification code and the original video data to the video processing demand confirmation module; The video processing requirement confirmation module confirms whether the video processing task corresponds to the original video data format. If so, the universal identification code of the video processing method and the header of the video to be processed are sent to the MIG module and temporarily stored by the DDR5 memory. Subsequently, the video processing method identification code and the original video data are sent to the task splitting scheme confirmation module; The task splitting scheme confirmation module receives the polling results of the GPU execution device polling module through CXL and confirms the idle distributed GPU computing cards; Based on the time loss evaluation data of the terminal server CPU for the video processing task, confirm whether the video processing task needs to be split and the specific number of splits, and the number of splits does not exceed the number of idle distributed GPU computing cards. a) If the current video processing task does not need to be split, the task splitting scheme confirmation module directly sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card and the original video data to the splitting scheme data transceiver FSM state machine, and the splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data to the target distributed GPU through CXL. The CXL address of the computing card; b) if the current video processing task needs to be split, the task splitting scheme confirmation module sequentially splits the original video data into several parts, allocates the CXL address of the idle distributed GPU computing card to each original video data, and sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card and the corresponding original video data to the non-splitting scheme data transceiver FSM state machine, and the non-splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data split into several parts to the CXL addresses of multiple target distributed GPU computing cards through CXL; After the target distributed GPU computing card completes the calculation, it writes the video processing results back to the corresponding split scheme data receiving and sending FSM state machine / non-split scheme data receiving and sending FSM state machine through CXL, and sends the video processing results to the data receiving and merging cache module; The data receiving and merging buffer module directly sends the video processing result to the video processing result data verification log generation module and the header verification module, or the data receiving and merging buffer module splices the video processing results of multiple video processing subtasks and sends them to the video processing result data verification log generation module and the header verification module; The header verification module reads the video processing mode universal identification code and the video header data to be processed stored in the DDR5 memory through the MIG module, and after confirming that the video processing result corresponds to the video processing task requirement, informs the video processing result data verification log generation module; The video processing result data verification log generation module verifies the video processing result. After verifying that the video processing result executed by the distributed GPU is accurate, the video processing log is generated and stored in the BRAM memory. Subsequently, the video processing result data verification log generation module sends the verified video processing result to the output data cache module. The output data cache module sends the verified video processing results to the terminal server CPU via the PCIe interface.

9. The GPU video processing load balancing system based on CXL technology according to claim 6, characterized in that: The workflow of the GPU video processing load balancing system is as follows: S1, the user cluster terminal sends the video processing task requirements to the GPU video processing center through the network; S2, the terminal server CPU of the GPU video processing center first receives the video processing task and then evaluates the time loss according to the complexity of the video processing task; S3, the terminal server CPU checks whether the server GPU is in an idle state, if not, jumps to step S4, if so, jumps to step S8; S4, the terminal server CPU distributes the video processing task to the GPU video processing distributed control device through the PCIe interface; S5, the FPGA chip of the GPU video processing distributed control device polls the working status of n distributed GPU computing cards, and determines whether split processing is required based on the time loss evaluation of the current video processing task, and then distributes the corresponding task to at least one target distributed GPU computing card in an idle state through CXL Switch; S6, the target distributed GPU computing card completes the corresponding video processing task and sends the video processing result back to the GPU video processing distributed control device; S7, the GPU video processing distributed control device receives the video processing result, verifies the video processing result and generates a video processing log, then sends the verified video processing result back to the terminal server CPU through the PCIe interface, and jumps to step S9; S8, the terminal server CPU directly assigns the task to the server GPU, the server GPU executes the current video processing task, and sends the video processing result back to the terminal server CPU; S9. The terminal server CPU receives the video processing result, generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network.

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