An integrated circuit scan chain diagnosis method and system based on artificial neural network

Abstract

The present invention discloses an integrated circuit scan chain diagnosis method and system based on artificial neural network. The method first injects two random faults, stuck at‑0 and stuck at‑1, into each scan trigger in the integrated circuit scan chain, wherein a random cycle of the fault is obtained by generating a random number through a linear feedback shift register; then automatic test vector generation is performed to obtain a pattern report containing fault information and a corresponding simulation log; finally, an integer fault vector and a label vector are obtained through the pattern report and the simulation log, and the integer fault vector and the label vector are input into the artificial neural network for training and verification, and the fault position in the integrated circuit scan chain is obtained by predicting the trained artificial neural network. The present invention generates random cycle faults, eliminates abnormal data, uses an artificial neural network model, effectively reduces the risk of human misjudgment and missed detection, and realizes accurate prediction.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testability design, in particular to an integrated circuit scan chain diagnosis method and system based on artificial neural network. Background Art

[0002] Scan testing has been proven to be a cost-effective way to achieve good test coverage in digital circuits. However, the integrity of the scan chain is the Achilles' heel of scan testing. The chip area consumed by the scan elements, chain connections, and control circuits varies from design to design. Among them, the scan elements and clocks can account for nearly 30% of the chip area. The percentage of defects that cause scan chain failures also varies from design to design, ranging from 10% to 30%, and chain failures account for almost 50% of chip failures. Therefore, scan chain fault diagnosis is of great significance for effective scan detection. For intermittent faults, the accuracy of existing test diagnosis methods needs to be improved, especially for faulty circuits with a low probability of failure, where abnormal data has a greater impact on the accuracy of prediction. Summary of the invention

[0003] Purpose of the invention: The purpose of the present invention is to provide an integrated circuit scan chain diagnosis method and system based on artificial neural network with high accuracy and fast diagnosis speed.

[0004] Technical solution: The integrated circuit scan chain diagnosis method based on artificial neural network described in the present invention comprises the following steps:

[0005] Injecting two random stuck-at-0 and stuck-at-1 faults into each scan trigger in the scan chain of the integrated circuit, wherein the random cycle of the fault is obtained by generating a random number through a linear feedback shift register;

[0006] Perform automatic test vector generation to obtain a pattern report containing fault information and the corresponding simulation log;

[0007] The integer fault vector and label vector are obtained through pattern report and simulation log, and the integer fault vector and label vector are input into artificial neural network for training and verification. The fault position in the integrated circuit scan chain is predicted by the trained artificial neural network.

[0008] Furthermore, after obtaining the integer fault vector and the label vector through the pattern report and the simulation log, the method further includes: deleting the value of the integer fault vector that is all 0.

[0009] Further, the method of injecting two random stuck-at-0 and stuck-at-1 faults into each scan trigger in the integrated circuit scan chain, wherein the random cycle of the fault is obtained by generating a random number through a linear feedback shift register, includes: generating an intermittent fault with a random intermittent value of 0%-100% according to the random cycle.

[0010] Furthermore, obtaining the integer fault vector and label vector through the pattern report and the simulation log includes: adding the binary fault vector of each pattern bit by bit to obtain the integer fault vector; and obtaining the label vector according to the scan trigger bit of the fault injection.

[0011] Furthermore, the integer fault vector and label vector are obtained through pattern report and simulation log, and the integer fault vector and label vector are input into the artificial neural network for training and verification, including: for the input integer fault vector, the artificial neural network generates a corresponding predicted label vector, the scan trigger bit with the highest probability is 1, and the remaining bits are 0, and the prediction accuracy of the artificial neural network is obtained by comparing with the input label vector.

[0012] Furthermore, the loss function of the artificial neural network is a cross entropy function.

[0013] The integrated circuit scan chain diagnostic system based on artificial neural network of the present invention comprises:

[0014] A fault injection unit is used to inject two random faults, stuck-at-0 and stuck-at-1, into each scan trigger in the scan chain of the integrated circuit, wherein a random cycle of the fault is obtained by generating a random number through a linear feedback shift register;

[0015] An automatic test vector generation unit, used to perform automatic test vector generation and obtain a pattern report containing fault information and a corresponding simulation log;

[0016] The diagnostic unit is used to obtain integer fault vectors and label vectors through pattern reports and simulation logs, input the integer fault vectors and label vectors into artificial neural networks for training and verification, and predict the fault locations in the integrated circuit scan chain through the trained artificial neural network.

[0017] Furthermore, after obtaining the integer fault vector and the label vector through the pattern report and the simulation log, the method further includes: deleting the value of the integer fault vector that is all 0.

[0018] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the integrated circuit scan chain diagnosis method based on artificial neural network is implemented.

[0019] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the integrated circuit scan chain diagnosis method based on an artificial neural network is implemented.

[0020] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) the present invention screens out integer fault vectors with all 0 values, and after eliminating these abnormal data, the prediction accuracy can be improved; (2) the present invention adds a linear feedback shift register to generate pseudo-random numbers to ensure the randomness of the fault occurrence cycle; (3) the present invention can process complex fault vectors by constructing an artificial neural network model, effectively reduce the risk of human misjudgment and missed detection, and achieve accurate prediction. In actual test environments, integrated circuits are often interfered by various noises, resulting in unstable diagnostic data. Traditional methods are often sensitive to these noises and are prone to misjudgment, especially in the detection of intermittent faults, which may occur irregularly in each shift or capture cycle. In contrast, the present invention can effectively process noisy input data by utilizing the robustness of artificial neural networks, and still maintain high-precision diagnostic results. For uncertain data, the nonlinear characteristics of neural networks enable them to have stronger adaptability and better handle these complex situations, thereby improving the stability and reliability of diagnosis; (4) Since neural networks have good generalization capabilities, the present invention can achieve high-precision fault classification and diagnosis in different types of integrated circuit designs, significantly reducing diagnostic time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of the integrated circuit scan chain diagnosis method of the present invention.

[0022] Figure 2 Schematic diagram of a scan chain fault circuit generation process according to an embodiment of the present invention.

[0023] Figure 3 Schematic diagram of an intermittent stuck-at fault circuit according to an embodiment of the present invention.

[0024] Figure 4 Schematic diagram of a simulation log according to an embodiment of the present invention.

[0025] Figure 5 Schematic diagram of a pattern report according to an embodiment of the present invention.

[0026] Figure 6Schematic diagram of integer fault vectors and label vectors in a training set according to an embodiment of the present invention.

[0027] Figure 7 Schematic diagram of the diagnosis result of the embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0029] like Figure 1 As shown, the integrated circuit scan chain diagnosis method based on artificial neural network includes the following steps.

[0030] Step 1: Read the netlist file and inject faults: Read the netlist file of the circuit, modify the circuit, and inject stuck-at-0 and stuck-at-1 faults into each scan trigger.

[0031] Step 2: Generate a fault probability circuit netlist: Based on the netlist of each injected fault, generate different versions with fault probability ranging from 0% to 100% to simulate the various possibilities of fault occurrence and obtain an intermittent fault circuit netlist; by adding a linear feedback shift register, generate pseudo-random numbers to ensure the randomness of the fault occurrence cycle.

[0032] Step 3: For all intermittent fault circuit netlist files, execute ATPG to automatically test vectors through Tetra Max to generate a pattern report containing fault information; run it through the VCS simulation tool to generate a simulation log containing fault information.

[0033] The pattern report contains the shift-in, shift-out and expected capture values ​​of each pattern. VCS simulation can obtain the shift-out and capture values ​​of the actual circuit under fault conditions.

[0034] Step 4: Obtain a data set based on the information in the simulation log and pattern report, and divide the data into a training set and a test set to ensure consistency in subsequent model training and verification.

[0035] XOR the expected pattern and the actual pattern to obtain a binary fault vector; add the binary fault vectors of each pattern bit by bit to obtain an integer fault vector; filter out the values ​​of the integer fault vector that are all 0, and process the corresponding abnormal data points in the label vector.

[0036] The label vector is obtained according to the scan flip-flop bits into which the fault is injected.

[0037] The integer fault vector and the corresponding label vector are organized into a matrix form and adapted to the input of the model.

[0038] Step 5: Normalize or standardize the integer fault vectors and label vectors in the training set to ensure that the input data format meets the requirements of the ANN, reduce numerical deviations during the training process, and improve the model convergence stability. The training set and the validation set are input into the ANN artificial neural network model for training and validation, and the embedding dimension and the number of message passing iterations are adjusted based on the loss function to obtain the optimized ANN artificial neural network model.

[0039] The validation set data is input for verification. The model will input the probability that each scan trigger is a faulty scan trigger and generate a label vector. The scan trigger bit with the highest probability is 1, and the remaining bits are 0. The faulty bit scan trigger index diagnosed by the model is output.

[0040] After the model generates the label vector, it will be compared with the actual label vector in the validation set and the diagnostic accuracy of the model will be output.

[0041]

[0042] Step 6: Select an artificial neural network architecture suitable for fault diagnosis and define the input layer to match the number of bits of the scan chain trigger. Design the hidden layer according to the complexity of the problem and reasonably configure the number of neurons to ensure that the model has sufficient expressive power. Finally, set the output layer to predict the probability of each bit failure.

[0043] Step 7: Set the initial learning rate and gradually adjust the training batch and number of iterations to optimize model performance. Introduce early stopping or learning rate decay mechanism to prevent the model from overfitting or underfitting and ensure generalization performance.

[0044] Step 8: Use the test set to evaluate the model, record the accuracy, precision, recall, and F1 value, and analyze the performance of the model in fault detection. If the test results are not ideal, adjust the model parameters (such as the number of hidden layers, the number of neurons, the learning rate, etc.), and retrain the model to improve the diagnostic accuracy and reliability.

[0045] In order to facilitate the understanding of the present invention by those who are not skilled in the art, this embodiment is explained separately from the following four aspects, as follows:

[0046] (1) Integrated circuit scan chain diagnosis process based on artificial neural network.

[0047] A complete scan chain diagnosis method based on artificial neural network is divided into four stages, namely, reading test data, fault location, fault classification, and generating diagnostic reports; since the traditional scan chain diagnosis process is inefficient, has limited ability to identify complex faults, and requires a lot of human intervention, in order to solve this problem, the present invention proposes an integrated circuit scan chain fault diagnosis method based on artificial neural network. The method is based on an adaptive neural network architecture and is implemented through modules such as dynamically adjusting the neural network structure, optimizing the training algorithm, and accurately classifying the fault type.

[0048] The method of the present invention introduces a parallel training mechanism of a neural network, which can process a large amount of scan chain data in a short time, automatically learn and extract data features, thereby greatly improving the efficiency of fault detection and classification. By adaptively adjusting the number of network layers and the number of nodes, redundant calculations in the diagnosis process are eliminated to ensure high accuracy and high coverage of fault detection. Compared with the traditional rule-based diagnosis mode, the neural network can autonomously learn fault modes in a complex circuit environment and has stronger robustness and generalization capabilities. The distributed computing architecture based on neural networks can process a larger amount of scan chain data per unit time, and achieve higher fault classification accuracy by continuously optimizing the model weights. The advantages of the distributed architecture are not only reflected in the accelerated diagnosis speed, but also provide greater memory resources and computing power scalability, so as to cope with complex fault scenarios of large-scale integrated circuits.

[0049] Reference Figure 1, read the circuit netlist file that has been inserted into the scan chain, and according to the circuit netlist file, inject stuck-at-0 and stuck-at-1 faults into each scan trigger on the scan chain bit by bit, and generate corresponding intermittent faults with fault occurrence probability ranging from 0% to 100%, and obtain all fault circuit netlists. Perform ATPG on all generated fault circuit netlists, run VCS simulation to generate pattern reports and simulation logs. According to the report, the first pattern is usually a chain test to check whether the scan chain has a fault and the type of fault. Secondly, extract and preprocess the simulation log data to generate integer fault vectors and label vectors required by the model. For fault circuits with a low probability of fault occurrence, data with integer fault vectors all being 0 will be generated, but corresponding to different fault locations. These abnormal data will affect the accuracy of the prediction. For this problem, the present invention removes the values ​​with integer fault vectors all being 0 in the data set. If the integer fault vectors of the circuit are all 0, then this circuit is a circuit without scan chain faults, and the integer fault vectors and label vectors of the remaining scan chain fault circuits are divided into training sets and verification sets according to the proportion. The training set is used for training the ANN artificial neural network, and the validation set is used for testing the model to obtain the predicted fault scan chain index of each sample and improve the accuracy of model diagnosis.

[0050] (2) Intermittent stuck-at fault injection.

[0051] After obtaining the circuit netlist file after inserting the scan chain, before executing ATPG and VCS simulation, an injection process of intermittent stuck-at faults is added. This process injects intermittent stuck-at faults at the SI end of each scan trigger according to the scan chain structure of the circuit. The traditional random fault injection may cause the probability of fault occurrence to be specified, but the cycle of fault occurrence has a certain regularity. For example, a scan chain composed of ten scan triggers is injected with an intermittent 10% fault. Although the probability of fault occurrence is 10%, with ten patterns as a cycle, the fault always occurs in the first cycle, and the other cycles remain normal. In order to improve this effect, the present invention adds a linear feedback shift register to generate pseudo-random numbers to ensure the randomness of the fault occurrence cycle. By generating fault manifestations at random clock edges.

[0052] It should be noted that the advantage of introducing the diagnostic method for intermittent stuck-at faults is that intermittent faults are random and irregular in actual integrated circuits, and traditional fault diagnosis methods are difficult to efficiently detect such faults. The present invention can cover more potential faults with fewer injection times through the simulation of intermittent faults, greatly improving the diagnostic efficiency. Since intermittent faults are often difficult to reproduce stably, this diagnostic method can more effectively locate these unstable faults, thereby improving the reliability of the system.

[0053] Reference Figure 2 Taking the s208 circuit netlist in the standard test circuit ISCAS'85 as an example, after analyzing its circuit netlist structure, the stuck-at-0 and stuck-at-1 faults are injected into the SI port of each scan chain respectively, and the faulty circuit netlists of different scan triggers are obtained. For example, SFF0_st0.v means that the netlist is the faulty circuit netlist of the SI port of the 0th trigger stuck-at-0. Then, based on the generated faulty circuit netlist, the faulty circuit netlist with the probability of fault occurrence ranging from 0% to 100% randomness is generated, such as SFFn_st0_1%.v means the faulty circuit netlist of the stuck-at-0 fault with the fault probability of 1% of the nth scan trigger, and finally all the faulty circuit netlists are obtained.

[0054] Figure 3 This is a simplified circuit diagram of the S208 circuit netlist after the scan chain is inserted. Figure 3 The functional circuit is shown above, which is the part of the chip or design that implements the actual application logic. The scan trigger close to the scan input port test_si is the 5th scan trigger SFF5, and the scan trigger close to the scan output port test_so is the 0th scan trigger SFF0.

[0055] The D port of the scan trigger is the data input port in the functional mode. The SE port is the control port of the scan trigger, which is used to switch between the functional mode and the test mode. When SE=0, the trigger works in the functional mode and receives data from the D port; when SE=1, the trigger switches to the test mode, receives data through the scan input port test_si, and participates in the operation of the scan chain. The CLK port is the clock input port of the trigger. The CLK signal controls the latching behavior of the trigger and determines when the data is updated.

[0056] like Figure 3 As shown in red font, the intermittent stuck-at-1 fault is injected into the SI port of the 0th scan flip-flop SFF0, and the probability of fault occurrence ranges from 0% to 100%. When a fault occurs, the observed value shifted out from the test_so port is 1.

[0057] (3) Perform ATPG and VCS simulation.

[0058] It should also be noted that the first pattern generated by ATPG is usually in the form of a chain test vector of 00110011... This is to detect whether there is a fault in the scan chain and what the type of fault is. In the simulation log generated by the VCS operation, if the vectors output in the chain test are all 0, it means that a certain scan trigger in the scan chain has a permanent stuck-at-0 fault. Similarly, if the vectors output in the chain test are all 1, it means that a certain scan trigger in the scan chain has a permanent stuck-at-1 fault. When part of 1 becomes 0, or part of 0 becomes 1, it means that there is an intermittent fault in a certain scan trigger in the scan chain. After extracting and preprocessing the data in the simulation log, an integer fault vector is obtained. If the vector is all 0, it means that the circuit is a circuit without a scan chain fault. The remaining data will be organized into a matrix form for generating a data set. The data set is divided into a training set and a verification set according to a certain ratio to ensure that the model can be effectively learned and verified during the training process to improve the accuracy and generalization ability of fault diagnosis.

[0059] Figure 4 It is a simulation log obtained after ATPG and VCS simulation, which records the vector information observed by the test_so port after the fault is injected into the scan chain.

[0060] Figure 5 These are the expected inbound and outbound vector values ​​generated by ATPG.

[0061] Reference Figure 6 ,In order to extract and process the simulation log vector information, for the fault circuit with low fault probability, there will be data with integer fault vectors all being 0, such as Figure 6 The three marked rows have all integer fault vectors (IFVs) that are 0, but correspond to different fault locations in the label vectors (labels). These abnormal data will affect the accuracy of the prediction, so the abnormal data in these three rows should be removed. After filtering out the values ​​of integer fault vectors that are all 0 in the data set, the feature vector used for model training includes the data set of integer fault vectors and label vectors.

[0062] (4) Model training and verification.

[0063] The integer fault vector in the training set is used as the input feature, and the label vector is used as the corresponding output target. The input vector contains the fault information of the circuit under different test modes, and the output label corresponds to the location of the scan chain fault in the circuit. The initial architecture of the artificial neural network model includes an input layer, several hidden layers, and an output layer. The number of nodes in the input layer is equal to the dimension of the integer fault vector, and the number of nodes in the output layer is equal to the number of possible fault locations (the number of scan chain indexes). The structure of the hidden layer is designed according to the actual data complexity, and a fully connected layer is usually used. During the training process, the ANN model transfers the input fault vector to the hidden layer through forward propagation, and performs nonlinear mapping through the activation function. The output layer calculates the probability distribution of each fault location through the Softmax function and predicts the scan chain index where the fault may occur.

[0064] The training uses the cross entropy loss function to evaluate the difference between the prediction result and the actual label (fault location). This loss function can effectively measure the deviation between the fault location predicted by the model and the actual location. The gradient of the loss relative to the parameters of each layer of the model is calculated by the back-propagation algorithm, and the weights and biases of the model are updated using an optimizer (such as Adam or SGD). This process gradually reduces the loss value of the model through multiple iterations, making the model's prediction of the fault location more accurate. The training process usually sets multiple hyperparameters, such as learning rate, batch size, training rounds, etc. As the number of training rounds increases, the prediction accuracy of the model gradually improves, and overfitting is prevented by the early stopping strategy.

[0065] Reference Figure 7 , which are some of the diagnosis results of the model after verification on the verification set. The category index is the fault bit scan trigger index.

[0066] Table 1 shows the diagnostic results of the S208 circuit by the present invention. The test set circuit includes 626 fault circuit simulation results, 610 of which are correctly located, and the prediction accuracy of the present invention is 97.44%; for the S386 circuit, the accuracy of the simulation-based method is 80%; for the S38584 circuit, the accuracy of the deep learning diagnosis method is 83.1%; for the B12 circuit, the diagnosis accuracy based on Tessent diagnostic is 83.7%.

[0067] Table 1 Diagnostic results of S208 circuit

[0068]

[0069] The integrated circuit scan chain diagnostic system based on artificial neural network of the present invention comprises:

[0070] A fault injection unit is used to inject two random stuck at-0 and stuck at-1 faults into each scan trigger in the scan chain of the integrated circuit, wherein a random cycle of the fault is obtained by generating a random number through a linear feedback shift register;

[0071] An automatic test vector generation unit, used to perform automatic test vector generation and obtain a pattern report containing fault information and a corresponding simulation log;

[0072] The diagnostic unit is used to obtain integer fault vectors and label vectors through pattern reports and simulation logs, input the integer fault vectors and label vectors into artificial neural networks for training and verification, and predict the fault locations in the integrated circuit scan chain through the trained artificial neural network.

[0073] Furthermore, after obtaining the integer fault vector and the label vector through the pattern report and the simulation log, the method further includes: deleting the value of the integer fault vector that is all 0.

[0074] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the integrated circuit scan chain diagnosis method based on artificial neural network is implemented.

[0075] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the integrated circuit scan chain diagnosis method based on an artificial neural network is implemented.

[0076] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0077] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. An integrated circuit scan chain diagnosis method based on artificial neural network, characterized in that: The steps include: Injecting random stuck-at-0 and stuck-at-1 faults into each scan trigger in the scan chain of the integrated circuit, wherein a pseudo-random number is generated by a linear feedback shift register to obtain a random period of the fault; Perform automatic test vector generation to obtain a pattern report containing fault information and the corresponding simulation log; The integer fault vector and label vector are obtained through pattern report and simulation log, and the integer fault vector and label vector are input into the artificial neural network for training and verification. The fault position in the integrated circuit scan chain is predicted by the trained artificial neural network. The obtaining of the integer fault vector and the label vector through the pattern report and the simulation log includes: adding the binary fault vector of each pattern bit by bit to obtain the integer fault vector; obtaining the label vector according to the scan trigger bit of the fault injection; The method of obtaining an integer fault vector and a label vector through a pattern report and a simulation log, and inputting the integer fault vector and the label vector into an artificial neural network for training and verification includes: for the input integer fault vector, the artificial neural network generates a corresponding predicted label vector, the scan trigger bit with the highest probability is 1, and the remaining bits are 0, and the prediction accuracy of the artificial neural network is obtained by comparing it with the input label vector.

2. The integrated circuit scan chain diagnosis method based on artificial neural network according to claim 1, characterized in that: After obtaining the integer fault vector and the label vector through the pattern report and the simulation log, the method further includes: deleting the value of the integer fault vector that is all 0.

3. The integrated circuit scan chain diagnosis method based on artificial neural network according to claim 1, characterized in that: The method of injecting two random stuck-at-0 and stuck-at-1 faults into each scan trigger in the integrated circuit scan chain, wherein generating a pseudo-random number through a linear feedback shift register to obtain a random period of the fault includes: generating an intermittent fault with a random intermittent value of 0%-100% according to the random period.

4. The integrated circuit scan chain diagnosis method based on artificial neural network according to claim 1, characterized in that: The loss function of the artificial neural network is a cross entropy function.

5. An artificial neural network based integrated circuit scan chain diagnostic system based on the method of claim 1, characterized in that: include: A fault injection unit is used to inject two random stuck-at-0 and stuck-at-1 faults into each scan trigger in the scan chain of the integrated circuit, wherein a random period of the fault is obtained by generating a pseudo-random number through a linear feedback shift register; An automatic test vector generation unit, used to perform automatic test vector generation and obtain a pattern report containing fault information and a corresponding simulation log; The diagnostic unit is used to obtain integer fault vectors and label vectors through pattern reports and simulation logs, input the integer fault vectors and label vectors into artificial neural networks for training and verification, and predict the fault locations in the integrated circuit scan chain through the trained artificial neural network.

6. The integrated circuit scan chain diagnostic system based on artificial neural network according to claim 5, characterized in that: After obtaining the integer fault vector and the label vector through the pattern report and the simulation log, the method further includes: deleting the value of the integer fault vector that is all 0.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that: When the computer program is loaded into a processor, the artificial neural network-based integrated circuit scan chain diagnosis method according to any one of claims 1 to 4 is implemented.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the artificial neural network-based integrated circuit scan chain diagnosis method according to any one of claims 1 to 4 is implemented.

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