PCB wiring method, device, equipment, medium and product

Abstract

The invention provides a PCB wiring method, device and equipment, a medium and a product, and relates to the technical field of computers, in particular to the field of printed circuit boards and automatic driving. According to the specific implementation scheme, the method comprises the steps of determining a DDR wiring layer used for DDR signal line deployment of the DDR memory, a ground layer used for ground wire deployment and a power supply layer used for power line deployment according to lamination information of the PCB; wherein the lamination information is used for indicating a top layer, a middle layer and a bottom layer of the PCB, and the DDR wiring layer is located in the middle layer; and wiring the DDR signal line, the ground line and the power line according to the DDR wiring layer, the ground layer and the power supply layer.

Description

Technical Field

[0001] The present disclosure relates to the field of printed circuit boards and autonomous driving in the field of computer technology, and in particular to a PCB wiring method, device, equipment, medium and product. Background Art

[0002] With the development of DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) technology, the memory capacity and transmission rate of DDR are getting higher and higher, while its transmission voltage is getting lower and lower. The combination of higher and higher transmission rates and lower and lower transmission voltages makes DDR more susceptible to electromagnetic interference.

[0003] Therefore, how to effectively improve the PCB (Printed Circuit Board) wiring solution of DDR electromagnetic compatibility has become a problem that needs to be solved urgently. Summary of the invention

[0004] The present disclosure provides a PCB wiring method, device, equipment, medium and product.

[0005] According to a first aspect of the present disclosure, a printed circuit board (PCB) wiring method is provided, comprising:

[0006] According to the stacking information of the PCB, a DDR wiring layer for deploying DDR signal lines of the DDR memory, a ground layer for deploying ground lines, and a power layer for deploying power lines are determined; wherein the stacking information is used to indicate a top layer, a middle layer, and a bottom layer of the PCB, and the DDR wiring layer is located in the middle layer;

[0007] The DDR signal line, the ground line and the power line are wired according to the DDR wiring layer, the ground layer and the power layer.

[0008] According to a second aspect of the present disclosure, a PCB wiring device is provided, comprising:

[0009] A wiring layer determination module, which is configured to determine a DDR wiring layer for DDR signal line deployment of a DDR memory, a ground layer for ground line deployment, and a power layer for power line deployment according to stacking information of the PCB; wherein the stacking information is used to indicate a top layer, a middle layer, and a bottom layer of the PCB, and the DDR wiring layer is located in the middle layer;

[0010] A wiring module is configured to wire the DDR signal line, the ground line and the power line according to the DDR wiring layer, the ground layer and the power layer.

[0011] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0012] at least one processor; and

[0013] a memory communicatively connected to the at least one processor; wherein,

[0014] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the PCB wiring method described in any one of the first aspects above.

[0015] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the PCB wiring method provided according to any one of the above-mentioned first aspects.

[0016] According to a fifth aspect of the present disclosure, there is provided a computer program product, comprising a computer program,

[0017] The computer program product includes: a computer program, the computer program is stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program so that the electronic device executes the PCB wiring method described in the first aspect.

[0018] According to a sixth aspect of the present disclosure, a PCB is provided, comprising a top layer, a middle layer and a bottom layer stacked in sequence from top to bottom; wherein:

[0019] The top layer and the top layer are configured as wiring layers for other lines except the DDR signal lines of the DDR memory, and the other lines include at least one of the following: a ground line, a power line, and other signal lines;

[0020] The middle layer is configured as a wiring layer of the DDR signal line.

[0021] According to a seventh aspect of the present disclosure, there is provided an autonomous driving vehicle, comprising a PCB as provided in any one of the first aspects above, wherein a DDR memory and a central processing unit CPU electrically connected to the DDR memory are arranged on the PCB;

[0022] The CPU is configured to store the vehicle processing data in the DDR memory, or read the vehicle processing data from the DDR memory.

[0023] According to the technology disclosed in the present invention, the electromagnetic compatibility performance of the DDR memory is effectively improved.

[0024] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0026] Figure 1 is a possible PCB hardware architecture diagram provided by an embodiment of the present disclosure;

[0027] Figure 2 is a schematic diagram of a possible PCB stackup provided in the related art;

[0028] Figure 3 It is a flow chart of a PCB wiring method provided by an embodiment of the present disclosure;

[0029] Figure 4 It is one of the flow diagrams of another PCB wiring method provided by an embodiment of the present disclosure;

[0030] Figure 5 This is a second flow chart of another PCB wiring method provided by an embodiment of the present disclosure;

[0031] Figure 6 is a schematic diagram of an exemplary PCB stackup provided by an embodiment of the present disclosure;

[0032] Figure 7 is a schematic diagram of the eye diagram quality of channel A in an embodiment of the present disclosure;

[0033] Figure 8 is a schematic diagram of the eye diagram quality of channel B in an embodiment of the present disclosure;

[0034] Fig. 9 is a structural schematic diagram of a PCB wiring device provided by an embodiment of the present disclosure;

[0035] Fig.10 is a structural schematic diagram of a PCB provided by an embodiment of the present disclosure;

[0036] Fig.11 is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0037] Fig.12 is a structural schematic diagram of an autonomous driving vehicle provided by an embodiment of the present disclosure;

[0038] Fig.13 It is a schematic diagram of the structure of an exemplary electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0040] The current domestic automobile consumer market has an increasing desire to experience advanced assisted (automatic) driving functions, which places higher and higher requirements on the advanced assisted (automatic) driving functions of vehicles. Advanced assisted (automatic) driving requires vehicles to be able to perceive and judge the driving environment in real time, and then control and decide the operating status of the vehicle. The processing and calculation of a large amount of environmental perception data makes the vehicle's computing unit have very high requirements for DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) memory capacity and transmission rate.

[0041] At present, SDRAM (Synchronous Dynamic Random-Access Memory) technology has developed to the fifth generation (DDR1~DDR5). Each generation has a significant improvement in transmission rate and transmission bandwidth compared to the previous generation, and its transmission voltage is getting lower and lower. Its transmission rate has increased from the highest 400MT / s in DDR1 to the current highest 7200MT / s in DDR5, while the transmission voltage has dropped from 2.5V to 1.1V. The combination of higher and higher transmission rates and lower transmission voltages makes DDR more and more susceptible to electromagnetic interference.

[0042] To facilitate understanding of the embodiments of the present disclosure, the embodiments of the present disclosure are introduced below in combination with a possible PCB hardware architecture:

[0043] Figure 1 The following is a schematic diagram of the PCB structure. The DDR layout design of the PCB is as follows Figure 1 As shown, it shows a schematic layout diagram of the PCB area where the central processing unit (CPU) and DDR memory particles (the basic storage unit of DDR memory, that is, memory chips) are located. Since the minimum number of PCB stacking in area a where DDR is located (that is, the CPU and SDRAM area, the PCB stacking improvement area) is related to the memory size (that is, the number of memory particles used), the more memory particles there are, the more and denser DDR routing lines are required, and objectively the larger the number of PCB stacking required. Figure 1 The example is a car-grade memory installation (Memory Down) with memory chips in the form of front and back stickers. The size of a single chip is 16Gb, each memory channel is 16GB, and a total of 4 memory channels ChannelA, ChannelB, ChannelC, and ChannelD are used.

[0044] against Figure 1 In the a area where the DDR is located, the related art strictly distinguishes the power (Power) layer, the ground (GND) layer and the signal line layer (including DDR signal line, Peripheral Component Interconnect Express (PCIE) bus (usually used to connect the CPU with the Field-Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), etc.) and Direct Media Interface (DMI) bus (based on the bus form of PCIE, used for data transmission between the CPU and the Platform Controller Hub (PCH)). PCB stacking design such as Figure 2 As shown, taking Layer 14 as an example, where:

[0045] The top layer is the data bus (DDR_DQx), data selection signal (Data Strobes) differential bus (DDR_DQSP / N) of DDR Channel A&B, chip select (Chip Select) signal line and command address (Command Address) signal line, etc.

[0046] Layer 2, 4, 6, 9, 11, and 13 are GND Layers;

[0047] Layer 7 and 8 are Power Layers;

[0048] Layer 3 is part of the Data bus (DDR_DQx) of DDR Channel A&B and C&D, Data Strobes differential bus (DDR_DQSP / N), and Chip Select and Command Address signal lines;

[0049] Layer 10 is the Data bus (DDR_DQx), Data Strobes differential bus (DDR_DQSP / N), and Chip Select and Command Address signal lines of DDR Channel C&D;

[0050] Layer 5 and 12 are the QACA (Quad Addressing Control Assertion) signals of Channel A, B, C, and D. This signal is used to control address access information. The memory particles of each channel need to be interconnected, which usually requires a separate PCB layer.

[0051] The bottom layer is the layer for other signal lines (such as USB lines, etc.).

[0052] Without considering its electromagnetic compatibility performance, combined with the convenience of PCB Layout, the signal integrity of DDR signals and a certain degree of cost considerations, this design can save the number of PCB stacking layers and is a better wiring solution.

[0053] In the PCB stacking design, DDR memory chips are placed on both the top and bottom sides of the PCB to reduce the area of ​​the PCB. However, this layout will increase the density of DDR signal lines in the vertical direction of the PCB. In order to control the number of PCB layers, DDR signal lines are usually routed on the top or bottom layer (i.e. Figure 2 The wiring method shown is the wiring of the Top layer), but because the DDR signal type is a single-ended non-differential line, and because of the higher transmission rate and lower transmission voltage of DDR5, it is difficult for a large-area DDR data bus to meet the automotive-grade anti-interference requirements without additional measures such as separate structural shielding. In addition, the design has been verified and found to be abnormal under high-level radiation anti-interference and electrostatic discharge test conditions, which in turn leads to a series of problems in the system.

[0054] Based on this, the present disclosure provides a PCB wiring method, device, equipment, medium and product, which are applied to the printed circuit board field and the autonomous driving field in the field of computer technology. By adjusting the wiring layer of the DDR signal line to the inner layer, the electromagnetic compatibility performance of the DDR can be improved without significantly reducing the signal integrity of the DDR.

[0055] It should be noted that the embodiments of the present disclosure are mainly aimed at the stacking and routing design of area a, and the main routing of this area mainly involves the power network, GND network, and buses and other signal lines related to the CPU and DDR. The contents described in the subsequent embodiments of the present disclosure are also mainly explained in this area, and the scheme adjustment in this area will not affect the stacking and routing design of other areas of the entire PCB (such as the interface area, power area, and other circuit areas, etc.).

[0056] In addition, the data in this embodiment comes from a public data set, and the data collection, storage, use, processing, transmission, provision and disclosure involved are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0057] In order to enable readers to more deeply understand the implementation principle of the present disclosure, the following Figure 1-Figure 13 The embodiments of the present disclosure are further refined.

[0058] Figure 3 A schematic diagram of a PCB wiring method provided by an embodiment of the present disclosure, such as Figure 3 As shown, the method may be performed by a terminal device and may include the following steps S301 and S302:

[0059] Step S301, according to the stacking information of the PCB, determine the DDR wiring layer for deploying the DDR signal line of the DDR memory, the ground layer for deploying the ground line, and the power layer for deploying the power line; wherein the stacking information is used to indicate the top layer, the middle layer and the bottom layer of the PCB, and the DDR wiring layer is located in the middle layer.

[0060] In this embodiment, the DDR signal lines may include a data bus (DDR_DQx), a data selection signal differential bus (DDR_DQSP / N), a chip select signal (Chip Select) line and a command address (Command Address) signal line, or any one of the above signal lines or other combinations thereof.

[0061] Exemplarily, the terminal device can scan the PCB through a scanning device to obtain the stacking information of the PCB, or the stacking information can be written into the memory of the terminal device. This embodiment is an improvement made to the PCB with a determined number of stacking layers, that is, on the basis of not changing the original number of stacking layers of the PCB, the DDR electromagnetic performance is improved through the wiring method. Among them, the stacking information can include stacking marks for each layer, and the stacking marks are used to facilitate the terminal device to identify different layers of the PCB, such as using a silk screen layer on the top or bottom layer of the PCB to mark the number of layers, component location and other information, or adding marks on the copper foil of each layer, which can be simple text, symbols or graphics, used to distinguish different layers, such as Top Layer, Layer2-Layer13 and Bottom Layer.

[0062] Compared with the related art, the DDR signal line is routed on the Top Layer or Bottom Layer of the PCB, which will result in a large area of ​​the DDR data bus being difficult to meet the automotive-grade anti-interference requirements without additional measures such as separate structural shielding. In this embodiment, the DDR routing layer is determined as the middle layer according to the stacking information of the PCB, so that the DDR signal lines are deployed in the middle layer without direct contact with the outside, and the power layer or ground layer corresponding to the top and bottom layers are used as shielding layers to reduce the electromagnetic radiation of the DDR signal line without adding additional shielding structures, thereby improving the electromagnetic compatibility performance of the DDR signal.

[0063] It can be understood that the DDR wiring layer is used to transmit high-speed data signals, the ground layer is used to provide a stable reference voltage, and the power layer is used to distribute the power supply voltage to ensure that each component can obtain a stable power supply.

[0064] Step S302: routing the DDR signal line, the ground line and the power line according to the DDR routing layer, the ground layer and the power layer.

[0065] In this embodiment, the DDR signal line is deployed to the DDR wiring layer, the ground line is deployed in the ground layer, and the power line is deployed in the power layer, wherein the power layer can be the top layer and the bottom layer, and the bottom layer can be other layers in the middle layer except the DDR signal layer. Optionally, in order to improve the performance and reliability of the PCB, in addition to being deployed in the top layer and the bottom layer, a spare electrophoretic layer can also be designed in the middle layer. It can be understood that the power layer and the spare power layer in this embodiment are only used to describe that the position of the power layer can be in the top layer or in the middle layer respectively, and no special limitation is made on the main and spare relationship of the power layer.

[0066] In this embodiment, the terminal device can perform automatic wiring according to the information of each wiring layer determined above in combination with a wiring tool (such as KiCad, etc.).

[0067] In an optional implementation, the middle layer may deploy DDR signal lines, ground lines, and power lines to further improve the electromagnetic compatibility of DDR. Specifically, the DDR wiring layer is located in the first relevant layer of the middle layer, the ground layer is located in the second relevant layer of the middle layer except the first relevant layer, and the power layer is located in the top layer and the bottom layer. Specifically, the method provided in this embodiment may also include the following steps:

[0068] Determine the second related layer according to the historical stratum wiring information of the PCB, wherein the second related layer includes stacked layers in the middle layer respectively close to the top layer and the bottom layer;

[0069] The stacked layer between every two second-related layers is determined as the first-related layer and / or a backup power layer for power line deployment.

[0070] In this implementation, the top and bottom layers of the PCB are determined as power layers, and the ground layer and the DDR wiring layer are determined in the middle layer. For the design of the ground layer, this embodiment is determined based on the historical ground layer wiring information of the PCB. In other words, the original ground layer design of the PCB is maintained, or the historical ground layer wiring information of the DDR PCB with the same stacking structure is maintained. Figure 2 In the PCB layout shown, Layer 2, 4, 6, 9, 11, and 13 are GND Layers. According to the ground layer wiring information, these layers are determined as the second related layer, that is, the ground layer for deploying the ground line. It is worth noting that the second related layer includes stacked layers close to the top layer and the bottom layer respectively. In this embodiment, the stacked layers close to the power layers corresponding to the top layer and the bottom layer are used as the ground layer. This design makes the power layer and the ground layer close to each other, thereby forming a shielding layer, reducing electromagnetic interference, and helping to further improve electromagnetic compatibility. In addition, by tightly coupling the power layer and the ground layer, a low-impedance power distribution network can be formed to reduce power supply noise and ground bounce noise, thereby improving signal integrity.

[0071] After determining the ground formation, the first relevant layer and the backup power layer for deploying the DDR signal line can be determined based on other stacked layers outside the ground formation, wherein the first relevant layer is the deployment layer for the DDR signal line, and the backup power layer is used to deploy the power supply (by designing a multi-layer power layer, the impedance of the power distribution network can be reduced, the power supply voltage can be ensured to be stable, and the power supply noise and ground bounce noise can be reduced). Optionally, the backup power layer in this embodiment may include two layers, one layer as a wiring layer for the power supply and ground line, and the other layer as a wiring layer for the power supply and DDR signal line, which has been described in detail later and will not be repeated here.

[0072] By determining the stack between each two of the second related layers as the first related layer for deploying the DDR signal line and the backup power layer for power line deployment (which can be used to deploy the DDR signal line), the reference plane of the DDR signal line has two reference grounds, for example Figure 2 The DDR signal lines in the DDR memory are changed from Layer 2 to Layer 2&4, which greatly improves the electromagnetic compatibility of DDR.

[0073] It can be understood that in this embodiment, the stack between every two second-related layers is determined as the first-related layer and / or the backup power supply layer, which means that the stack between every two related layers can be individually determined as the first related layer, or can be separately determined as the first related layer and the backup power supply layer.

[0074] Next, this embodiment takes the determination of the stack between every two second related layers as the first related layer and the backup power layer as an example, and further introduces the determination of the stack between every two second related layers as the first related layer and / or the backup power layer in the above steps:

[0075] According to the historical power layer wiring information of the PCB, a stack between every two of the second related layers is obtained as a stack of the original power layer, and the stack is determined as the backup power layer, wherein the backup power layer includes a first wiring layer for part of the power line and part of the DDR signal line, and a second wiring layer for part of the power line and part of the ground line;

[0076] The stacked layers except the backup power supply layer in the stacked layers between every two of the second related layers are determined as the first related layers.

[0077] In this embodiment, the historical power layer wiring information can be understood in combination with the above-mentioned historical stratum wiring information, and the relevant description will not be repeated. Figure 2 As shown, Layer 7 and Layer 8 are the original power layers. The original power layers are used as backup power layers. Unlike the power layers, a portion of the backup power layers is used as the wiring area for the ground line or the DDR signal line. Specifically, those skilled in the art can divide specific areas (such as sensitive signal areas) in the original power layer into other areas of the power layer in combination with actual applications, and adjust the specific areas to GND, which can reduce the interference of power supply noise and ground bounce noise on the analog signal. The division of the second wiring layer is similar, and the relevant instructions will not be elaborated. In addition, in the design of multi-layer PCBs, since the signal lines may need to be routed across layers, by adjusting the key intersection areas in the power layer to the DDR signal layer, the use of vias can be reduced and the signal transmission path can be optimized.

[0078] Through the above technical solution, by adjusting one layer of the original power layer to the ground layer and the power layer, and adjusting another layer of the original power layer to the DDR signal layer and the power layer, the electromagnetic compatibility performance can be effectively improved without increasing the stacking layer.

[0079] Figure 4 It is a flow chart of another PCB wiring method provided by an embodiment of the present disclosure, which provides a DDR signal line wiring method for a memory channel close to the outer side of a PCB to improve the electromagnetic compatibility performance of the outer memory channel DDR. Specifically, the DDR memory of this embodiment includes a first memory channel and a second memory channel located at the edge of the PCB. In addition to the above steps S301 and S302, this embodiment divides the above step S302 into steps S401 and S402.

[0080] The relevant descriptions of step S301 and step S302 are not repeated here.

[0081] Step S401, acquiring the first stacked layer in the DDR wiring layer in a top-to-bottom order according to the DDR wiring layer;

[0082] Step S402: routing DDR signal lines of the first memory channel and the second memory channel according to the first stack.

[0083] The above embodiment has been introduced. A DDR wiring layer located in the middle layer is determined according to the PCB stack information, wherein the middle layer is usually composed of multiple stacks. Taking the middle layer of 12 stacks as an example, the first stack can be Layer 3, which is the next layer of the ground layer close to the top power layer. The first stack is used to route the DDR signal lines of the outer memory channels A&B (i.e., the first memory channel and the second memory channel). Since the first stack is close to the reference ground and the power layer, a shorter and more direct return path can be provided, which can effectively reduce signal delay and distortion. Moreover, by routing on the first stack, the need for cross-layer routing of signal lines can be reduced, and the use of vias can be reduced, thereby reducing signal reflection and interference.

[0084] It is understandable that since the first memory channel A and the second memory channel B are at the edge of the PCB and closer to the outside of the PCB, their signal lines may be affected by the edge effect, resulting in signal integrity problems such as increased signal reflection and radiation. Since they are close to the edge, the signal lines of channel A and channel B may lack sufficient shielding and are susceptible to external electromagnetic interference. Therefore, it is necessary to pay more attention to the electromagnetic interference problem of the memory channels close to the outside. In this embodiment, by routing channel A and channel B in the first stack, the signal lines can achieve better electromagnetic compatibility performance under the shielding of the power layer and the ground layer.

[0085] In some embodiments, depending on the different designs of the ground layer and the power layer corresponding to the top layer and the bottom layer, the first stacked layer in the DDR wiring layer may also be other layers, such as Layer 2.

[0086] Furthermore, the DDR memory further includes a third memory channel and a fourth memory channel located inside the PCB. The above step S302 routes the DDR signal line, the ground line and the power line according to the DDR routing layer, the ground layer and the power layer. Figure 5 As shown, the following steps may also be included:

[0087] Step S501, obtaining a next stack of the first stack, the next stack belonging to the first related layer, the next stack being used for routing DDR signal lines of the first memory channel and the second memory channel that are not fully deployed in the first stack, and some DDR signal lines of the third memory channel and the fourth memory channel;

[0088] Step S502: acquiring a DDR spare stack according to the historical signal wiring layer information of the PCB, wherein the DDR spare stack is used to route the remaining DDR signal lines of the third memory channel and the fourth memory channel;

[0089] Step S503: routing the DDR signal lines of the first memory channel and the second memory channel that are not deployed in the first stack, and the DDR signal lines of the third memory channel and the fourth memory channel according to the next stack and the DDR backup stack.

[0090] It is understandable that DDR usually contains a large number of signal lines, and a single-layer wiring usually cannot accommodate all of these signal lines, especially in the high-density design of the autonomous driving system scenario. Therefore, in the first stack, usually due to space or other design limitations, all DDR signal lines of the first and second memory channels are not fully deployed. This embodiment continues to deploy these unfinished signal lines in channels A&B in the next stack, and deploys the signal lines of the inner channels C&D. As for the remaining DDR signal lines in channels C&D, they can be deployed in the DDR backup stack, which can be based on historical signal wiring layer information, such as the wiring layer of the current PCB for channels C&D, such as Figure 2 Layer 10 and Layer 12 in.

[0091] Through the above signal line deployment method, the deployment of channel A&B signal lines can be realized, and the signal lines of channel A&B are both located between reference planes (such as ground layers), thereby solving the problem that channel A&B is more susceptible to electromagnetic interference.

[0092] In some embodiments, the DDR signal line further includes an access control signal line for controlling address access information between various channels; the method may further include the following steps:

[0093] The first wiring layer of the backup power layer in the middle layer is determined as the wiring layer of the access control signal line, so as to wire the access control signal line based on the backup power layer.

[0094] Among them, the access control signal line, namely (Quad Addressing Control Assertion, QACA), in this embodiment, is used to manage and control the address access of four independent channels. It plays a key role in the memory access process to ensure that data can be correctly read and written to the specified memory address.

[0095] Since the QACA signal needs to be connected to the memory chip of each channel in order to correctly control the address access. Therefore, in order to ensure the integrity of the QACA signal, this embodiment uses the backup power layer as the wiring layer of the QACA signal line on the PCB. Optionally, this embodiment uses a specific area in the first wiring layer of the backup power layer to route the QACA signal line, and other areas are still used as power layers to route the power lines. It should be noted that the first wiring layer and the second wiring layer of the backup power layer have been introduced above and will not be repeated here.

[0096] Through the above technical solution, the integrity of the QACA signal can be guaranteed without adding stacking layers while improving the EMC performance of DDR.

[0097] In some embodiments, the DDR backup stack can perform routing for the channels C&D as well as routing for the CPU-PCH signal lines and the CPU-FGPA signal lines. The method may further include the following steps:

[0098] The DDR backup stack in the DDR wiring layer is determined as a wiring layer for connecting the CPU-PCH signal line of the central processing unit CPU and the platform controller hub PCH, and for connecting the CPU and the field programmable gate array FGPA CPU-FGPA signal line, so as to route the CPU-PCH signal line and the CPU-FGPA signal line based on the DDR backup stack.

[0099] It is understandable that in the automatic driving system, the CPU-PCH signal line and the CPU-FGPA signal line are indispensable signal lines in the PCB. After the stacking adjustment, this embodiment can complete the wiring of the CPU-PCH signal line and the CPU-FGPA signal line by determining the wiring layer of the CPU-PCH signal line and the CPU-FGPA signal line in the DDR spare stacking layer without adding stacking layers.

[0100] In this way, by routing the CPU-PCH and CPU-FPGA signal lines on the DDR spare stack, the existing PCB layers can be used more efficiently, avoiding waste of stack resources and achieving optimal utilization of resources.

[0101] In some embodiments, the power layer may be used to route other signal lines. The method may further include the following steps:

[0102] The power layer is determined as a wiring layer for other signal lines except the DDR signal line, the CPU-PCH signal line and the CPU-FGPA signal line, so that the other signal lines are wired based on the power layer.

[0103] Among them, other signal lines can be peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe), inter-integrated circuit communication (Inter-Integrated Circuit, I2C) and communication serial bus (Universal Serial Bus, USB), etc.

[0104] In the related art, other signal lines are usually in an independent stacking layer of the PCB, such as Figure 2 The Bottom layer in the circuit is used to route other signal lines. In this embodiment, after the surface layer is designed as the power layer, the number of PCB stacking layers can be optimized by routing other signal lines in the power layer. At the same time, the signal integrity of other signal lines can be improved based on the power layer as a reference plane.

[0105] In some embodiments, in addition to designing the top layer and the bottom layer of the PCB as power layers, the top layer and the bottom layer of the PCB can also be designed as ground layers to improve the electromagnetic compatibility performance of the DDR. Specifically, the DDR wiring layer is located at the first relevant layer of the middle layer, the power layer is located at the second relevant layer of the middle layer except the first relevant layer, and the ground layer is located at the top layer and the bottom layer.

[0106] It should be noted that, compared with the above-mentioned embodiment in which the surface layer (i.e., the top layer and the bottom layer) is designed as a power layer, this embodiment designs the surface layer as a ground layer. Although it can achieve the function of improving the electromagnetic compatibility performance, since the ground layer usually requires a complete plane, that is, different from the signal and power-related routing design, this will likely occupy the wiring space for other functional routings, making it difficult to complete the wiring with the current minimum number of stacks. In other words, if the surface layer is designed as a ground layer, the number of stacks may need to be increased, and if the surface layer is designed as a power layer, the routing of other signal lines can be completed on the surface layer without adding new stacks.

[0107] The technical solution of the present disclosure is described below in conjunction with a specific embodiment:

[0108] To facilitate understanding of this embodiment, continue to combine Figure 2 The PCB stackup design is described in Figure 2 The wiring method shown in the figure has good performance in terms of convenience and signal integrity. However, since the layout network types on each stack are relatively single, there is still room for optimization in terms of layout compactness and space saving. Based on this, the present embodiment found that by making other networks more compact and adjusting the DDR data bus to the inner layer without increasing the total number of stacked layers, the electromagnetic compatibility performance of DDR can be greatly improved without significantly reducing the signal integrity of DDR. Combined with the stacking design of the PCB, such as Figure 6 (against Figure 1 The PCB stack-up improvement shown in area a) is shown in the figure.

[0109] Design the Top and Bottom Layers as power layers. Figure 2 The corresponding part of the power supply in the Layer7 in this area is adjusted to the Top and Bottom layers respectively, and the area after the adjustment of Layer 7 is adjusted to the QACA signal of Channel A&B&C&D;

[0110] Layer 2, 4, 6, 9, 11, and 13 are still used as GND layers;

[0111] Layer 3 is adjusted to the DDR signal lines of DDR Channel A&B, such as the Data bus (DDR_DQx), DataStrobes differential bus (DDR_DQSP / N), and Chip Select and Command Address signal lines;

[0112] Layer 5 is adjusted to part of the Data bus (DDR_DQx) of DDR Channel A&B and C&D, Data Strobes differential bus (DDR_DQSP / N), and Chip Select and Command Address signal lines;

[0113] Layer 7 is adjusted to the QACA (Quad Addressing Control Assertion) signal of Channel A&B&C&D. This signal is used to control address access information. It is necessary to interconnect the memory particles of each channel, so it is used as a separate PCB layer. It should be pointed out that the area of ​​this layer not involved in this solution can still exist as a power layer; wherein, Layer 7 of this embodiment is also the first wiring layer of the backup power layer mentioned above;

[0114] The specific area in Layer 8 is adjusted to GND, and the other areas in this layer still exist as the power layer; wherein, Layer 8 in this embodiment is also the second wiring layer of the backup power layer mentioned above;

[0115] Layer 10 and Layer 12 are used as the routing layers for the C&D signal lines of DDR, as well as the CPU-PCH and CPU-FPGA signal lines; Layer 10 and Layer 12 are also the DDR backup stacking layers;

[0116] The Bottom Layer can be used as a power backup layer for Layer 7 and for the layout of part of the original power network of Layer 7.

[0117] By adjusting the original DDR signal line of the top layer to the inner layer, and changing the signal line type from microstrip line to stripline, the reference plane of the DDR signal line is changed from Layer 2 to Layer 2&4. Since the signal line is changed from the surface layer to the inner layer, the GND layer has a shielding effect, which greatly improves the electromagnetic compatibility of DDR, especially Channel A and B. Take electrostatic discharge as an example, Figure 2 The wiring design can only meet the human body model static electricity of ±4kV, while the human body model static electricity level that the technical solution of the present invention can resist can be greatly improved to ±10kV, and the improvement effect is very obvious.

[0118] In order to verify the effectiveness of the embodiment of the present disclosure, this embodiment takes Channel A and B as an example. Figure 2The signal quality of Channel A and B in the stacking design of the present invention is measured and compared with the signal quality of Channel A and B in the wiring design of the present invention. Figure 7 Shown and Figure 8 As shown, the results are the average values ​​obtained after five measurements of the eye diagram quality of Channel A and B, and the results before and after improvement. The measurement parameters include the minimum voltage value Vmin, maximum voltage value Vmax, minimum time Tmin, and maximum time Tmax of the eye diagram quality of the data bus (Data Queue, DQ) data signal line of DDR under read and write conditions respectively.

[0119] It is understandable that the eye diagram quality is an important tool for evaluating signal quality. The eye diagram forms an "eye-like" figure by superimposing the signal waveforms of multiple bit periods, thereby intuitively showing the quality and transmission performance of the signal. For DDR (double data rate) memory signals, the eye diagram quality is an important indicator for evaluating signal integrity and system performance. The larger the eye (the smaller the minimum voltage, the larger the maximum voltage, the smaller the minimum time, and the larger the maximum time), the better the signal quality. Conversely, the worse.

[0120] from Figure 4 and Figure 5 The comparison of the signal quality measurement results of DDR Channel A and B before and after the PCB stackup improvement is shown. It can be seen that the stackup improvement has little effect on the signal quality of Channel A and B. According to the verification results of PCB electrostatic discharge, the stackup improvement has a significant effect on improving the electrostatic immunity performance during DDR data transmission.

[0121] In addition, it should be noted that the technical solution disclosed in the present invention focuses on ensuring that DDR-related signal lines are designed on non-PCB surface layers (Top or Bottom). The example described in the embodiment of the present invention is only used to illustrate this solution. However, for other PCBs with different numbers of stacked layers and device layouts involving DDR design, they also belong to the scope of the invention of this solution without departing from the design viewpoint of the present invention and will not be limited to the limit values ​​of the examples mentioned in this solution.

[0122] Fig. 9 is a schematic diagram of the structure of a PCB wiring device provided by an embodiment of the present disclosure, such as Fig. 9 As shown, the device includes a wiring layer determination module 901 and a wiring module 902, wherein:

[0123] A wiring layer determination module 901 is configured to determine a DDR wiring layer for DDR signal line deployment of a DDR memory, a ground layer for ground line deployment, and a power layer for power line deployment according to stacking information of the PCB; wherein the stacking information is used to indicate a top layer, a middle layer, and a bottom layer of the PCB, and the DDR wiring layer is located in the middle layer;

[0124] The wiring module 902 is configured to wire the DDR signal line, the ground line and the power line according to the DDR wiring layer, the ground layer and the power layer.

[0125] In an optional implementation, the DDR wiring layer is located at a first relevant layer of the middle layer, the ground layer is located at a second relevant layer in the middle layer except the first relevant layer, and the power layer is located at the top layer and the bottom layer; the device further comprises:

[0126] A first related layer determination module determines the second related layer according to the historical stratum wiring information of the PCB, wherein the second related layer includes stacked layers in the middle layer respectively close to the top layer and the bottom layer;

[0127] The second related layer determination module is configured to determine the stacked layer between every two second related layers as the first related layer and / or a backup power layer for power line deployment.

[0128] In an optional implementation, the second related layer determination module includes:

[0129] A first determining unit is configured to obtain a stack between every two second related layers as an original power layer according to the historical power layer wiring information of the PCB, and determine the stack as the backup power layer, wherein the backup power layer includes a first wiring layer for part of the power line and part of the DDR signal line, and a second wiring layer for part of the power line and part of the ground line;

[0130] The second determining unit is configured to determine the stacked layers, except the backup power supply layer, in the stacked layers between every two of the second related layers as the first related layers.

[0131] In an optional embodiment, the DDR memory includes a first memory channel and a second memory channel located at an edge of the PCB;

[0132] The wiring module 902 includes:

[0133] A first acquisition unit, configured to acquire a first stack in the DDR wiring layer in a top-to-bottom order according to the DDR wiring layer;

[0134] A first wiring unit is configured to wire DDR signal lines of the first memory channel and the second memory channel according to the first stack.

[0135] In an optional implementation, the DDR memory further includes a third memory channel and a fourth memory channel located inside the PCB;

[0136] The wiring module 902 includes:

[0137] a second acquisition unit, configured to acquire a next stack of the first stack, the next stack belonging to the first related layer, the next stack being used for routing of DDR signal lines of the first memory channel and the second memory channel that are not fully deployed in the first stack, and part of DDR signal lines of the third memory channel and the fourth memory channel;

[0138] A third acquisition unit, configured to acquire a DDR spare stack according to historical signal wiring layer information of the PCB, wherein the DDR spare stack is used to route remaining DDR signal lines of the third memory channel and the fourth memory channel;

[0139] The second wiring unit is configured to route the DDR signal lines of the first memory channel and the second memory channel that are not deployed in the first stack, and the DDR signal lines of the third memory channel and the fourth memory channel according to the next stack and the DDR backup stack.

[0140] In an optional implementation, the DDR signal line includes at least one of the following: a data bus, a data selection signal differential bus, a chip selection signal line, and a command address signal line.

[0141] In an optional implementation, the DDR signal line further includes an access control signal line for controlling address access information between channels; the wiring module 902 includes:

[0142] The fourth wiring unit is configured to determine the first wiring layer of the backup power layer in the middle layer as the wiring layer of the access control signal line, so as to wire the access control signal line based on the backup power layer.

[0143] In an optional implementation, the wiring module 902 further includes:

[0144] A fifth wiring unit is configured to determine the DDR backup stack in the DDR wiring layer as a wiring layer for connecting the CPU-PCH signal line of the central processing unit CPU and the platform controller hub PCH, and a wiring layer for connecting the CPU and the field programmable gate array FGPA CPU-FGPA signal line, so as to route the CPU-PCH signal line and the CPU-FGPA signal line based on the DDR backup stack.

[0145] In an optional implementation, the wiring module 902 further includes:

[0146] The sixth wiring unit is configured to determine the power layer as a wiring layer for other signal lines except the DDR signal line, the CPU-PCH signal line and the CPU-FGPA signal line, so as to wire the other signal lines based on the power layer.

[0147] In an optional implementation, the DDR wiring layer is located at a first relevant layer of the middle layer, the power layer is located at a second relevant layer of the middle layer except the first relevant layer, and the ground layer is located at the top layer and the bottom layer.

[0148] The relevant instructions can be understood by referring to the relevant descriptions and effects corresponding to the steps in the embodiment of the method disclosed in the present invention, and no further details will be given here.

[0149] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure, the electronic device may be a terminal device, a processor or a server, such as Fig.10 As shown, the electronic device 100 includes: at least one processor 101; and a memory 101 that is communicatively connected to the at least one processor 102; wherein the memory stores instructions that can be executed by the at least one processor 102, and the instructions are executed by the at least one processor 102 so that the at least one processor 102 can execute the PCB wiring method of the embodiment of the present disclosure.

[0150] The electronic device 100 further includes a receiver 103 and a transmitter 104. The receiver 103 is used to receive instructions and data sent by other devices, and the transmitter 104 is used to send instructions and data to external devices.

[0151] The relevant instructions can be understood by referring to the relevant descriptions and effects corresponding to the steps in the embodiment of the method disclosed in the present invention, and no further details will be given here.

[0152] The embodiment of the present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the PCB wiring method provided by the embodiment of the present disclosure.

[0153] The relevant instructions can be understood by referring to the relevant descriptions and effects corresponding to the steps in the embodiment of the method disclosed in the present invention, and no further details will be given here.

[0154] The embodiments of the present disclosure also provide a computer program product, including a computer program, which is stored in a readable storage medium. At least one processor of an electronic device can read the computer program from the readable storage medium, and at least one processor executes the computer program so that the electronic device executes the PCB wiring method provided in any of the above embodiments.

[0155] The relevant instructions can be understood by referring to the relevant descriptions and effects corresponding to the steps in the embodiment of the method disclosed in the present invention, and no further details will be given here.

[0156] Fig.11 A PCB is provided in an embodiment of the present disclosure, such as Fig.11 As shown, the PCB 110 includes a top layer 111, a middle layer 112 and a bottom layer 113 stacked in order from top to bottom; wherein,

[0157] The top layer 111 and the top layer 113 are configured as wiring layers for other lines except the DDR signal lines of the DDR memory, and the other lines include at least one of the following: a ground line, a power line, and other signal lines;

[0158] The middle layer 112 is configured as a wiring layer for the DDR signal line.

[0159] Fig.12 An automatic driving car provided by an embodiment of the present disclosure, such as Fig.12 As shown, including Fig.11 The PCB 110 provided in the corresponding embodiment has a DDR memory 120 and a central processing unit CPU 130 electrically connected to the DDR memory 120 disposed on the PCB 110;

[0160] The CPU 130 is configured to store the vehicle processing data in the DDR memory 120 , or read the vehicle processing data from the DDR memory 120 .

[0161] Fig.13A schematic block diagram of an exemplary electronic device 1300 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0162] like Fig.13 As shown, the device 1300 includes a computing unit 1301, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1302 or a computer program loaded from a storage unit 1308 into a random access memory (RAM) 1303. In the RAM 803, various programs and data required for the operation of the device 1300 can also be stored. The computing unit 1301, the ROM 802, and the RAM 803 are connected to each other via a bus 1304. An input / output (I / O) interface 805 is also connected to the bus 1304.

[0163] A number of components in the device 1300 are connected to the I / O interface 1305, including: an input unit 1306, such as a keyboard, a mouse, etc.; an output unit 1307, such as various types of displays, speakers, etc.; a storage unit 1308, such as a disk, an optical disk, etc.; and a communication unit 1309, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1309 allows the device 1300 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0164] The computing unit 1301 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1301 performs the PCB wiring method and processing described above, such as the wiring method of the method PCB. For example, in some embodiments, the PCB wiring method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1308. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1300 via the ROM 802 and / or the communication unit 1309. When the computer program is loaded into the RAM 803 and executed by the computing unit 1301, one or more steps of the PCB wiring method described above may be performed. Alternatively, in other embodiments, the computing unit 1301 may be configured to perform the PCB wiring method in any other appropriate manner (e.g., by means of firmware).

[0165] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0166] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0167] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0168] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0169] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0170] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services ("Virtual Private Server", or "VPS" for short). The server may also be a server of a distributed system, or a server combined with a blockchain.

[0171] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0172] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A printed circuit board (PCB) wiring method, comprising: According to the stacking information of the PCB, a DDR wiring layer for deploying DDR signal lines of the DDR memory, a ground layer for deploying ground lines, and a power layer for deploying power lines are determined; wherein the stacking information is used to indicate a top layer, a middle layer, and a bottom layer of the PCB, and the DDR wiring layer is located in the middle layer; The DDR signal line, the ground line and the power line are wired according to the DDR wiring layer, the ground layer and the power layer.

2. The method according to claim 1, wherein: The DDR wiring layer is located at the first relevant layer of the middle layer, the ground layer is located at the second relevant layer of the middle layer except the first relevant layer, and the power layer is located at the top layer and the bottom layer; the method further includes: Determine the second related layer according to the historical stratum wiring information of the PCB, wherein the second related layer includes stacked layers in the middle layer respectively close to the top layer and the bottom layer; The stacked layer between every two second-related layers is determined as the first-related layer and / or a backup power layer for power line deployment.

3. The method according to claim 2, wherein: The step of determining the stacked layer between every two second related layers as the first related layer and / or the backup power supply layer comprises: According to the historical power layer wiring information of the PCB, a stack between every two of the second related layers is obtained as a stack of the original power layer, and the stack is determined as the backup power layer, wherein the backup power layer includes a first wiring layer for part of the power line and part of the DDR signal line, and a second wiring layer for part of the power line and part of the ground line; The stacked layers except the backup power supply layer in the stacked layers between every two of the second related layers are determined as the first related layers.

4. The method according to any one of claims 1 to 3, wherein: The DDR memory includes a first memory channel and a second memory channel located at an edge of the PCB; The step of wiring the DDR signal line, the ground line and the power line according to the DDR wiring layer, the ground layer and the power layer comprises: According to the DDR wiring layers, in order from top to bottom, obtaining a first stack in the DDR wiring layers; According to the first stack, DDR signal lines of the first memory channel and the second memory channel are routed.

5. The method according to claim 4, wherein: The DDR memory further includes a third memory channel and a fourth memory channel located inside the PCB; The step of wiring the DDR signal line, the ground line and the power line according to the DDR wiring layer, the ground layer and the power layer comprises: Acquire a next stack of the first stack, the next stack belonging to the first related layer, the next stack being used for routing DDR signal lines of the first memory channel and the second memory channel that are not fully deployed in the first stack, and some DDR signal lines of the third memory channel and the fourth memory channel; Acquire a DDR spare stack according to the historical signal wiring layer information of the PCB, wherein the DDR spare stack is used to wire the remaining DDR signal lines of the third memory channel and the fourth memory channel; According to the next stack and the DDR standby stack, the DDR signal lines of the first memory channel and the second memory channel that are not deployed in the first stack, and the DDR signal lines of the third memory channel and the fourth memory channel are routed.

6. The method according to any one of claims 1 to 5, wherein: The DDR signal line includes at least one of the following: a data bus, a data selection signal differential bus, a chip selection signal line and a command address signal line.

7. The method according to claim 6, wherein the DDR signal line further comprises an access control signal line for controlling address access information between channels; the method further comprises: The first wiring layer of the backup power layer in the middle layer is determined as the wiring layer of the access control signal line, so as to wire the access control signal line based on the backup power layer.

8. The method according to any one of claims 1 to 5, further comprising: The DDR backup stack in the DDR wiring layer is determined as a wiring layer for connecting the CPU-PCH signal line of the central processing unit CPU and the platform controller hub PCH, and for connecting the CPU and the field programmable gate array FGPA CPU-FGPA signal line, so as to route the CPU-PCH signal line and the CPU-FGPA signal line based on the DDR backup stack.

9. The method according to claim 8, further comprising: The power layer is determined as a wiring layer for other signal lines except the DDR signal line, the CPU-PCH signal line and the CPU-FGPA signal line, so that the other signal lines are wired based on the power layer.

10. The method according to any one of claims 1 to 5, wherein: The DDR wiring layer is located at a first relevant layer of the middle layer, the power layer is located at a second relevant layer of the middle layer except the first relevant layer, and the ground layer is located at the top layer and the bottom layer.

11. A PCB wiring device, comprising: A wiring layer determination module, which is configured to determine a DDR wiring layer for DDR signal line deployment of a DDR memory, a ground layer for ground line deployment, and a power layer for power line deployment according to stacking information of the PCB; wherein the stacking information is used to indicate a top layer, a middle layer, and a bottom layer of the PCB, and the DDR wiring layer is located in the middle layer; A wiring module is configured to wire the DDR signal line, the ground line and the power line according to the DDR wiring layer, the ground layer and the power layer.

12. The device according to claim 11, wherein the DDR wiring layer is located at a first relevant layer of the middle layer, the ground layer is located at a second relevant layer of the middle layer except the first relevant layer, and the power layer is located at the top layer and the bottom layer; the device further comprises: A first related layer determination module determines the second related layer according to the historical stratum wiring information of the PCB, wherein the second related layer includes stacked layers in the middle layer respectively close to the top layer and the bottom layer; The second related layer determination module is configured to determine the stacked layer between every two second related layers as the first related layer and / or a backup power layer for power line deployment.

13. The device according to claim 12, wherein: The second related layer determination module includes: A first determining unit is configured to obtain a stack between every two second related layers as an original power layer according to the historical power layer wiring information of the PCB, and determine the stack as the backup power layer, wherein the backup power layer includes a first wiring layer for part of the power line and part of the DDR signal line, and a second wiring layer for part of the power line and part of the ground line; The second determining unit is configured to determine the stacked layers, except the backup power supply layer, in the stacked layers between every two of the second related layers as the first related layers.

14. The device according to any one of claims 11 to 13, wherein: The DDR memory includes a first memory channel and a second memory channel located at an edge of the PCB; The wiring module comprises: A first acquisition unit, configured to acquire a first stack in the DDR wiring layer in a top-to-bottom order according to the DDR wiring layer, wherein the first stack is used for wiring of DDR signal lines of the first memory channel and the second memory channel; A first wiring unit is configured to wire DDR signal lines of the first memory channel and the second memory channel according to the first stack.

15. The device according to claim 14, wherein: The DDR memory further includes a third memory channel and a fourth memory channel located inside the PCB; The wiring module comprises: a second acquisition unit, configured to acquire a next stack of the first stack, the next stack belonging to the first related layer, the next stack being used for routing of DDR signal lines of the first memory channel and the second memory channel that are not fully deployed in the first stack, and part of DDR signal lines of the third memory channel and the fourth memory channel; A third acquisition unit, configured to acquire a DDR spare stack according to historical signal wiring layer information of the PCB, wherein the DDR spare stack is used to route remaining DDR signal lines of the third memory channel and the fourth memory channel; The second wiring unit is configured to route the DDR signal lines of the first memory channel and the second memory channel that are not deployed in the first stack, and the DDR signal lines of the third memory channel and the fourth memory channel according to the next stack and the DDR backup stack.

16. The device according to any one of claims 11 to 15, wherein: The DDR signal line includes at least one of the following: a data bus, a data selection signal differential bus, a chip selection signal line and a command address signal line.

17. The device according to claim 16, wherein the DDR signal line further comprises an access control signal line for controlling address access information between various channels; and the wiring module comprises: The fourth wiring unit is configured to determine the first wiring layer of the backup power layer in the middle layer as the wiring layer of the access control signal line, so as to wire the access control signal line based on the backup power layer.

18. The device according to any one of claims 11 to 15, wherein the wiring module further comprises: A fifth wiring unit is configured to determine the DDR backup stack in the DDR wiring layer as a wiring layer for connecting the CPU-PCH signal line of the central processing unit CPU and the platform controller hub PCH, and a wiring layer for connecting the CPU and the field programmable gate array FGPA CPU-FGPA signal line, so as to route the CPU-PCH signal line and the CPU-FGPA signal line based on the DDR backup stack.

19. The apparatus according to claim 18, wherein the wiring module further comprises: The sixth wiring unit is configured to determine the power layer as a wiring layer for other signal lines except the DDR signal line, the CPU-PCH signal line and the CPU-FGPA signal line, so as to wire the other signal lines based on the power layer.

20. The device according to any one of claims 11 to 15, wherein: The DDR wiring layer is located at a first relevant layer of the middle layer, the power layer is located at a second relevant layer of the middle layer except the first relevant layer, and the ground layer is located at the top layer and the bottom layer.

21. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the PCB wiring method according to any one of claims 1 to 10.

22. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to enable the computer to execute the PCB wiring method according to any one of claims 1-10.

23. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the PCB wiring method according to any one of claims 1 to 8 is implemented.

24. A PCB, comprising a top layer, a middle layer and a bottom layer stacked in order from top to bottom; wherein: The top layer and the top layer are configured as wiring layers for other lines except the DDR signal lines of the DDR memory, and the other lines include at least one of the following: a ground line, a power line, and other signal lines; The middle layer is configured as a wiring layer of the DDR signal line.

25. An automatic driving car, comprising the PCB as claimed in claim 11, wherein a DDR memory and a central processing unit CPU electrically connected to the DDR memory are arranged on the PCB; The CPU is configured to store the vehicle processing data into the DDR memory, or The vehicle processing data is read from the DDR memory.

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