Clock frequency test method, circuit, medium and equipment

Abstract

The invention discloses a clock frequency test method, circuit, medium and equipment, and the method comprises the steps: carrying out the frequency division processing of a to-be-tested clock signal and a reference clock signal according to the to-be-tested clock signal, an input frequency division coefficient A value and an input frequency division coefficient B value, and obtaining the to-be-tested clock signal after frequency division and the reference clock signal after frequency division; performing rising edge counting on the to-be-measured clock signal after frequency division from zero to obtain a count value A, and performing rising edge counting on the reference clock signal after frequency division to obtain a count value B; the count value A is converted into a Gray code, and after synchronization, the Gray code is converted into a standard binary code A '; processing the count value B to obtain a count value B ', taking the standard binary code A' and the count value B 'as a group of synchronizing signals in a reference clock domain, comparing the values of the synchronizing signals A' and B 'at the rising edge of each reference clock in the clock domain of the reference clock signal, and outputting a corresponding high level or low level according to the frequency of the clock to be measured and the calibration value.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit testing, and in particular relates to a clock frequency testing method, circuit, medium and equipment. Background Art

[0002] During the communication process of the system on chip, the stability of the system is very high. The clock is a crucial signal in the initialization and normal working process of the entire system. Once the input clock frequency is abnormal, the entire system may not operate normally. Therefore, it is necessary to perform frequency inspection on the input clock of the system.

[0003] At present, the commonly used clock frequency test methods are mostly implemented by counters. The number of flips of the clock to be tested starts from zero and is reset to zero when the count reaches a certain threshold. If the number of flips of the clock to be tested is detected to be a fixed value within a certain reference clock flip cycle, the frequency of the clock to be tested is determined to be correct. If the number of flips of the clock to be tested is greater than or less than the fixed value, the frequency of the clock to be tested is determined to be wrong.

[0004] Considering that the clock to be tested and the reference clock are not synchronized, there is a clock skew between them and the phase skew changes with time, making the phase relationship between the clock to be tested and the reference clock unknown. At the same time, both the clock to be tested and the reference clock have clock jitter, so blindly counting cannot obtain accurate detection results. At the same time, the detection time of the above method is uncertain. If the detection time is too short, the frequency anomaly of the clock to be tested cannot be detected; if the detection time is too long, the system power consumption will increase and may affect the subsequent operation of the system, such as clock repair or other functions. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a clock frequency verification method, circuit, medium and equipment in view of the deficiencies in the above-mentioned prior art, which is used to solve the technical problems in the prior art that the phase difference between the clock to be measured and the reference clock is unknown, and both the clock to be measured and the reference clock have clock jitter and cannot accurately detect whether the frequency of the clock to be measured is a calibrated value, and the detection accuracy cannot be controlled.

[0006] The present invention adopts the following technical solutions: A clock frequency testing method comprises the following steps: S1. According to the clock signal to be measured and the input frequency division coefficient A and frequency division coefficient B, the clock signal to be measured and the reference clock signal are frequency divided to obtain the clock signal to be measured and the reference clock signal after frequency division; S2, counting the rising edges of the divided clock signal to be measured from zero to obtain a count value A, and at the same time counting the rising edges of the divided reference clock signal to obtain a count value B; S3, converting the count value A into Gray code, and then converting the Gray code into standard binary code A' after synchronization; processing the count value B to obtain count value B', and using the standard binary code A' and count value B' as a set of synchronization signals in the reference clock domain; S4. In the clock domain of the reference clock signal, at each rising edge of the reference clock, the values ​​of the synchronization signals A' and B' are compared, and a corresponding high level or low level is output according to the clock frequency to be measured and the calibration value.

[0007] Preferably, in step S3, a reference clock signal is used to perform two-level synchronization, and after synchronization, the Gray code is converted into a standard binary code A'; the count value B is delayed by two beats to obtain the count value B'.

[0008] Preferably, in step S4, when the counting time reaches the detection window size, the value of the difference is checked. If the value is not equal to any value among +1, -1, and 0, it is determined that the frequency of the clock to be measured does not match the calibration value, and a high level is output; otherwise, it is determined that the frequency of the clock to be measured matches the calibration value, and a low level is output.

[0009] Preferably, when the value of the synchronization signal A' or B' changes and A'≠B', the difference is incremented, and if the synchronization signal A'=B', the difference is decremented.

[0010] Preferably, the detection window is calculated as follows:

[0011] in, is the clock cycle to be measured, is the maximum frequency error of the clock to be tested that needs to be detected.

[0012] Another technical solution of the present invention is a clock frequency detection circuit, which utilizes the clock frequency detection method, including a frequency divider A and a frequency divider B; the clock signal to be measured and the reference clock signal enter the frequency divider A and the frequency divider B respectively for frequency division operation, the clock signal to be measured after frequency division enters the counter A, and then outputs the count value of the clock to be measured to enter the synchronizer A, the synchronizer A outputs the synchronized count value A' of the clock to be measured, and inputs this count value A' to the comparator; for the reference clock signal, the frequency divider B outputs the divided reference clock to the counter B and outputs the count value B, the count value B' obtained after synchronization of the synchronizer B is input to the comparator, and the output of the comparator is used as the detection result.

[0013] Preferably, the input end of the frequency divider A is connected to the clock signal to be measured and the frequency division coefficient A, the output end of the frequency divider A is connected to the input end of the counter A; the output end of the counter A is connected to the input end of the synchronizer A; The input end of the frequency divider B is connected to the reference clock signal and the frequency division coefficient B, the output end of the frequency divider B is connected to the input end of the counter B; the output end of the counter B is connected to the input end of the synchronizer B.

[0014] Preferably, each synchronizer contains two levels of registers, the clocks of synchronizer A and synchronizer B are both derived from the reference clock signal, the data input end of synchronizer A is connected to the output end of counter A, and the data input end of synchronizer B is connected to the output end of counter B; the output ends of synchronizer A and synchronizer B are both connected to the input end of the comparator.

[0015] In a third aspect, a computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned clock frequency verification method when executing the computer program.

[0016] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, including a computer program, which implements the steps of the above-mentioned clock frequency verification method when executed by a processor.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: A clock frequency inspection method is provided, which reduces the frequency of the clock signal to a range suitable for subsequent processing by performing frequency division processing on a clock signal to be tested and a reference clock signal; the divided signal can effectively reduce the load of the counter, improve the counting accuracy, and reduce the influence of the high-frequency clock signal on the system stability and circuit performance; by frequency division, the sampling error problem that may be caused by directly processing the high-frequency clock signal is avoided, and the synchronization and stability of subsequent counting and comparison are guaranteed; at the same time, by setting appropriate frequency division coefficients A and B, the inspection range can be flexibly adjusted to enhance the adaptability of the system; on the basis of the frequency division processing, the counting values ​​A and B are obtained by counting the rising edges, which reflect the relative frequency characteristics of the clock signal to be tested and the reference clock signal in the same time, which is a key step in quantitatively measuring the frequency of the clock signal; this counting method uses the rising edge of the clock signal for counting, and compared with the traditional time measurement method, the counting accuracy is higher and the implementation is simpler; the counting value directly reflects the frequency information of the clock signal , which simplifies the inspection process of clock frequency and reduces the probability of misjudgment caused by frequency fluctuation; Step S3 converts the count value A into Gray code and performs synchronization processing, and then converts it back to standard binary code to avoid the metastability problem of the count value during the synchronization process; Gray code has only one bit difference between adjacent numbers, which reduces the probability of error during state conversion, and is particularly suitable for synchronous transmission between asynchronous clock domains; Through Gray code conversion, the data error caused by metastability during clock domain synchronization is significantly reduced; After synchronization processing, Gray code is converted to standard binary code A', which ensures the accurate transmission of the count value; The overall steps improve the robustness of the inspection method and enhance the reliability of clock frequency inspection; In the clock domain of the reference clock, step S4 determines whether the clock frequency to be tested meets the expectations by comparing the values ​​of synchronization signals A' and B'; Using the reference clock as a reference, the counting results are compared one by one, and a high or low level signal is output to indicate the relative deviation of the frequency. A direct comparison between the clock frequency to be tested and the calibration value is realized, which is simple and intuitive. A frequency determination is performed on each rising edge of the reference clock, which improves the real-time and accuracy of the test method. At the same time, a level signal is output as the test result to facilitate subsequent signal processing and judgment.

[0018] Furthermore, by using the reference clock signal for two-level synchronization, the stability and data consistency of the count value when it is transmitted between asynchronous clock domains are further guaranteed. The two-level synchronization effectively reduces the impact of glitches and jitters on the count value during high-frequency conversion. At the same time, delaying the count value B by two beats can make the B value more aligned with A' during the comparison process, eliminating delay errors. This method can enhance the accuracy of data synchronization and improve the accuracy of count value transmission; align the count value to make the comparison operation more accurate, which helps to improve the accuracy of frequency verification; it can also reduce system errors and improve the reliability of the overall clock frequency verification.

[0019] Furthermore, by comparing the difference when the counting time reaches the detection window size, the matching of the clock frequency to be measured and the calibration value can be determined. The size of the detection window is set to accumulate the count value within a certain time range, so as to accurately determine the error range of the clock frequency. By checking whether the difference is +1, -1 or 0, the slight deviation between the clock frequency to be measured and the reference clock can be effectively evaluated. By controlling the difference within the range of ±1, instantaneous misjudgment caused by clock jitter or occasional counting errors can be eliminated. This error judgment method is suitable for occasions where high-precision clock frequencies are detected, while maintaining the sensitivity of the test and being able to quickly respond to obvious frequency deviations. When the difference exceeds the range of ±1, the output of a high-level signal indicates that the frequency does not match, and vice versa, the output of a low-level signal indicates that the frequency matches. The output of high-level and low-level signals simplifies the judgment logic of the system, which is convenient for circuit integration and subsequent processing.

[0020] Furthermore, by refining the dynamic adjustment mechanism of the difference, the difference is increased or decreased according to the changes in the synchronization signals A' and B', thereby achieving real-time tracking and correction of the frequency deviation. When the synchronization signal A' or B' changes, the difference is adjusted in real time by judging whether A' and B' are equal. When A'≠B', the difference is incremented, indicating that there is a deviation between the clock frequency to be measured and the reference frequency; when A'=B', the difference is decremented to gradually correct or offset the previously accumulated error. This setting allows the system to track the frequency deviation in detail and ensure the dynamics and continuity of frequency detection.

[0021] A clock frequency detection circuit, wherein frequency dividers A and B are used to perform frequency division processing on a clock signal to be tested and a reference clock signal respectively, so as to reduce the clock frequency to a range suitable for counting. By frequency division of the signal, the interference of high-frequency signals can be effectively reduced and the processing capacity of the counter can be matched; counter A is used to count the rising edges of the clock signal to be tested after frequency division, and counter B is used to count the rising edges of the reference clock signal after frequency division. The function of the counter is to convert the frequency of the clock signal into a quantifiable count value to provide basic data for subsequent comparison. The characteristics of the clock frequency are converted into an easy-to-process digital form to facilitate high-precision frequency detection; synchronizers A and B are used to synchronize the count values ​​output by the counter to ensure that these count values ​​have been correctly transmitted to the comparator at the comparison moment. The design of the synchronizer can alleviate the synchronization problem between different clock domains and avoid the metastable state of the data. Through the synchronization processing of the synchronizer, the count value errors caused by the inconsistency between the clock domains are avoided, and the reliability of the system is improved. It reduces the synchronization delay and metastable problems that may occur during data transmission, ensuring the accuracy of the comparison results; the comparator is used to compare the synchronized count values ​​A' and B', and output a high or low level signal as the detection result according to the comparison result. Directly compare the count values ​​to determine the matching of the clock frequency to be measured with the reference frequency, provide real-time level signal output, facilitate subsequent circuit processing and external judgment, simplify the logic of frequency detection, and achieve fast and stable frequency testing; overall, the test circuit realizes efficient and accurate clock frequency detection through the organic combination of frequency division, counting, synchronization and comparison steps. Compared with the traditional frequency detection method, this circuit has a clear structure, reliable performance, and strong real-time performance. It is a very effective hardware implementation solution.

[0022] Furthermore, the two-level register setting is to further enhance the data synchronization capability of the synchronizer between asynchronous clock domains. The two-level synchronization can effectively reduce the probability of metastable data during transmission during single-level synchronization and improve the reliability of data transmission; the use of the reference clock as the synchronization clock can ensure that all synchronization operations are performed in the same clock domain, thereby ensuring the consistency and correctness of the synchronization data. This circuit can ensure synchronization consistency. By performing data synchronization under a unified reference clock, it can ensure that the operations of synchronizers A and B remain consistent, avoiding phase differences and synchronization errors caused by different synchronization clocks.

[0023] In summary, the present invention has significant advantages in frequency detection accuracy, real-time response, anti-interference ability, data synchronization accuracy, scope of application and implementation cost, and is an efficient and reliable clock frequency detection method and circuit implementation solution.

[0024] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a functional block diagram of a clock detection circuit of the present invention; Figure 2 It is the timing diagram of clock signal; Figure 3 A schematic diagram of a computer device provided by an embodiment of the present invention; Figure 4 The present invention is a block diagram of an electronic device provided according to an embodiment. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0029] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0030] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0031] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0032] The present invention provides a clock frequency testing method, circuit, medium and device, which have significant differences and advantages over the prior art: 1) Use the frequency division counting method to test the clock frequency Most clock frequency verification methods in the prior art are based on direct frequency measurement or counting comparison methods, while the present invention performs frequency division processing on the clock signal to be tested and the reference clock signal, and then performs rising edge counting. The frequency division operation converts the high-frequency signal into a low-frequency signal, which improves the stability and accuracy of the frequency verification; by adjusting the frequency division coefficient, the verification method of the present invention can be applied to a wider frequency range and adapt to different application scenarios.

[0033] 2) Judgment mechanism for dynamic adjustment of difference The present invention introduces a dynamic adjustment mechanism for the synchronization signal difference in the frequency test process, and ensures that the difference between the count values ​​A' and B' is controlled within the range of ±1 by increasing or decreasing the difference in real time. This dynamic difference adjustment mechanism can effectively deal with small-scale jitter and frequency drift, reduce misjudgment, and improve the robustness of the system; through real-time difference adjustment, the present invention can accurately determine the matching degree between the clock frequency to be tested and the reference frequency, avoid error accumulation, and improve the reliability of the detection result.

[0034] 3) Determination of high and low level output results The present invention uses simple and intuitive high-level and low-level signals to output the detection results, which is more direct and easy to use compared to complex numerical output or display. The intuitive level signal is convenient for subsequent circuit processing, reduces the demand for complex control logic, and is suitable for embedded and automated detection environments; the rapid switching of high and low levels can reflect the matching status of the clock frequency in real time and provide instant feedback.

[0035] See also Figure 1 The present invention provides a clock frequency detection circuit, comprising a frequency divider A, a frequency divider B, a synchronizer A, a synchronizer B, a counter A, a counter B and a comparator; a clock signal to be detected enters the comparator via the frequency divider A and the synchronizer A in sequence, a reference clock signal is divided into three paths, one path enters the comparator via the frequency divider B and the synchronizer B in sequence, a second path and a third path enter the comparator via the synchronizer A and the synchronizer B respectively, and the comparator outputs the detection result.

[0036] Frequency divider A is a frequency divider for the clock to be tested, and is used to access the clock signal to be tested; Frequency divider B is a frequency divider for reference clock, and is used to access reference clock signal.

[0037] Counter A is a counter for the clock to be tested, and is used to access the clock to be tested after frequency division; Counter B is a reference clock counter, which is used to access the divided reference clock.

[0038] Among them, the reference clock is the crystal oscillator clock.

[0039] The clock signal to be measured and the reference clock signal enter the frequency divider A and the frequency divider B respectively for frequency division operation. The divided clock signal to be measured enters the counter A. The counter A outputs the count value of the clock to be measured and enters the synchronizer A. The synchronizer A outputs the synchronized count value A' of the clock to be measured, and the count value A' is input to the comparator. For the reference clock signal, the frequency divider B outputs the divided reference clock to the counter B and outputs the count value B, and then sends the count value B to the synchronizer B. The synchronized count value B' is input to the comparator, and the output of the comparator is the detection result.

[0040] The connection relationship of the clock frequency detection circuit of the present invention is as follows: The input end of the frequency divider A is connected to the clock signal to be measured and the frequency division coefficient A, the output end of the frequency divider A is connected to the input end of the counter A; the output end of the counter A is connected to the input end of the synchronizer A; The input end of the frequency divider B is connected to the reference clock signal and the frequency division coefficient B, the output end of the frequency divider B is connected to the input end of the counter B; the output end of the counter B is connected to the input end of the synchronizer B.

[0041] Each synchronizer contains two levels of registers. The clocks of synchronizer A and synchronizer B are both derived from the reference clock signal. The data input of synchronizer A is connected to the output of counter A, and the data input of synchronizer B is connected to the output of counter B. The outputs of synchronizer A and synchronizer B are both connected to the input of the comparator.

[0042] The working principle of a clock frequency detection circuit of the present invention is as follows: Use frequency dividers, counters, and synchronizers to complete the detection of the correctness of the frequency of the clock to be tested. For the clock to be tested, its frequency calibration value is known, and the frequency division coefficient A and frequency division coefficient B are obtained based on the greatest common divisor of the calibration value and the reference clock frequency. For example, if the frequency of the clock to be tested is 20MHz and the reference clock frequency is 50MHz, then the frequency division coefficient A is 4 and the frequency division coefficient B is 10; If the real frequency of the clock to be measured is indeed its frequency calibration value, the divided clock to be measured and the divided reference clock are a group of signals with the same frequency but different phases. Therefore, within the same time range, the number of flips of the divided clock to be measured and the divided reference clock should be the same value. Input the divided clock to be measured and the divided reference clock into the counter, count the rising edges of the divided clock to be measured and the divided reference clock respectively, and synchronize the count value to the reference clock domain; Then, within the detection window, the difference between the two counts is the basis for determining whether the frequency of the clock to be measured is the calibrated value.

[0043] Considering that there is a certain delay when beating across clock domains, there may be a single missed acquisition during the synchronization process using Gray code, so the difference between the two counts is 0 or When the frequency of the clock to be measured is different from the calibration value, the counting difference will increase with the increase of the detection time. Therefore, this limitation will not cause detection errors.

[0044] At the same time, changing the size of the detection window can achieve the purpose of controlling the detection accuracy.

[0045] The calculation formula of the detection window of the clock frequency detection circuit of the present invention is: (1) in, is the clock cycle to be measured, is the maximum frequency error of the clock to be tested that needs to be detected.

[0046] The data flow when a clock frequency checking circuit of the present invention is executed is: S1, input the clock to be tested and the reference clock, and divide the clock to be tested and the reference clock according to the clock to be tested and the input frequency division coefficient A and frequency division coefficient B values ​​to obtain the divided clock to be tested and the divided reference clock; See also Figure 2 , the clock to be measured after frequency division in the figure, the current frequency division coefficient A is 6; Figure 2 The reference clock after medium frequency division, the current frequency division factor B is 4.

[0047] S2, the divided clock to be measured output by the frequency divider A is sent to the counter A, and the rising edge count is performed from zero to obtain the count value A, that is, the count value A is incremented every time the rising edge of the divided clock to be measured is sampled, and at the same time, the divided reference clock output by the frequency divider B is sent to the counter B to count the rising edge to obtain the count value B; See also Figure 2In the figure, the divided clock to be tested flips at T6, T588, T594, and T600, and the count value B performs a self-increment operation at the above moments; S3, convert the count value A into Gray code and input it into synchronizer A for two-level synchronization using the reference clock. After synchronization, the Gray code is converted into standard binary code A'. In order to synchronize the count of the clock to be tested with the reference clock, the count value B also needs to be input into synchronizer B for two-beat delay processing to obtain the count value B'. In this way, A' and B' are a set of synchronization signals in the reference clock domain; See also Figure 2 , the clock count to be measured after synchronization in the figure, at time T6, the count value A increases from 0 to 1, and then passes through the synchronizer A to obtain the count value A', which is sampled by the reference clock at time T12; similarly, the count value B increases from 0 to 1 at time T6, and after two levels of delay, the count value B' is obtained, which is sampled by the reference clock at time T12; S4. Input A' and B' into the comparator. In the clock domain of the reference clock, at each rising edge of the reference clock, compare the values ​​of A' and B' to see if they have changed. If the value of A' or B' has changed and A'≠B', the difference is incremented. If A'=B', the difference is decremented (provided that the difference is not zero). When the counting time reaches the detection window size, check the value of the difference. If its value is not equal to any of +1, -1, 0, it is determined that the frequency of the clock to be measured does not match the calibration value, and a high level is output; otherwise, it is determined that the frequency of the clock to be measured matches the calibration value, and a low level is output.

[0048] See also Figure 2 , the current detection window size is 100, and when the delayed reference clock count reaches 100, the difference check is performed. At this time, the difference in the figure is 0, and it is determined that the clock frequency to be measured is consistent with the calibration value, and a low level is output.

[0049] It should be noted that Figure 2 At T591, the value of A' changes from 98 to 99. This is because when Gray code is sampled, a missed sample may occur. However, this situation only lasts for one beat at most. That is, the next time the count value A is sampled, that is, at T591, the correct counter value 99 can be sampled. This is the difference equal to This is also considered to be the reason why the clock frequency to be measured is consistent with the calibrated value.

[0050] In another embodiment of the present invention, a terminal device is provided, the terminal device includes a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., which are the computing core and control core of the terminal, which are suitable for implementing one or more instructions, and are specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding functions; the processor described in the embodiment of the present invention can be used for the operation of the clock frequency inspection method, including: According to the clock signal to be measured and the input frequency division coefficient A and the frequency division coefficient B value, the clock signal to be measured and the reference clock signal are divided to obtain the divided clock signal to be measured and the divided reference clock signal; the rising edge of the divided clock signal to be measured is counted from zero to obtain the count value A, and the rising edge of the divided reference clock signal is counted to obtain the count value B; the count value A is converted into Gray code, and then converted from Gray code to standard binary code A' after synchronization; the count value B is processed to obtain the count value B', and the standard binary code A' and the count value B' are used as a group of synchronization signals in the reference clock domain; in the clock domain of the reference clock signal, at each rising edge of the reference clock, the values ​​of the synchronization signals A' and B' are compared, and the corresponding high level or low level is output according to the frequency of the clock to be measured and the calibration value.

[0051] In another embodiment of the present invention, the present invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a terminal device for storing programs and data. It is understandable that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and the extended storage medium supported by the terminal device, and can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that more specific examples (non-exhaustive list) of the computer-readable storage medium here include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0052] Computer readable storage media also include data signals propagated in baseband or as part of a carrier wave, which carry readable program codes. Such propagated data signals can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than a readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0053] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0054] The processor may load and execute one or more instructions stored in a computer-readable storage medium to implement the corresponding steps of the clock frequency inspection method in the above embodiment; the processor may load and execute the following steps: According to the clock signal to be measured and the input frequency division coefficient A and the frequency division coefficient B value, the clock signal to be measured and the reference clock signal are divided to obtain the divided clock signal to be measured and the divided reference clock signal; the rising edge of the divided clock signal to be measured is counted from zero to obtain the count value A, and the rising edge of the divided reference clock signal is counted to obtain the count value B; the count value A is converted into Gray code, and then converted from Gray code to standard binary code A' after synchronization; the count value B is processed to obtain the count value B', and the standard binary code A' and the count value B' are used as a group of synchronization signals in the reference clock domain; in the clock domain of the reference clock signal, at each rising edge of the reference clock, the values ​​of the synchronization signals A' and B' are compared, and the corresponding high level or low level is output according to the frequency of the clock to be measured and the calibration value.

[0055] See also Figure 3 , the terminal device is a computer device. The computer device 60 of this embodiment includes: a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61. When the computer program 63 is executed by the processor 61, the method for calculating the fluid composition in the reservoir transformation wellbore in the embodiment is implemented. To avoid repetition, it is not described one by one here. Alternatively, when the computer program 63 is executed by the processor 61, the functions of each model / unit in the system of the embodiment* are implemented. To avoid repetition, it is not described one by one here.

[0056] The computer device 60 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The computer device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will appreciate that Figure 3 This is only an example of the computer device 60 and does not constitute a limitation of the computer device 60. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the computer device may also include input and output devices, network access devices, buses, etc.

[0057] The processor 61 may be a central processing unit (CPU), or other general-purpose processors, central processing units, graphics processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, data processing logic based on quantum computing, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0058] The memory 62 may be an internal storage unit of the computer device 60, such as a hard disk or memory of the computer device 60. The memory 62 may also be an external storage device of the computer device 60, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc., equipped on the computer device 60.

[0059] Furthermore, the memory 62 may include both an internal storage unit of the computer device 60 and an external storage device. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 may also be used to temporarily store data that has been output or is to be output.

[0060] Any reference to a memory, database or other medium used in the embodiments provided in the present application may include at least one of a non-volatile and a volatile memory. Non-volatile memory may include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical memory, a high-density embedded non-volatile memory, a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, etc. Volatile memory may include a random access memory (RAM) or an external cache memory, etc. As an illustration and not limitation, RAM may be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), etc.

[0061] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0062] See also Figure 4 The terminal device 600 is an electronic device, and the electronic device is in the form of a general computing device. The components of the electronic device may include but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including the storage unit 620 and the processing unit 610), a display unit 640, etc.

[0063] The storage unit stores program codes, which can be executed by the processing unit 610, so that the processing unit 610 performs the steps according to various exemplary embodiments of the present invention described in the above method section of this specification. For example, the processing unit 610 can perform the following steps: Figure 1 Follow the steps shown in .

[0064] The storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 6201 and / or a cache memory unit 6202 , and may further include a read-only memory unit (ROM) 6203 .

[0065] The storage unit 620 may also include a program / utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0066] Bus 630 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0067] The electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 600, and / or communicate with any device that enables the electronic device 600 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 650. Furthermore, the electronic device 600 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 660. The network adapter 660 may communicate with other modules of the electronic device 600 via a bus 630. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms, etc.

[0068] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0069] Simulation experiment A clock frequency test circuit of the present invention is tested, wherein the random range of the clock frequency to be tested is 1.6 GHz to 5 MHz, and the reference clock frequency is 100 MHz; a clock jitter of no more than 10% is added to the clock to be tested, a clock jitter of no more than 1% is added to the reference clock, and a frequency random error of 1‱ to 100‱ is added to the clock to be tested. The simulation results are as follows: Table 1 Simulation results

[0070] It can be seen from Table 1 that within a given detection window, the frequency anomalies caused by the frequency error of the clock to be measured can be correctly detected. And the size of the detection window is only related to the clock to be measured and its error, that is, the detection accuracy can be controlled by changing the size of the detection window. For example, increasing the detection window can increase the detection accuracy, and vice versa.

[0071] In summary, the present invention provides a clock frequency verification method, circuit, medium and device, which realize high-precision, anti-interference and real-time clock frequency verification through a unique frequency division counting method, a dynamic difference adjustment mechanism and the result judgment of high and low level outputs; it shows significant advantages in terms of clock frequency detection accuracy, anti-interference ability, real-time performance, adaptability and hardware implementation, and can provide an efficient, reliable and flexible frequency verification solution, significantly improve the overall performance of clock frequency verification, and reduce the misjudgment rate, which is an innovative improvement and optimization of the existing frequency verification technology.

[0072] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A clock frequency testing method, characterized in that: The following steps are involved: S1. According to the clock signal to be measured and the input frequency division coefficient A and frequency division coefficient B, the clock signal to be measured and the reference clock signal are frequency divided to obtain the clock signal to be measured and the reference clock signal after frequency division; S2, counting the rising edges of the divided clock signal to be measured from zero to obtain a count value A, and at the same time counting the rising edges of the divided reference clock signal to obtain a count value B; S3, converting the count value A into Gray code, and then converting the Gray code into standard binary code A' after synchronization; processing the count value B to obtain count value B', and using the standard binary code A' and count value B' as a set of synchronization signals in the reference clock domain; S4. In the clock domain of the reference clock signal, at each rising edge of the reference clock, the values ​​of the synchronization signals A' and B' are compared, and a corresponding high level or low level is output according to the clock frequency to be measured and the calibration value.

2. The clock frequency checking method according to claim 1, characterized in that: In step S3, a reference clock signal is used to perform two-level synchronization, and after synchronization, the Gray code is converted into a standard binary code A'; the count value B is delayed by two beats to obtain a count value B'.

3. The clock frequency checking method according to claim 1, characterized in that: In step S4, when the counting time reaches the detection window size, check the value of the difference. If the value is not equal to any of +1, -1, and 0, it is determined that the frequency of the clock to be measured does not match the calibration value, and a high level is output; otherwise, it is determined that the frequency of the clock to be measured matches the calibration value, and a low level is output.

4. The clock frequency checking method according to claim 3, characterized in that: When the value of the synchronization signal A' or B' changes and A'≠B', the difference is incremented. If the synchronization signal A'=B', the difference is decremented.

5. The clock frequency checking method according to claim 3, characterized in that: The detection window is calculated as follows: in, is the clock cycle to be measured, is the maximum frequency error of the clock to be tested that needs to be detected.

6. A clock frequency detection circuit, characterized in that: A clock frequency inspection method according to any one of claims 1 to 5, comprising a frequency divider A and a frequency divider B; a clock signal to be tested and a reference clock signal enter the frequency divider A and the frequency divider B respectively for frequency division operation, the clock signal to be tested after frequency division enters the counter A, and then outputs the count value of the clock to be tested and enters the synchronizer A, the synchronizer A outputs the synchronized count value A' of the clock to be tested, and the count value A' is input to the comparator; For the reference clock signal, the frequency divider B outputs the divided reference clock to the counter B and outputs the count value B. The count value B' obtained after synchronization with the synchronizer B is input to the comparator, and the output of the comparator is used as the detection result.

7. The clock frequency checking circuit according to claim 6, characterized in that: The input end of the frequency divider A is connected to the clock signal to be measured and the frequency division coefficient A, the output end of the frequency divider A is connected to the input end of the counter A; the output end of the counter A is connected to the input end of the synchronizer A; The input end of the frequency divider B is connected to the reference clock signal and the frequency division coefficient B, the output end of the frequency divider B is connected to the input end of the counter B; the output end of the counter B is connected to the input end of the synchronizer B.

8. The clock frequency checking circuit according to claim 6, characterized in that: Each synchronizer contains two levels of registers. The clocks of synchronizer A and synchronizer B are both derived from the reference clock signal. The data input of synchronizer A is connected to the output of counter A, and the data input of synchronizer B is connected to the output of counter B. The outputs of synchronizer A and synchronizer B are both connected to the input of the comparator.

9. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform the method of any one of claims 1 to 5.

10. A computing device, characterized in that: include: One or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include steps for executing the method described in any one of claims 1 to 5.

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