Redundant circuit, redundant address access circuit and access method

Abstract

The invention provides a redundant circuit, a redundant address access circuit and an access method. The redundant circuit comprises a fusing enabling generation module and an address fusing module, the fusing enabling generation module is used for generating a fusing enabling signal based on an input address and inputting the fusing enabling signal into the address fusing module, and the address fusing module comprises a plurality of units; the fusing enabling generation module is configured as follows: when an input address does not belong to a characteristic address, fusing enabling signals are all effective signals; and when the input address belongs to the characteristic address, the fusing enable signal input into the specific unit is an invalid signal, and the fusing enable signals input into the other units are effective signals. By designing the fusing enabling generation module, wrong matching without fusing enabling signals can be avoided without loading the fusing enabling signals from the outside, compared with the prior art, a loading module of the fusing enabling signals is omitted, the fusing loading time during startup can be shortened, and the reliability of the device is improved. And the workload of burnout of the fuse in a test project can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a redundant circuit, a redundant address access circuit and an access method. Background Art

[0002] The configuration of a DRAM (Dynamic Random Access Memory) storage array is: an array structure including multiple word lines and bit lines connected along the rows and columns of the storage array, and storage capacitors configured one by one at the intersection nodes of the word lines and bit lines. As the DRAM manufacturing process continues to shrink and the storage capacity continues to increase, there are failed cells in mass-produced DRAM chips. In order to enable the normal use of DRAM, the chip design includes redundant cells, which are used to repair failed cells to achieve the purpose of mass-producing qualified DRAM.

[0003] The redundant address that may be wrong during the DRAM chip access process. Figure 1 and 2 As shown in the figure, the chip test engineer tests the chip. Taking bit line redundancy as an example, assuming that the chip is well made and no bit line fails during the test, the fuse setting will not be modified. At this time, the fuse will have a default fuse address. When the chip is turned on, the default fuse address will be loaded as fuse address 2. When performing write / read operations, the column address may just match fuse address 2, thereby generating an erroneous redundant address, but in fact the column address is not invalid. To avoid the above situation, it is usually necessary to control it by loading a fuse enable signal from the outside. The process is as follows Figure 3 As shown. If there is no failed bit line during the test process, the fuse is set to the corresponding value by modifying the enable signal fuse setting, so that the fuse enable signal 1 is invalid. During the process of powering on the chip, this fuse enable signal 1 is loaded into the redundant circuit. This value is called fuse enable signal 2. Even if the column address and fuse address 2 match, the fuse enable signal 2 is invalid and there will be no erroneous redundant address, thereby avoiding the above situation. However, this method not only requires a special setting of a load module for generating the fuse enable signal 1, but also increases the time for fuse loading during power-on and the workload of the test engineering to burn the fuse.

[0004] To this end, the present application proposes a redundant circuit, a redundant address access circuit and an access method, which can reduce the number of DRAM fuses. It does not require loading a fuse enable signal from the outside and can avoid the above-mentioned situation where there is no fuse enable signal and the mismatch occurs. It plays a role in reducing the number of fuses, and can also reduce the time for fuse loading when starting up, and can also reduce the workload of blowing fuses in the test project.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] The object of the present invention is to provide a redundant circuit, a redundant address access circuit and an access method.

[0007] In order to solve the above problems, in a first aspect, a redundant circuit is provided below, including a fuse enable generation module and an address fuse module; The fuse enable generation module generates a fuse enable signal based on an input address and inputs the signal into the address fuse module, wherein the address fuse module includes a plurality of units; The fuse enable generation module is configured as follows: when the input address does not belong to the characteristic address, the fuse enable signals are all valid signals; when the input address belongs to the characteristic address, the fuse enable signal input to a specific unit is an invalid signal, and the fuse enable signal input to the remaining units is a valid signal.

[0008] By designing a fuse enable generation module, the present application can avoid the need to load the fuse enable signal from the outside and can also avoid the occurrence of erroneous matching without the fuse enable signal. Compared with the prior art, not only the loading module of the fuse enable signal is omitted, but also the time for fuse loading during startup can be reduced, and the workload of the test project for blowing the fuse can be reduced.

[0009] The address fuse module includes a plurality of address fuse loading and address comparison units; the address fuse loading and address comparison units are configured to: load the fuse address and store it in the unit, compare the input address with the stored fuse address; if the address matches and the fuse enable signal is a valid signal, the address fuse loading and address comparison unit generates the flag signal representing the valid signal and the corresponding redundant address; if it does not match or the fuse enable signal is an invalid signal, the address fuse loading and address comparison unit generates the flag signal representing the invalid signal and an invalid redundant address. By comparing the input address with each fuse address stored in the unit to confirm whether it matches, and then combining the fuse enable signal to comprehensively judge whether it is a redundant address, that is, only if it matches the fuse address and the fuse enable signal is valid, it is identified as a redundant address to prevent incorrect matching.

[0010] The number of the address fuse loading and address comparison units is the same as the number of the redundant addresses; the fuse enable generation module can generate multiple independent fuse enable signals and input them into each of the address fuse loading and address comparison units, respectively, to ensure that each redundant address can be judged to avoid errors.

[0011] The first level indicates that the fuse enable signal is a valid signal, and the second level indicates that the fuse enable signal is an invalid signal; the first level indicates that the flag signal is a valid signal, and the second level indicates that the flag signal is an invalid signal; the first level and the second level are respectively one of a high level and a low level. Validity and invalidity are respectively indicated by high and low levels, that is, the first level and the second level can be set to low or high, for example, a low level indicates invalidity, a high level indicates validity, or vice versa.

[0012] In a second aspect, the present invention further provides a redundant address access circuit, comprising the redundant circuit, the selector and the normal and redundant decoding circuit described in the first aspect; The selector selects to output the input address or the redundant address to the normal and redundant decoding circuit based on the input address, the redundant address and the flag signal; The normal and redundant decoding circuit decodes the received address and outputs the corresponding word line address or bit line address.

[0013] After adopting the redundant circuit of the present invention, the structure of the redundant address access circuit is greatly simplified, and the time of fuse loading during startup can be effectively reduced.

[0014] The invention also includes an address latch circuit; the address latch circuit is used to receive the input address and output the latch address after latching, and the latch address is input into the redundant circuit and the selector respectively. The input address is latched, and when the activation operation is performed, the input address is maintained unchanged, and the address information of non-current bank activation is filtered out.

[0015] The invention also includes a pre-decoding circuit; the pre-decoding circuit is arranged between the address latch circuit and the selector, and the pre-decoding circuit is used to pre-decode the input latch address and then input it into the selector. The pre-decoding circuit performs pre-decoding, and the addressable range can be divided first, and the target word line / bit line can be located more quickly, thereby improving the overall work efficiency.

[0016] In a third aspect, the present invention further provides a redundant address access method, which is performed using a redundant address access circuit as described in the second aspect, and comprises the following steps: Loading the input address and the fuse address to the redundant circuit respectively to generate a flag signal and a redundant address; Based on the flag signal, the selector selects and outputs the input address or the redundant address; The address output by the selector is transmitted to the normal and redundant decoding circuit, and decoded to obtain a corresponding word line address or bit line address.

[0017] The method comprises the following steps: when there is no failed unit, setting the default fuse address corresponding to each redundant address to a characteristic address respectively; loading the input address to the redundant circuit, loading the characteristic address as the fuse address and storing it in one of the units respectively; and generating a flag signal and a redundant address based on the fuse enable signal, the input address and the fuse address.

[0018] When a failed unit exists, the failed address is recorded, and the default fuse address corresponding to the redundant address is modified to the failed address, and the default fuse addresses corresponding to the remaining redundant addresses are respectively set to a characteristic address; when the failed address does not belong to the characteristic address, the input address is loaded to the redundant circuit, the failed address and / or the characteristic address are loaded as the fuse address and stored in one of the units respectively, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address; when the failed address belongs to the characteristic address, the input address is loaded to the redundant circuit, the failed address and / or the characteristic address are loaded as the fuse address and stored in one of the units respectively, wherein the failed address is loaded into the unit where the received fuse enable signal is a valid signal, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address.

[0019] Compared with the prior art, the beneficial effects of the present invention mainly include as follows: by designing a fuse enable generation module, the present application can avoid the need to load the fuse enable signal from the outside and can also avoid the occurrence of erroneous matching without the fuse enable signal. Compared with the prior art, not only the loading module of the fuse enable signal is omitted, but also the time for fuse loading during startup can be reduced, and the workload of the test project for blowing the fuse can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 Schematic diagram of the word line / bit line redundant cell access process.

[0022] Figure 2 It is a schematic diagram of the redundant circuit structure in the prior art.

[0023] Figure 3 The figure is a schematic diagram of the overall structure of a redundant circuit in the prior art.

[0024] Figure 4 It is a schematic diagram of the word line / bit line redundant unit access process provided in this embodiment.

[0025] Figure 5 This is a schematic diagram of the redundant circuit structure provided in this embodiment.

[0026] Figure 6 This is the circuit design of the fuse enabling module provided in this embodiment. DETAILED DESCRIPTION

[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0028] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0029] In order to better understand the working principle of the present invention, the general working process of accessing a redundant unit in a DRAM chip and the structure of a related circuit are exemplarily described below, but the present invention is not limited in any form.

[0030] like Figure 1As shown, the word line / bit line redundant access circuit mainly includes an address latch circuit, a pre-decoding circuit, a redundant circuit, a selector, and a normal and redundant decoding circuit. When the DRAM chip is operated (ACT), the input address is latched by the address latch circuit and then the latch address is output; based on the input latch address, the redundant circuit compares the latch address with the fuse address stored in the redundant circuit to determine whether it is a redundant word line / bit line, and generates a corresponding flag signal and redundant address; the flag signal and the redundant address are input into the selector, and the flag signal controls the selector to select between the normal address and the redundant address, and finally the word line / bit line address is decoded by the normal and redundant decoding circuit; the flag signal is generated after each comparison, and the flag signal has two states, 0 or 1, where 0 can represent a redundant address and 1 can represent a non-redundant address. For example, the low level (first level) is 0, the high level (second level) is 1, the first level indicates that the flag signal is a valid signal, and the second level indicates that the flag signal is an invalid signal, or vice versa.

[0031] In the above process, the redundant circuit is the key to realize the access process. It can be understood that the above example is only a common structure in the prior art. In other schemes, the address latch circuit may not be set, which is not limited here. Figure 1 The structure also includes a pre-decoding circuit, which is connected to the address latch circuit and the selector respectively. In the example case, the latched input address enters the pre-decoding circuit and the redundant circuit at the same time. In other schemes, the pre-decoding circuit may not be set, which is not limited here.

[0032] The redundant circuit diagram in the prior art is as follows: Figure 2 As shown. The redundant circuit mainly includes an enable fuse loading module, an address fuse loading module and an address comparison module. Figure 1 As shown, the signals input to the redundant circuit include a power-on signal, a latch address, a fuse address 1, and a fuse enable signal 1; Figure 2 As shown, the power-on signal is respectively input into the enable fuse loading module and the address fuse loading module, the latched address is directly input into the address comparison module, the fuse address 1 is input into the address fuse loading module, and the fuse enable signal 1 is input into the enable fuse loading module.

[0033] Specifically, refer to Figure 2, the figure shows the process of fuse address loading and address comparison. It can be understood that in order to ensure the normal use of DRAM chips, after the chip design stage is completed, the chip test engineer will test the chip. If the word line / bit line is found to be failed, the address will be recorded, and the fuse will be set to the corresponding value by modifying the fuse setting (that is, the fuse is assigned to the recorded failure address). This value is called fuse address 1; during the process of powering on the chip (that is, a power-on signal will be generated), this fuse address 1 is loaded into the redundant circuit (that is, the input address fuse loading module) and latched to obtain a new value, which is called fuse address 2; when the chip is operated, it is performed Figure 1 The process shown is to compare the latch address with the fuse address 2 to obtain the corresponding flag signal and redundant address.

[0034] However, the above process may generate an erroneous redundant address. For easier understanding, the bit line redundancy is used as an example. Assuming that the chip is well made and no bit line fails during the test, the fuse setting will not be modified. At this time, although the fuse will not be assigned a failure address, it will have a default fuse address. The default fuse address here is the input fuse address 1 (the default fuse address and the above fuse address 1 are the values ​​of the same point. It just means that when the fuse setting is not modified, there will be a default fuse address. When the fuse setting is modified, the default fuse address will be modified to the recorded failure address). When the chip is powered on, the default fuse address (that is, the fuse address 1 in the figure) will be loaded into the address fuse loading circuit and fuse address 2 will be generated; when the write / read operation is performed later, the latch address (in bit line redundancy, the latch address is the column address) may just match the fuse address 2, thereby generating an erroneous redundant address, but in fact the latch address is not invalid.

[0035] In order to avoid the above-mentioned mismatch, it is necessary to add a fuse enable signal for control. In the prior art, the generation of the fuse enable signal requires a special setting of a corresponding circuit module. If there is no failed bit line in the test process, the fuse is set to the corresponding value by modifying the enable signal fuse setting, thereby obtaining a fuse enable signal 1, which represents invalidity; during the process of powering on the chip, this fuse enable signal 1 is loaded into the enable fuse loading module of the redundant circuit and a new value is output, which is called fuse enable signal 2, which also represents invalidity, and is input into the address comparison circuit.

[0036] The overall structure diagram of the redundant circuit is as follows: Figure 3 As mentioned above, the redundant circuit mainly includes an enable fuse loading module, an address fuse loading module and an address comparison module. Figure 3In FIG. 1 , the address fuse loading module and the address comparison module are combined in one place, that is, the address fuse loading and address comparison module shown. Figure 3 , taking DDR4 as an example, it is assumed that its bit line has 4 sets of redundant addresses, namely SYS0, SYS1, SYS2 and SYS3. After the latch address and fuse address 1 (fuse address 1 is not shown in the figure here) are input, the 4 sets of fuse addresses 1 are loaded into the 4 sets of address fuse loading and address comparison units respectively and the corresponding fuse address 2 is obtained, and then the latch address is compared with the 4 sets of fuse addresses 2 respectively. When the latch address (column address) and the fuse address 2 are compared, the additional judgment of the fuse enable signal 2 is introduced. In this process, even if the latch address and the fuse address 2 match, since the fuse enable signal 2 is invalid, there will be no erroneous redundant address, thereby avoiding the above situation. Only when the latch address and the fuse address 2 match, and the fuse enable signal 2 also indicates validity, the redundant circuit will generate the corresponding flag signal and redundant address and input them into the selector.

[0037] Embodiment 1 As mentioned above, although the prior art can avoid generating erroneous redundant addresses, it needs to load the fuse enable signal 1 from the outside (i.e., a corresponding fuse enable signal 1 generation module is required, and each redundant address needs a corresponding generation module). Taking DDR4 as an example, assuming that its bit line has 4 groups of redundant addresses, the column address has 7 bits, that is, the bit fuse address is 7 bits, the fuse enable signal is 1 bit, and the column fuse is divided into 24 modules, then the number of fuses is 4*(7+1)*24=768; similarly, assuming that the word line has 64 groups of redundant addresses, the row address has 14 bits, that is, the row fuse address has 14 bits, and the fuse enable signal is 1 bit, then the number of fuses is 64*(14+1)=960. Among them, the number of fuses used to generate the fuse enable signal 1 is (4*1*24)+64*1=160. To this end, the present application intends to provide a new technical solution, which can avoid the need to load the fuse enable signal 1 from an external circuit module and avoid the above-mentioned situation where there is no fuse enable signal and the mismatch occurs, thereby greatly reducing the number of fuses used. Taking the above as an example, it can not only reduce 160 groups of fuse enable signal generating modules, but also reduce the time of fuse loading when starting up, and also reduce the workload of fuse burning in the test engineering.

[0038] The present application provides a redundant circuit, a redundant address access circuit and an access method, wherein the word line / bit line redundant access circuit structure is as follows: Figure 4 As shown, the redundant circuit structure is as follows Figure 5 shown.

[0039] refer to Figure 4 and Figure 5 . Figure 4The word line / bit line redundant access circuit provided by the present application. A redundant address access circuit mainly includes an address latch circuit, a pre-decoding circuit, a redundant circuit, a selector, and a normal and redundant decoding circuit. Among them, the address latch circuit and the pre-decoding circuit are not necessarily set.

[0040] like Figure 5 As shown, a redundant circuit is provided, in which the redundant circuit structure mainly includes a fuse enable generation module and an address fuse module.

[0041] Among them, the address fuse module is as described above, which includes multiple units, each unit stores a fuse address, and the address fuse module generates a flag signal and a redundant address based on the fuse enable signal, the input address and the fuse address; specifically, the address fuse module includes multiple groups of one-to-one corresponding address fuse loading units and address comparison units, wherein the address fuse loading and address comparison units are the same as those in the prior art.

[0042] The present application specifically designs a fuse enable generation module, which is used to generate the MFSYST<3:0> signal (MFSYST<3:0> is an independent four-bit signal, each bit of which has two states, 0 or 1. In this embodiment, 0 represents an invalid signal and 1 represents a valid signal. The specific representation method can also refer to the flag signal). The role played by this signal is similar to that of the fuse enable signal 2 in the prior art. However, in the prior art, the fuse enable signal 1 needs to be loaded from an external circuit module before the fuse enable signal 2 can be obtained. However, the present patent generates the signal directly inside the circuit without the need for external loading.

[0043] It can be understood that a certain number of redundant units are provided in the chip to replace possible word line / bit line failures. The fuse of each redundant unit has a default blown address. In order to facilitate understanding of the working principle of the redundant circuit provided in the present application, the bit line is also taken as an example. Assume that the bit line has 4 groups of redundant addresses (named as redundant address SYS0, redundant address SYS1, redundant address SYS2 and redundant address SYS3), and the column address has 7 bits, that is, the length of the bit blown address is 7 bits. First, the default blown addresses corresponding to the 4 groups of bit line redundant addresses are set to different values. In this embodiment, the value is called the characteristic address, that is, the 4 groups of characteristic addresses at this time are: characteristic address SYS0: 0000000, characteristic address SYS1: 0000001, characteristic address SYS2: 1000000, characteristic address SYS3: 1000001. It can be understood that the characteristic address is a pre-determined address, the number of characteristic addresses should be the same as the number of redundant addresses, and the length of the redundant address should be the length of the blown address. In other embodiments, each characteristic address may also be set to other values, which are not limited thereto. However, when set to other values, the logic structure of the corresponding circuit needs to be adaptively adjusted so that the corresponding characteristic address meets the conditions.

[0044] It can be understood that since the bit lines have four sets of redundant addresses, four address fuse loading and address comparison units should also be set in the corresponding address fuse module, that is, Figure 5 The address fuse loading and address comparison unit SYS0, the address fuse loading and address comparison unit SYS1, the address fuse loading and address comparison unit SYS2 and the address fuse loading and address comparison unit SYS3 are shown.

[0045] Figure 5 The fuse enable generation module shown is configured as follows: when the input address (i.e., latch address) and the characteristic address SYS0-SYS3 are different (i.e., not any one of 0000000, 0000001, 1000000 and 1000001), the 4-bit fuse enable signals generated by the fuse enable generation module all represent valid signals; when the input address (i.e., latch address) and a certain characteristic address are the same (i.e., one of 0000000, 0000001, 1000000 and 1000001), in the 4-bit fuse enable signal MFSYST<3:0> generated by the fuse enable generation module, 3-bit fuse enable signals represent valid, 1-bit fuse enable signal represents invalid, and the fuse enable signal representing invalid will be input into a specific unit. In the present application, the specific unit is a unit in which the fuse address stored in the unit is the same as the input address. There are many ways to implement the circuit of the fuse enable signal MFSYST<3:0>. This application proposes a logic structure, such as Figure 6 shown.

[0046] Specifically, if a bit line failure is found during the test, the failure address is recorded, and the fuse is subsequently modified to the recorded failure address by modifying the fuse setting. There are two situations at this time: First, the failure address and the four groups of characteristic addresses are different, then a characteristic address is modified to the recorded failure address by modifying the fuse setting, and this value is fuse address 1, which is latched in the subsequent circuit to obtain fuse address 2 for comparison. During access, if the latch address and the failure address are different, the latch address and the fuse address 2 cannot match. Regardless of whether the MFSYST<3:0> signal is valid or not, the final output flag signal represents that it is not a redundant address, and a normal bit line will be obtained after decoding; if the latch address and the failure address are the same, the 4-bit MFSYST<3:0> signal generated by the fault enable generation module represents validity (because the latch address and the 4 sets of characteristic addresses are different at this time), and the final output flag signal represents a redundant address, and a redundant bit line will be obtained after decoding; second, if the failure address is the same as one of the 4 sets of characteristic addresses, the characteristic address is also modified to the recorded failure address by modifying the fuse setting, which is the fuse address 1. After latching in the subsequent circuit, the fuse address 2 for comparison is obtained. However, it should be noted that the address fuse loading and address comparison unit to which the fuse address 1 is to be loaded should be reasonably selected here. For example, when the failure address is 0000000, the characteristic address is modified to the recorded failure address by modifying the fuse setting. The fuse address 1 here cannot be loaded into the address fuse loading and address comparison unit SYS0, but is loaded into the remaining address fuse loading and address comparison units. During access, if the latch address and the failure address are different, the latch address and fuse address 2 cannot match at this time. Regardless of whether the MFSYST<3:0> signal is valid, the final output flag signal represents that it is not a redundant address, and a normal bit line will be obtained after decoding; if the latch address and the failure address are the same, the 4-bit MFSYST<3:0> signal generated by the fault enable generation module at this time, the input to the address fuse loading and address comparison unit SYS0 represents invalid, while the other 3 represent valid. Because the fuse address 2 here is located in the unit representing valid, the final output flag signal represents that it is a redundant address, and a redundant bit line will be obtained after decoding, thus achieving repair.

[0047] If no failed unit is found during the test, the fuse setting will not be modified, and the fuse will not be assigned a failed address, that is, the fuse address 1 finally loaded is the characteristic address. For the first group of bit line redundancy addresses SYS0, its characteristic address is 0000000, that is, the first group of fuse address 1 is 0000000, and after the fuse address 1 is input into the address fuse loading unit, the corresponding first group of fuse address 2 will be output, and its value is still 0000000, that is, the value of the fuse address 2 loaded in the first address fuse loading and address comparison unit SYS0 at this time is 0000000; similarly, the value of the fuse address 2 loaded in the second address fuse loading and address comparison unit SYS1 is 0000001; the value of the fuse address 2 loaded in the third address fuse loading and address comparison unit SYS2 is 1000000; the value of the fuse address 2 loaded in the fourth address fuse loading and address comparison corresponding SYS3 is 1000001.

[0048] As mentioned above, we know that the reason for the generation of the wrong redundant address is that the value of the fuse address 2 loaded into the corresponding unit of the fuse and the value of the input latch address just match. In other words, only when the value of the latch address input into the address fuse loading and address comparison unit is the same as the value of the fuse address 2 stored in the unit, the wrong redundant address match will occur. Therefore, there are only 4 column addresses that may produce wrong matches, namely 0000000, 0000001, 1000000, and 1000001.

[0049] refer to Figure 4 and Figure 5 When the value of the first column address 0000000 is input, the corresponding latch address will be latched and output through the address latch circuit. The value of the latch address is still 0000000; the generated latch address will be input at the same time Figure 5 In the fuse enable generation module and the address fuse module.

[0050] The latched address input into the address fuse module is compared with the fuse address 2 in each unit respectively. It can be understood that the result of the address comparison is that only the address fuse load matches the address comparison unit SYS0, while the other three units do not match.

[0051] The latched address of the input fuse enable generation module generates the MFSYST<3:0> signal and inputs it to the four groups of address fuse loading and address comparison units SYS0-SYS3. As mentioned above, the function of the fuse enable generation module is: when the input address (i.e. latched address) is the same as a certain characteristic address, 3 bits of the 4-bit MFSYST<3:0> signal generated by the fuse enable generation module represent valid and 1 bit represents invalid, and the invalid signal will be input to the address fuse loading and address comparison unit with the same value as the latched address, that is, the MFSYST<3:0> in the output MFSYST<3:0> at this time will be valid. <0> =0, then although the address fuse load matches the address comparison unit SYS0, the corresponding signal MFSYST <0> If 1 represents invalid, the final output flag signal represents not a redundant address. Although the remaining 3 bits represent valid, the other 3 address fuses do not match the two addresses in the address comparison unit SYS1-SYS3, and no redundant address will be generated in the end.

[0052] Similarly, when the input column address value is 0000001, only the address fuse load matches the address comparison unit SYS1, and MFSYST <1> =0, and no erroneous redundant address will be generated in the end; when the input column address value is 1000000, only the address fuse load matches the address comparison unit SYS2, and MFSYST <2> =0, and no erroneous redundant address will be generated in the end; when the input column address value is 1000001, only the address fuse load matches the address comparison unit SYS3, and MFSYST <3> =0, no erroneous redundant addresses will be generated in the end.

[0053] The above description is only for the purpose of exemplary description using four groups of bit lines, and the present application does not limit the bit lines or word lines, the specific number of redundant cells, the length of each address, etc.

[0054] It can be understood that the number of redundant addresses in the DRAM chip can be predetermined. According to the number of redundant addresses, the fuse enable generation module and the address fuse module will also be modified accordingly. When there are N groups of redundant addresses, respectively recorded as redundant addresses SYSi (0≤i≤N-1), the corresponding address fuse module is also composed of N address fuse loading and address comparison units, respectively recorded as address fuse loading and address comparison units SYSi (0≤i≤N-1). The fuse enable generation module is used to generate a fuse enable signal MFSYST <n-1:0>, the MFSYST <n-1:0>The signals are N independent signals, which are input into an address fuse loading and address comparison unit respectively.

[0055] First, before designing the fuse enable generation module, some characteristic addresses must be confirmed first, and then the circuit design of the fuse enable generation module is performed based on the pre-set characteristic addresses. Specifically, the default fuse address corresponding to each redundant address SYSi is first set to a different characteristic address, which is recorded as a characteristic address Mi (0≤i≤N-1); at this time, the fuse enable generation module is configured as follows: when the input address does not belong to the characteristic address (that is, it is different from each characteristic address Mi), the N-bit fuse enable signals generated by the fuse enable generation module all represent valid signals; when the input address belongs to the characteristic address (that is, it is the same as a certain characteristic address Mi), in the N-bit fuse enable signals generated by the fuse enable generation module, N-1 bits represent valid, 1 bit represents invalid, and the invalid signal will be input into a specific unit, and the address stored in the specific unit is the same as the input address. This is easy to achieve because we can control the address loaded in each address fuse loading and address comparison unit SYSi. As long as we confirm in advance which unit each characteristic address is located in, we can set the circuit of the fuse enable generation module accordingly, so that when the input address belongs to the characteristic address, the fuse enable signal input to the specific unit is an invalid signal, and the fuse enable signal input to the remaining units is a valid signal.

[0056] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0057] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A redundant circuit, characterized in that: It includes a fuse enable generation module and an address fuse module; The fuse enable generation module generates a fuse enable signal based on an input address and inputs the signal into the address fuse module, wherein the address fuse module includes a plurality of units; The fuse enable generation module is configured as follows: when the input address does not belong to the characteristic address, the fuse enable signals are all valid signals; when the input address belongs to the characteristic address, the fuse enable signal input to a specific unit is an invalid signal, and the fuse enable signal input to the remaining units is a valid signal.

2. A redundant circuit according to claim 1, characterized in that: The address fuse module includes a plurality of address fuse loading and address comparison units; The address fuse loading and address comparison unit is configured to: load a fuse address and store it in the unit, and compare the input address with the stored fuse address; If the address matches and the fuse enable signal is a valid signal, the address fuse loading and address comparison unit generates the flag signal indicating a valid signal and a corresponding redundant address; If there is no match or the fuse enable signal is an invalid signal, the address fuse loading and address comparison unit generates the flag signal indicating an invalid signal and an invalid redundant address.

3. A redundant circuit according to claim 2, characterized in that: The number of the address fuse loading and address comparison units is the same as the number of the redundant addresses; The fuse enable generation module can generate multiple independent fuse enable signals and input them into each of the address fuse loading and address comparison units respectively.

4. A redundant circuit according to claim 2, characterized in that: The first level indicates that the fuse enable signal is a valid signal, and the second level indicates that the fuse enable signal is an invalid signal; Indicating that the flag signal is a valid signal with a first level, and indicating that the flag signal is an invalid signal with a second level; The first level and the second level are respectively one of a high level and a low level.

5. A redundant address access circuit, characterized in that: The method comprises a redundant circuit, a selector and a normal and redundant decoding circuit according to any one of claims 1 to 4; The selector selects to output the input address or the redundant address to the normal and redundant decoding circuit based on the input address, the redundant address and the flag signal; The normal and redundant decoding circuit decodes the received address and outputs the corresponding word line address or bit line address.

6. A redundant address access circuit according to claim 5, characterized in that: Also included is an address latch circuit; The address latch circuit is used to receive the input address and output a latched address after latching, and the latched address is input into the redundancy circuit and the selector respectively.

7. A redundant address access circuit according to claim 6, characterized in that: Also includes a pre-decoding circuit; The pre-decoding circuit is arranged between the address latch circuit and the selector, and is used for pre-decoding the input latch address and then inputting it into the selector.

8. A redundant address access method, characterized in that: The method is performed by using a redundant address access circuit as claimed in any one of claims 5 to 7, comprising the following steps: Loading the input address and the fuse address to the redundant circuit respectively to generate a flag signal and a redundant address; Based on the flag signal, the selector selects and outputs the input address or the redundant address; The address output by the selector is transmitted to the normal and redundant decoding circuit, and decoded to obtain a corresponding word line address or bit line address.

9. A redundant address access method according to claim 8, characterized in that: The steps include: When there is no failed unit, the default fuse address corresponding to each redundant address is set to a characteristic address; The input address is loaded into the redundant circuit, the characteristic address is loaded as a fuse address and is stored in one of the units respectively, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address.

10. A redundant address access method according to claim 8, characterized in that: When a failed unit exists, the failed address is recorded, and the default fuse address corresponding to the redundant address is modified to the failed address, and the default fuse addresses corresponding to the remaining redundant addresses are respectively set as a characteristic address; When the failure address does not belong to the characteristic address, the input address is loaded into the redundant circuit, the failure address and / or the characteristic address are loaded as a fuse address and stored in one of the units respectively, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address; When the failure address belongs to the characteristic address, the input address is loaded into the redundant circuit, and the failure address and / or the characteristic address are loaded as fuse addresses and stored in one of the units respectively, wherein the failure address is loaded into the unit where the received fuse enable signal is a valid signal, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address.

Images