D-STATCOM coordination control method for system short circuit fault

Abstract

The invention relates to the technical field of power system control, in particular to a D-STATCOM coordination control method for a system short circuit fault. On the basis of a traditional double-closed-loop control strategy, an outer loop achieves voltage control, an inner loop rapidly tracks current, a control link based on the bus voltage change rate and a transient rapid reactive compensation control link are introduced into the outer loop voltage control, and after q-axis reactive reference current output in the outer loop control is modified, the current is subjected to rapid reactive compensation control. And the voltage is sent to inner loop control, a control signal is generated and input into SPWM to obtain a trigger signal of an IGBT, and the D-STATCOM is controlled to send out reactive power to compensate the voltage. The method has the advantages that the reactive compensation capability of the D-STATCOM in the short-circuit fault is improved, and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of power system control, and in particular to a D-STATCOM coordinated control method for a system short circuit fault. Background Art

[0002] With the rapid development of smart grids, the increasing complexity of power loads, and the large-scale incorporation of nonlinear disturbance sources into the power grid, a large number of increasingly prominent power quality problems have appeared in regional power grids, causing very serious losses to modern industry and the national economy. Among these problems, among various power quality problems, voltage sag is the most frequent and most serious one. Monitoring data shows that more than 80% of power quality problems are caused by voltage sag. Short-term voltage sags may cause abnormal working conditions of sensitive devices, and in severe cases may even cause sensitive devices to shut down, causing significant losses to enterprises.

[0003] In order to solve the problem of voltage sag, the engineering projects usually adopt the method of installing reactive power compensation devices to support the bus voltage. In the solution of voltage sag control, the distribution network static synchronous compensator (D-STATCOM) plays an important role. Since the compensator connected to the distribution network is close to the load, it can avoid the long-distance flow of reactive power flow and timely suppress the power quality problems caused by single-phase high-power equipment or nonlinear loads, so that the performance of STATCOM can be maximized. Its control method has also been a hot research topic in recent years.

[0004] The classic D-STATCOM control strategy is to use dual closed-loop control, with the outer loop implementing voltage control and the inner loop quickly tracking the current. When a short circuit occurs in the system, the existing D-STATCOM control method compensates for the system voltage change by changing the control system output command, which inevitably has a certain lag delay. When the control command cannot immediately respond to the rapid change in voltage, it will lead to insufficient compensation for low voltage during the fault, which will help increase the system's overvoltage after the fault ends, but the existing control method does not consider these issues. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention is proposed.

[0006] Therefore, the present invention provides a D-STATCOM coordinated control method for system short-circuit faults, adds a control link based on the bus voltage change rate and a transient fast reactive power compensation control link to the outer loop part of the control system, improves the original control system, and improves the reactive power compensation capability of D-STATCOM during short-circuit faults.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: a D-STATCOM coordinated control method for system short-circuit faults, comprising: based on a dual closed-loop control strategy, the outer loop realizes voltage coordinated control, the inner loop quickly tracks the current, a control link based on the bus voltage change rate and a transient fast reactive power compensation control link are introduced into the outer loop voltage control, the q-axis reactive reference current output in the outer loop control is modified and sent to the inner loop control, a control signal is generated and input into the SPWM to obtain an IGBT trigger signal, and the D-STATCOM is controlled to emit reactive power to compensate the voltage; the detected bus voltage and current are obtained, and the The detected voltage is derived and sent to the fault judgment module to determine whether a fault occurs, and the fault judgment module controls the input of the undervoltage module and the overvoltage module; the additional component generated after the input of the undervoltage module or the overvoltage module is sent to the outer loop q-axis voltage control of the D-STATCOM; the reactive input component generated by the transient fast reactive compensation control link is sent to the outer loop q-axis voltage control after PI control; the q-axis reactive reference current output from the modified outer loop control is sent to the inner loop control, and the control signal is generated and input into the SPWM to obtain the trigger signal of the IGBT, so as to control the D-STATCOM to emit reactive power compensation voltage.

[0008] As a preferred solution of the D-STATCOM coordinated control method for system short circuit fault described in the present invention, wherein: the voltage coordinated control is put into operation only when it is judged that a fault occurs, and the bus minimum reference voltage U minref Take 0.98pu, the bus maximum reference voltage U maxref Take 1.02pu, the minimum reference value of bus voltage change rate Take -0.1, and the maximum reference value of the bus voltage change rate is 0.1. When a voltage sag occurs, voltage coordination control is started in advance to reduce the impact of communication delay.

[0009] As a preferred solution of the D-STATCOM coordinated control method for system short circuit fault described in the present invention, the fault judgment module includes measuring the bus voltage U c , calculate the voltage change rate dU c / dt, when a fault occurs, detected and U c <U minref When both conditions are met, the undervoltage module is put into use. When the fault disappears, it is detected and U c >U maxref When all conditions are met at the same time, the overvoltage module is put into use, and after the voltage returns to normal, normal voltage control is restored and the system resumes stable operation.

[0010] As a preferred solution of the D-STATCOM coordinated control method for system short-circuit fault described in the present invention, the undervoltage module includes: when there is no short-circuit fault in the system, The undervoltage module is not enabled; when a short circuit occurs in the system, it is detected and U c <U minref When both conditions are met, the undervoltage module is activated to suppress voltage sag, and the reactive reference current output by the q-axis in the outer loop control is:

[0011]

[0012] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I1 K is the integral time constant of the undervoltage module PI controller; P1 is the proportional coefficient of the undervoltage module PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control;

[0013] When the bus voltage is lower than the normal value due to a short circuit fault and has a tendency to decrease, is a positive value. After PI control, the positive voltage compensation value is added to the voltage link. The additional component of the outer loop reactive current G obtained by PI in voltage control U When the reactive current is positive, the reactive current sent to the inner loop to control the outer loop increases. As the reactive current in the outer loop increases, STATCOM speeds up the reactive power generation rate, increases the reactive power generated, and better suppresses voltage sag.

[0014] As a preferred solution of the D-STATCOM coordinated control method for system short circuit fault described in the present invention, the overvoltage module includes: The overvoltage module is not enabled;

[0015] When a fault is detected and U c >U maxref When the overvoltage module is turned on through the fault judgment module, the transient high voltage is suppressed. The reactive reference current value of the q-axis output in the outer loop control is:

[0016]

[0017] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I2K is the integral time constant of the undervoltage module PI controller; P2 is the proportional coefficient of the undervoltage module PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control;

[0018] When the fault disappears, due to the excessive reactive power generated by D-STATCOM, the bus voltage is higher than the normal value and tends to increase. It is a negative value. After PI control, the negative voltage compensation value is added to the voltage control link. The additional component of the outer loop reactive current G obtained by PI in the voltage control is U When the reactive current of the outer loop is negative, the reactive current sent to the inner loop is reduced. As the reactive current of the outer loop decreases, STATCOM speeds up the reduction of the reactive power output rate, better suppressing the voltage overshoot caused by excessive reactive power output.

[0019] As a preferred solution of the D-STATCOM coordinated control method for system short circuit fault described in the present invention, wherein: the q-axis reactive reference current is expressed as,

[0020] i qref =[(U cref -U c )+(Q cref -Q c )×(K P-Q +K I-Q / s)]

[0021] ×(K P +K I / s)

[0022] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I-Q K is the integral time constant of the transient fast reactive power-voltage compensation PI controller; P-Q is the proportional coefficient of the transient fast reactive power-voltage compensation PI controller; U cref is the reference value of bus voltage; Q cref is the bus reactive power reference voltage; Q c is the detected bus reactive power; U c To detect the bus voltage of the system.

[0023] As a preferred solution of the D-STATCOM coordinated control method for system short-circuit fault described in the present invention, wherein: a reactive input component is added to the q-axis voltage control of the STATCOM outer loop to form a bus voltage-reactive droop control, and according to the droop control principle, it is calculated that:

[0024] U c =U cref -K Qs (Q ref -Q c )

[0025] Among them, K Qs is the droop coefficient of reactive power droop control; U cref is the reference value of bus voltage; Q cref is the bus reactive power reference voltage; Q c Detected bus reactive power; U c To detect the bus voltage of the system;

[0026] According to the above analysis, in the fast reactive power compensation control link, the integral gain coefficient K in the improved additional reactive power input PI controller can be reduced. I-Q , which can increase the droop coefficient K Qs , improve the reactive power response speed of D-STATCOM under transient conditions.

[0027] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of any one of the methods of D-STATCOM coordinated control for system short circuit faults are implemented.

[0028] A computer-readable storage medium having a computer program stored thereon, characterized in that when the computer program is executed by a processor, the steps of any one of the methods of D-STATCOM coordinated control method for system short circuit faults are implemented.

[0029] Beneficial effects of the present invention: After the present invention adopts the coordinated control method, when a short circuit fault occurs in the system, the reactive reference current sent by the reactive compensation device D-STATCOM to the inner loop control is more precise, and the signal input to the IGBT is also more accurate, so that the target voltage and reactive power compensation can be performed quickly, reducing the damage to the equipment caused by voltage sag.

[0030] After adopting the coordinated control method, after a short circuit fault occurs in the system, the reactive reference current sent by the reactive compensation device D-STATCOM to the inner loop control is more accurate, and the signal input to the IGBT is also more accurate. D-STATCOM can reduce the reactive power generated in a timely and rapid manner, reducing the degree of voltage overshoot after the fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 A main circuit topology diagram of a D-STATCOM connected to a distribution network in a D-STATCOM coordinated control method for a system short circuit fault provided by an embodiment of the present invention.

[0033] Figure 2 A diagram of D-STATCOM reactive power regulation of a D-STATCOM coordinated control method for a system short circuit fault provided by an embodiment of the present invention.

[0034] Figure 3 A D-STATCOM double closed-loop control diagram of a D-STATCOM coordinated control method for a system short-circuit fault is provided in one embodiment of the present invention.

[0035] Figure 4 A method flow chart of a D-STATCOM coordinated control method for system short circuit faults provided by an embodiment of the present invention.

[0036] Figure 5 A D-STATCOM control method diagram based on voltage transient change rate is provided for a D-STATCOM coordinated control method for a system short circuit fault according to an embodiment of the present invention.

[0037] Figure 6 A logic block diagram of a fault judgment module of a D-STATCOM coordinated control method for a system short circuit fault is provided in one embodiment of the present invention.

[0038] Figure 7 A transient fast reactive power compensation control diagram of a D-STATCOM coordinated control method for a system short circuit fault is provided in accordance with an embodiment of the present invention.

[0039] Figure 8A fast reactive power-voltage compensation control characteristic diagram of a D-STATCOM coordinated control method for a system short circuit fault is provided in one embodiment of the present invention.

[0040] Fig. 9 A system grid diagram of a D-STATCOM coordinated control method for system short circuit faults provided by an embodiment of the present invention.

[0041] Fig.10 A simulation result of a single-phase grounding fault grounding resistance of 1.5Ω for a D-STATCOM coordinated control method for a system short circuit fault provided by an embodiment of the present invention.

[0042] Fig.11 A simulation result of a single-phase grounding fault grounding resistance of 1.6Ω for a D-STATCOM coordinated control method for a system short circuit fault provided by an embodiment of the present invention.

[0043] Fig.12 A simulation result of a three-phase grounding fault with a grounding resistance of 1.5Ω for a D-STATCOM coordinated control method for a system short circuit fault provided by an embodiment of the present invention.

[0044] Fig.13 A simulation result of a three-phase grounding fault grounding resistance of 1.6Ω for a D-STATCOM coordinated control method for a system short circuit fault provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0046] Example 1, reference Figure 1 - Figure 8 , which is the first embodiment of the present invention. This embodiment provides a D-STATCOM coordinated control method for bus voltage sag when a short circuit fault occurs in the system. It is based on the traditional dual closed-loop control strategy, the outer loop realizes voltage control, and the inner loop quickly tracks the current. The method introduces a control link based on the bus voltage change rate and a transient fast reactive power compensation control link in the outer loop voltage control, and the q-axis reactive reference current output in the outer loop control is modified and sent to the inner loop control to generate a control signal input into the SPWM to obtain the trigger signal of the IGBT, so as to control the D-STATCOM to emit reactive power to compensate the voltage.

[0047] This embodiment first introduces the structure, working principle and existing control method of D-STACOM.

[0048] In D-STATCOM, voltage-type bridge converter is often used, capacitors are connected in parallel on the DC side, and filters are connected to the power grid on the AC side. The main circuit topology of its access to the distribution network is as follows: Figure 1 As shown. Figure 1 In the figure, the voltage-type inverter is connected to the distribution network via a resistor R and an inductor L. u and i are the grid voltage and grid current (subscripts a, b, and c represent the three phases, respectively), C is the DC side capacitor of the inverter, and u dc Indicates the voltage of the DC link capacitor.

[0049] The basic working principle of D-STATCOM is as follows: the converter converts the voltage on the DC side into an output voltage with the same frequency as the grid side according to the control strategy, so that the STATCOM device can be equivalently regarded as an AC voltage source with controllable amplitude and phase. The difference between the output voltage and the system voltage generates a current at the connection reactor. If the current leads the system voltage, the device will generate capacitive reactive power; if the current lags the system voltage, the device will generate inductive reactive power. The reactive power regulation is as follows: Figure 2 shown.

[0050] The traditional D-STATCOM control strategy is a classic dual closed-loop control, which consists of a current inner loop and a voltage outer loop. Figure 3 As shown. The outer loop controller controls the DC voltage, and the control signal it outputs is used as the reference instruction for the reactive current and active current (or reactive power and active power) required by the inner loop controller. The inner loop tracks the instruction signal. The output value of the inner loop is modulated to generate a synchronous drive signal, thereby establishing a linear relationship between the converter output current and the active and reactive power instructions, achieving the purpose of rapid current control.

[0051] Depend on Figure 3 It can be seen that in the voltage control link, the difference between the bus voltage setting value and the actual value is obtained through PI control and sent to the inner loop control, and then the converter is controlled to output or absorb the required reactive power. The output reactive current setting value is shown in the formula:

[0052] i qref =(U cref -U c )×(K P +K I / s)

[0053] =K P ×(U cref -U c )+(U cref -U c )×KI / s

[0054] =G P +G I

[0055] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control.

[0056] Specifically, Figure 4 As shown, the method of the present invention comprises the following steps:

[0057] S1. Obtain the detected bus voltage and current, and send the detected voltage to the fault judgment module after differentiation. The fault judgment module controls the input of the undervoltage module and the overvoltage module.

[0058] S2, sending the additional component generated after the undervoltage module or overvoltage module is put into operation to the D-STATCOM outer loop q-axis voltage control;

[0059] S3, the reactive input component generated by the transient fast reactive compensation control link is sent to the outer loop q-axis voltage control after PI control;

[0060] S4. The q-axis reactive reference current outputted from the modified outer loop control is fed into the inner loop control to generate a control signal which is inputted into the SPWM to obtain a trigger signal of the IGBT, and the D-STATCOM is controlled to emit reactive power to compensate the voltage.

[0061] The voltage coordination control method is put into operation only when a fault is judged to occur. The D-STATCOM control method based on the voltage transient change rate is as follows: Figure 5 As shown, the logic block diagram of the fault judgment module is as follows Figure 6 As shown. The bus minimum reference voltage U minref Take 0.98pu, the bus maximum reference voltage U maxref Take 1.02pu, the minimum reference value of bus voltage change rate Take -0.1, the maximum reference value of bus voltage change rate Take 0.1, so that voltage coordination control can be started earlier when a voltage sag occurs, reducing the impact of communication delay.

[0062] The purpose of this value is to reduce the impact of communication delay caused by the D-STATCOM's own structure, start the undervoltage module in the voltage coordination control faster in the event of a fault, and start the overvoltage module in the coordination control faster after a fault, so as to quickly increase or decrease reactive power to stabilize the bus voltage.

[0063] The logic flow of the fault judgment module is as follows: first, measure the bus voltage U c , then calculate the voltage change rate dU c / dt, when a fault occurs, the bus voltage will drop temporarily and the voltage change rate will decrease sharply. and U c <U minref When all the above conditions are met, the undervoltage module is put into use. After the fault disappears, the bus voltage rises rapidly due to the large reactive power generated by the D-STATCOM during the fault. and U c >U maxref When all conditions are met at the same time, the overvoltage module is put into use, and after the voltage returns to normal, normal voltage control is restored and the system resumes stable operation.

[0064] When there is no short circuit fault in the system, The undervoltage module is not enabled; when a short circuit occurs in the system, it is detected and U c <U minref When these two conditions are met at the same time, the undervoltage module is activated to suppress voltage sag, and the reactive reference current output by the q axis in the outer loop control is:

[0065]

[0066] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I1 K is the integral time constant of the undervoltage module PI controller; P1 is the proportional coefficient of the undervoltage module PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control.

[0067] When the bus voltage is lower than the normal value due to a short circuit fault and tends to decrease rapidly, is a positive value. After PI control, the positive voltage compensation value is added to the voltage link. Then, the additional component of the outer loop reactive current G is obtained by PI in the voltage control. UAs the reactive current of the outer loop increases, STATCOM speeds up the reactive power generation rate, increases the reactive power generated, and better suppresses voltage sag.

[0068] During normal operation The overvoltage module is not enabled; when a fault is detected and U c >U maxref When the overvoltage module is turned on through the fault judgment module, the transient high voltage is suppressed. At this time, the reactive reference current value of the q-axis output in the outer loop control is:

[0069]

[0070] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I2 K is the integral time constant of the undervoltage module PI controller; P2 is the proportional coefficient of the undervoltage module PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control.

[0071] When the fault disappears, due to the excessive reactive power generated by the D-STATCOM, the bus voltage is higher than the normal value and tends to increase rapidly. It is a negative value. After PI control, the negative voltage compensation value is added to the voltage control link. Then, the outer loop reactive current additional component G is obtained through PI in voltage control. U The negative value reduces the reactive current sent to the inner loop to control the outer loop. As the outer loop reactive current decreases, STATCOM speeds up the reduction of reactive power output rate, better suppressing the voltage overshoot caused by excessive reactive power output.

[0072] Transient fast reactive power compensation control Figure 7 As shown in the figure, the q-axis reactive reference current input under transient fast reactive-voltage compensation control is:

[0073] i qref =[(U cref -U c )+(Q cref -Q c )×(K P-Q +K I-Q / s)]

[0074] ×(K P +K I / s)

[0075] Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I-Q K is the integral time constant of the transient fast reactive power-voltage compensation PI controller; P-Q is the proportional coefficient of the transient fast reactive power-voltage compensation PI controller; U cref is the reference value of bus voltage; Q cref is the bus reactive power reference voltage; Q c is the detected bus reactive power; U c To detect the bus voltage of the system.

[0076] The reactive input component is added to the q-axis voltage control of the STATCOM outer loop to form bus voltage-reactive droop control. Compared with the traditional method, in this improved method, the q-axis outer loop input characteristic is no longer a straight line with a slope of 0, but a bus voltage-reactive ratio characteristic with a specific slope. According to the droop control principle, the combined formula can be obtained;

[0077] U c =U cref -K Qs (Q ref -Q c )

[0078] Among them, K Qs is the droop coefficient of reactive power droop control; U cref is the reference value of bus voltage; Q cref is the bus reactive power reference voltage; Q c Detected bus reactive power; U c To detect the bus voltage of the system.

[0079] Fast reactive power-voltage compensation control characteristics such as Figure 8 As shown, K Qs is the slope of reactive voltage characteristic (K Qs1 <K Qs2 ), when the bus voltage is equal to the reference value, the STATCOM reactive output is 0; when the bus voltage drops to U c1 When point A has a droop coefficient of K Qs2 The operating point, C is the droop coefficient K Qs1 The horizontal coordinates of points A and C are Q s1 , Q s2 , we can see that Q s1 <Q s2 , indicating that the droop coefficient is K Qs2 When the reactive power output task undertaken by D-STATCOM is small, it is convenient to flexibly and reasonably control the reactive power output.

[0080] According to the above analysis, in the fast reactive power compensation control link, the integral gain coefficient K in the improved additional reactive power input PI controller can be reduced. I-Q , which can increase the droop coefficient K Qs , improve the reactive power response speed of D-STATCOM under transient conditions.

[0081] According to the above, in the fast reactive power compensation control link, the integral gain coefficient K in the improved additional reactive power input PI controller can be reduced. I-Q , which can increase the droop coefficient K Qs , improve the reactive power response speed of D-STATCOM under transient conditions.

[0082] Embodiment 2, the second embodiment of the present invention, is different from the previous embodiment in that:

[0083] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program code.

[0084] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as based on a computer, including a processor or other device that can fetch instructions from the instruction execution system, device or apparatus and execute instructions), or in conjunction with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with these instruction execution systems, devices or apparatuses.

[0085] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0086] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0087] Example 3, reference Fig. 9 - Fig.13 , which is the third embodiment of the present invention, based on the method described in the above embodiment 1, this embodiment provides the following example analysis.

[0088] A system simulation model of D-STATCOM was built in PACAD to verify the correctness and effectiveness of the above control method. The specific parameters are shown in Table 1. The system grid used is as follows: Fig. 9 As shown in the figure, the short-circuit fault types are the single-phase ground fault with the most occurrence in the distribution network and the three-phase ground short-circuit fault with the most damage for testing. The voltage values ​​mentioned in the simulation comparison are all per-unit values, and the voltage change rate is also the voltage per-unit value change rate. The differences in system components are not considered, and the three-phase parameters are symmetrical.

[0089] Table 1 Simulation system parameters

[0090] Parameter name Parameter Value Grid voltage level 110kV Grid frequency 50Hz DC link capacitor 3000uF D-STATCOM Capacity 10MVA Carrier frequency 1000Hz Equivalent Inductance 2mH Equivalent resistance 0.2Ω

[0091] This embodiment sets four scenario instances according to different fault types and grounding resistance values, as shown below:

[0092] At 1.5s, a single-phase grounding fault occurs at the busbar, the grounding resistance is 1.5Ω, and the fault duration is 0.1s. Fig.10This is the simulation result of a single-phase grounding fault with a grounding resistance of 1.5Ω.

[0093] At 1.5s, a single-phase grounding fault occurs at the busbar, the grounding resistance is 1.6Ω, and the fault duration is 0.1s. Fig.11 This is the simulation result of a single-phase grounding fault with a grounding resistance of 1.6Ω.

[0094] At 1.5s, the three-phase ground fault grounding resistance is set to 1.5Ω, the fault duration is 0.1s, and the three-phase ground fault grounding resistance is 1.5Ω. The simulation results are as follows: Fig.12 shown.

[0095] The simulation results of the three-phase ground fault grounding resistance of 1.6Ω at 1.5s and the fault duration of 0.1s and the three-phase ground fault grounding resistance of 1.6Ω are shown in the figure below. Fig.13 shown.

[0096] from Fig.10 It can be seen that when the grounding resistance of the busbar is 1.5Ω when a single-phase grounding fault occurs, the lowest transient low voltage value is 0.854pu when the conventional control method is used, and the lowest transient low voltage value is 0.88pu when the voltage coordination control method is used. The voltage coordination control method increases the lowest transient low voltage by 2.4% compared with the conventional control method. The highest transient high voltage using the conventional control method is 1.077pu, and the highest transient high voltage using the voltage coordination control method is 1.042pu, which is a decrease of 3.5%. And after the fault ends, it helps the system to restore the voltage to the normal operating level 0.18s in advance. The simulation results show that when a single-phase grounding fault occurs, the voltage coordination control method is better than the conventional control method in improving the transient low voltage, reducing the transient overvoltage, and helping the system to recover stable operation faster.

[0097] from Fig.11 It can be seen that when the grounding resistance of the busbar is 1.6Ω due to a single-phase grounding fault, the minimum transient low voltage value is 0.856pu and the maximum transient high voltage is 1.076pu when the conventional control method is used. The minimum transient low voltage is 0.897pu and the maximum transient high voltage is 1.036pu when the voltage coordination control method is used. Compared with the conventional control method, the voltage coordination control method increases the minimum transient low voltage by 4.1% and reduces the maximum transient high voltage by 4%. After the fault ends, it helps the system to restore the voltage to the normal operating level 0.2s in advance. It is better than the conventional control method in improving the transient low voltage, reducing the transient overvoltage, and helping the system to resume stable operation faster.

[0098] from Fig.12It can be seen that after a three-phase fault occurs on the bus, the lowest transient low voltage value is 0.778pu when the conventional control method is used, and the lowest transient low voltage value is 0.794pu when the voltage coordination control method is used, and the lowest transient low voltage is increased by 2.2%. The highest transient high voltage is 1.078pu when the conventional control method is used, and the highest transient high voltage is 1.039pu when the voltage coordination control method is used, which is reduced by 3.9%. After the fault ends, it helps the system to restore the voltage to the normal operating level 0.2s in advance. The simulation results show that when a three-phase fault occurs, the voltage coordination control method is better than the conventional control method in improving transient low voltage, reducing transient overvoltage, and helping the system to recover stable operation faster.

[0099] from Fig.13 It can be seen that the lowest transient low voltage value is 0.779pu and the highest transient high voltage is 1.092pu when the conventional control method is used. The lowest transient low voltage is 0.804pu and the highest transient high voltage is 1.032pu when the voltage coordination control method is used. The voltage coordination control method increases the lowest transient low voltage by 2.5% and reduces the highest transient high voltage by 6% compared with the conventional control method. It helps the system to restore the voltage to the normal operating level 0.15s in advance after the fault ends. The simulation results show that when a three-phase fault occurs, the voltage coordination control method is superior to the conventional control method in improving the transient low voltage, reducing the transient overvoltage, and helping the system to recover stable operation faster.

[0100] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A D-STATCOM coordinated control method for system short circuit fault, characterized by: include, Based on the dual closed-loop control strategy, the outer loop realizes voltage coordinated control, and the inner loop quickly tracks the current. The control link based on the bus voltage change rate and the transient fast reactive power compensation control link are introduced into the outer loop voltage control. After the q-axis reactive reference current output in the outer loop control is modified, it is sent to the inner loop control to generate a control signal input into the SPWM to obtain the trigger signal of the IGBT, and control the D-STATCOM to emit reactive power to compensate the voltage. The detected bus voltage and current are obtained, and the detected voltage is derived and sent to the fault judgment module to determine whether a fault occurs, and the fault judgment module controls the input of the undervoltage module and the overvoltage module; The additional component generated after the undervoltage module or overvoltage module is put into operation is sent to the q-axis voltage control of the outer loop of D-STATCOM; The reactive input component generated by the transient fast reactive compensation control link is sent to the outer loop q-axis voltage control after PI control; The q-axis reactive reference current output from the modified outer loop control is sent to the inner loop control to generate a control signal which is input into the SPWM to obtain the trigger signal of the IGBT, and the D-STATCOM is controlled to emit a reactive power compensation voltage.

2. A D-STATCOM coordinated control method for system short circuit fault according to claim 1, characterized in that: The voltage coordination control is put into operation when a fault is determined to occur, and the bus minimum reference voltage U minref Take 0.98pu, the bus maximum reference voltage U maxref Take 1.02pu, the minimum reference value of bus voltage change rate Take -0.1, and the maximum reference value of bus voltage change rate is 0.

1.

3. A D-STATCOM coordinated control method for system short circuit fault according to claim 2, characterized in that: The fault judgment module includes: measuring the bus voltage U c , calculate the voltage change rate dU c / dt, when a fault occurs, detected and U c <U minref When both conditions are met, the undervoltage module is put into use. When the fault disappears, it is detected and U c >U maxref When all conditions are met at the same time, the overvoltage module is put into use, and after the voltage returns to normal, normal voltage control is restored and the system resumes stable operation.

4. A D-STATCOM coordinated control method for system short circuit fault according to claim 3, characterized in that: The undervoltage module includes: when there is no short circuit fault in the system, The undervoltage module is not enabled; When a short circuit occurs in the system, it is detected and U c <U minref When both conditions are met, the undervoltage module is activated to suppress voltage sag, and the reactive reference current output by the q-axis in the outer loop control is: Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I1 K is the integral time constant of the undervoltage module PI controller; P1 is the proportional coefficient of the undervoltage module PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control; When the bus voltage is lower than the normal value due to a short circuit fault and has a tendency to decrease, is a positive value. After PI control, the positive voltage compensation value is added to the voltage link. The additional component of the outer loop reactive current G obtained by PI in voltage control U A positive value increases the reactive current sent to the inner loop to control the outer loop.

5. A D-STATCOM coordinated control method for system short circuit fault according to claim 4, characterized in that: The overvoltage module includes: The overvoltage module is not enabled; When a fault is detected and U c >U maxref When the overvoltage module is turned on through the fault judgment module, the transient high voltage is suppressed. The reactive reference current value of the q-axis output in the outer loop control is: Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I2 K is the integral time constant of the undervoltage module PI controller; P2 is the proportional coefficient of the undervoltage module PI controller; G P is the proportional component of PI output in voltage control; G I It is the integral component of PI output in voltage control.

6. A D-STATCOM coordinated control method for system short circuit fault according to claim 5, characterized in that: The voltage module also includes, when the bus voltage is higher than the normal value and has an increasing trend due to the excessive reactive power generated by the D-STATCOM after the fault disappears, It is a negative value. After PI control, the negative voltage compensation value is added to the voltage control link. The additional component of the outer loop reactive current G obtained by PI in the voltage control is U A negative value reduces the reactive current sent to the inner loop to control the outer loop.

7. A D-STATCOM coordinated control method for system short circuit fault according to claim 6, characterized in that: The q-axis reactive reference current is expressed as, i qref =[(U cref -U c )+(Q cref -Q c )×(K P-Q +K I-Q / s)] ×(K P +K I / s) Among them, K P is the proportional coefficient of the PI controller; K I is the integral time constant of the PI controller; K I-Q K is the integral time constant of the transient fast reactive power-voltage compensation PI controller; P-Q is the proportional coefficient of the transient fast reactive power-voltage compensation PI controller; U cref is the reference value of bus voltage; Q cref is the bus reactive power reference voltage; Q c is the detected bus reactive power; U c To detect the bus voltage of the system.

8. A D-STATCOM coordinated control method for system short circuit fault according to claim 7, characterized in that: Adding reactive input component to the q-axis voltage control of the STATCOM outer loop forms bus voltage-reactive droop control. According to the droop control principle, U c =U cref -K Qs (Q ref -Q c ) Among them, K Qs is the droop coefficient of reactive power droop control; U cref is the reference value of bus voltage; Q cref is the bus reactive power reference voltage; Q c Detected bus reactive power.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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