FTL table item full-hardware acceleration module method based on logic address merging and sorting

Abstract

The invention belongs to the technical field of data center level or industrial level SSD arrays, and particularly relates to an FTL table item full-hardware acceleration module method based on logical address merge sorting, which comprises the following steps: a TU module receives a logical address sequence processed by a controller at a host end, and further splits logical addresses into a new mapping relationship; the CPU does not directly access table items in the dynamic random access memory, access is controlled through hardware, the hardware and the CPU work at the same time, the running efficiency of the CPU is improved, the code burden is reduced, code logic control is reduced, each command sequence only needs to be inserted into the TU for one time, follow-up operation is completed through the hardware, the use efficiency of the dynamic random access memory is improved, and the service life of the dynamic random access memory is prolonged. According to the method and the system, the adjacent mapping relation can be updated once by taking burst (a minimum trigger unit of once DMA transmission) as a unit, and for a high-performance SSD, more idle time slices can be reserved for a CPU to process functions such as regular routing inspection, read interference and Garage Collision, so that the utilization rate of the CPU is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of industrial-grade SSD arrays, and in particular relates to a FTL table entry full hardware acceleration module method based on logical address merge sorting. Background Art

[0002] Data center-level solid state drives or industrial-level hard drives usually have dynamic random access memory to improve the host-side reading and access performance. In actual usage scenarios, when a piece of data is written, the corresponding first-level table entry needs to first read the original mapping relationship from the dynamic random access memory, reduce the number of valid data in the original data block of the first-level table entry, and then write the mapping relationship corresponding to the new data into the dynamic random access memory, and mark the current first-level table entry as a modified table entry. The firmware needs to access this table entry as a snapshot content to the Flash, and usually this flag is also placed in the dynamic random access memory. In addition, the written data also needs to write the corresponding reverse table in the dynamic random access memory, indicating the logical address of the current physical address, which is used to determine whether the current data is valid during Garbage Collection. It can be seen that when the actual controller is operating, the writing of a 4KB data usually includes the reading of a logical address dynamic random access memory data and the writing of two or three dynamic random access memory data, and will change the reading and access direction of the dynamic random access memory data, seriously affecting the efficiency of the dynamic random access memory.

[0003] If the CPU is used to update the mapping relationship in real time, a large amount of CPU access overhead will be introduced, resulting in reduced efficiency in searching and updating the mapping relationship, thereby reducing the operating efficiency of the FTL CPU and affecting the performance of reading and accessing.

[0004] In addition to updating the mapping relationship in real time, the existing technology mainly solves the problem by increasing the frequency of dynamic random access memory or avoiding it through code optimization solutions. The first-level table items use static random access memory to temporarily cache dynamic random access memory. The sequential read and write table items are moved to the static random access memory through the hardware bus, and then the static random access memory is accessed. After the size allocated by the static random access memory is updated, it is moved to the dynamic random access memory as a whole through the hardware bus. For the table items marked as modified, it records whether the first-level table items actually updated for each piece of data are the same. If they are the same, they are not set.

[0005] The defects of this method include but are not limited to: the real-time update of the mapping relationship by the CPU will increase the CPU burden; the frequency of the dynamic random access memory is fixed and cannot be increased without limit; the example is only effective for the sequential read and write lookup of the mapping relationship and the update of the mapping relationship for large data blocks. For random reads and accesses, the positions of the read, write, and table update cannot be predicted, so this optimization scheme cannot be used; the short-term caching of the dynamic random access memory by the static random access memory strongly depends on the speed of hardware transfer. Since the hardware bus transfer and the CPU operation are serial operations, it consumes a certain amount of CPU performance and needs to satisfy tM (transfer time) + tS (access static random access memory) < tD (access dynamic random access memory); it increases the code burden. The CPU needs to determine whether the transfer scenario is met. If misjudged, it will increase the CPU burden. Summary of the Invention

[0006] The purpose of the present invention is to provide a full-hardware acceleration module method for FTL table entries based on logical address merge sorting, aiming to solve the problems of the CPU real-time update of the mapping relationship, limited frequency increase, the short-term caching of the dynamic random access memory by the static random access memory being only effective for the sequential read and write lookup of the mapping relationship and the update of the mapping relationship for large data blocks, the inability to predict the positions of the read, write, and table update for random reads and accesses, the inability to accelerate, the strong dependence on the speed of hardware transfer, the hardware bus transfer and the CPU operation being serial operations, consuming a certain amount of CPU performance, and the CPU needing to determine whether the transfer scenario is met. If misjudged, it will increase the CPU burden.

[0007] To achieve the above purpose, the present invention provides the following technical solution: A full-hardware acceleration module method for FTL table entries based on logical address merge sorting, including:

[0008] The TU module receives the logical address sequence and disassembles the logical address into a new valid mapping relationship;

[0009] The commands disassembled by the TU module are merged and sorted by the L2PA module to sort the logical address sequence in an unknown state;

[0010] The P2LA module saves the logical address information according to the actual physical unit write order for the logical addresses generated by disassembling the TU module;

[0011] The TMU module is a hardware module that actually interacts with the dynamic random access memory to update the newly generated mapping relationship;

[0012] The VM module interacts with the TMU module to update the effective data volume of the VB (Virtual Block).

[0013] As a preferred method of the FTL table entry full hardware acceleration module method based on logical address merge sorting of the present invention, after the TU module disassembles the logical address command sequence, it is refreshed to the L2PA module and the P2LA module at an appropriate time, and the timing is as follows:

[0014] 1) When the accumulated logical address sequence exceeds the size of the internal cache;

[0015] 2) The accumulated number of logical addresses exceeds a certain fixed value;

[0016] 3) Send the Flush command.

[0017] As a preferred method of the FTL table entry full hardware acceleration module method based on logical address merge sorting of the present invention, the L2PA module sorting method is to assume that each physical unit is a mapping relationship between a pair of logical addresses and physical addresses, the first layer has N groups of sorted physical units, and each layer except the first layer has M groups of sorted physical unit sequences, and there are K layers of logical address sorting, then the physical units that need to be stored in each layer are:

[0018] S=N*M K-1

[0019] The physical units stored in each layer are merged and sorted before being moved to the next layer.

[0020] As a preferred method of the FTL table entry full hardware acceleration module method based on logical address merge sorting of the present invention, the L2PA module flushes the K-th layer data to the TMU module to perform table entry insertion cache operation each time. During the table entry insertion cache, the lower K-1 layer continues to receive the data inserted by the TU module until all the data of the K-1 layer is full, and then the TU module is paused. In addition, L2PA continues to determine whether the currently inserted logical address is continuously inserted according to the sorting rules. If the logical address is a sequential operation, it is not sorted and directly merged to the next layer.

[0021] As a preferred method of the present invention for a full hardware acceleration module of FTL table entries based on logical address merge sorting, the logical address stored by the P2LA module is finally inserted into a storage location dynamic random access memory or static random access memory.

[0022] As a preferred method of the present invention for a full hardware acceleration module of FTL table entries based on logical address merging and sorting, the TMU module can calculate the position of the first-level table entry that needs to be updated according to the table entry start address set by the internal register and the actual unit of the logical address in the L2PA. Since the table entries in the dynamic random access memory are stored in the order of the logical addresses, when the continuous logical addresses inserted out of order are sorted and merged, they can be merged and updated to the dynamic random access memory, thereby improving the data transmission efficiency of the dynamic random access memory.

[0023] As a preferred method of the FTL table entry full hardware acceleration module based on logical address merge sorting of the present invention, when the TMU module receives the command inserted from the L2PA module, the VM module accesses the mapping relationship in the current dynamic random access memory according to the logical address, obtains the physical address of the original data, and updates the VPC (Valid Page Count: the valid data size of the VB). Usually, the valid data size is stored in the static random access memory and can be updated according to the address set by the internal register.

[0024] As a preferred method of the FTL table entry full hardware acceleration module based on logical address merge sorting of the present invention, the hardware in the TU module controls access to the dynamic random access memory, the CPU does not directly access the dynamic random access memory, and the hardware and CPU work synchronously.

[0025] As a preferred method of the FTL table entry full hardware acceleration module based on logical address merge sorting of the present invention, the adjacent mapping relationship in the storage location (dynamic random access memory or static random access memory) can be updated once in burst units without being split into multiple read and write storage location commands.

[0026] As a preferred method of the FTL table entry full hardware acceleration module based on logical address merge sorting of the present invention, the TU module disassembles the logical address command sequence (starting logical address, starting physical address, command length) into multiple pairs of mapping relationships between logical addresses and physical addresses in units of 4KB according to the command length, and inserts them into L2PA (L2P Array) and P2LA (P2L Array).

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The beneficial effects of the present invention are: the CPU does not directly access the table items in the dynamic random access memory, but controls the access through hardware. The hardware and the CPU work simultaneously, which improves the operating efficiency of the CPU, reduces the code burden, reduces the code logic control, and each command sequence only needs to be inserted into the TU once, and all subsequent operations are completed by hardware, which improves the utilization efficiency of the dynamic random access memory. For adjacent mapping relationships, they can be updated once in units of burst (the minimum trigger unit for a DMA transfer). For high-performance SSDs, more idle time slices can be reserved for the CPU to process functions such as timed inspections, read interference, and GarbageCollection, thereby improving CPU utilization. In random mode, adjacent logical address data are merged and inserted, and the data of the same first-level table item is only marked once as a second-level table item. Both the forward table and the reverse table can be updated by hardware and are no longer accessed by the CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0030] Figure 1 It is a schematic diagram of the process of the present invention;

[0031] Figure 2 It is a schematic diagram of a TU module of the present invention;

[0032] Figure 3 This is a schematic diagram of the L2PA module of the present invention;

[0033] Figure 4 It is a schematic diagram of the P2LA module of the present invention;

[0034] Figure 5 It is a schematic diagram of the TMU module of the present invention;

[0035] Figure 6 Schematic diagram of the VM module of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] See also Figure 1-6 The present invention provides the following technical solution: a FTL table entry full hardware acceleration module method based on logical address merge sorting, comprising:

[0038] The TU module receives a logical address sequence and decomposes the logical address into a new valid mapping relationship;

[0039] The commands disassembled by the TU module are merged and sorted by the L2PA module, and the logical address sequences of unknown states are sorted;

[0040] The P2LA module disassembles the logical address generated by the TU module and saves the logical address information according to the actual physical unit writing order;

[0041] The TMU module is a hardware module that actually interacts with the dynamic random access memory and updates the newly generated mapping relationship;

[0042] The VM module interacts with the TMU module to update the effective data volume of the VB (Virtual Block).

[0043] Preferably, after the TU module disassembles the logical address sequence, it is flashed to the L2PA module and the P2LA module at an appropriate time, and the timing is as follows:

[0044] 1) When the accumulated logical address sequence exceeds the size of the internal cache;

[0045] 2) The accumulated number of logical addresses exceeds a certain fixed value;

[0046] 3) Send the Flush command;

[0047] Preferably, the L2PA module sorting method is to assume that each physical unit is a mapping relationship between a pair of logical addresses and physical addresses, the first layer has N groups of sorted physical units, and each layer except the first layer has M groups of sorted physical unit sequences, and there are K layers of logical address sorting. Then, the physical units that need to be stored in each layer are:

[0048] S=N*M K-1

[0049] The physical units stored in each layer are merged and sorted before being moved to the next layer.

[0050] Preferably: the L2PA module flushes the K-th layer data to the TMU module each time to perform table entry insertion cache operation. During the table entry insertion cache period, the lower K-1 layer continues to receive the data inserted by the TU module until all the data of the K-1 layer is full, and then the TU module is paused. In addition, the L2PA continuously determines whether the currently inserted logical address is continuously inserted according to the sorting rules. If the logical address is a sequential operation, it is not sorted and directly merged into the next layer.

[0051] Preferably: the logical address saved by the P2LA module is finally inserted into the storage location dynamic random access memory or static random access memory. Since the writing is sequential, the function still supports storing multiple writes at one time, and multiple groups of data can be written to the dynamic random access memory in one operation, instead of only writing one group each time, which significantly improves the efficiency of data writing and reduces the waiting time of the CPU or other processing units.

[0052] Preferably: the TMU module can calculate the position of the actual changed first-level table entry corresponding to LAA according to the table entry starting address set by the internal register. For continuous data, a merge insertion method is adopted, and merge sort is used to sort the FTL table entries, which can optimize the storage structure of the table entries and improve the efficiency of searching and updating the table entries.

[0053] Preferably: the TMU module can calculate the position of the first-level table entry that needs to be updated according to the table entry start address set in the internal register and the actual unit of the logical address in the L2PA. Since the table entries in the dynamic random access memory are stored in the order of the logical address, when the continuous logical addresses inserted out of order are sorted and merged, they can be merged and updated to the dynamic random access memory, thereby improving the data transmission efficiency of the dynamic random access memory.

[0054] Preferably: the hardware in the TU module controls access, the CPU does not directly access the dynamic random access memory, the hardware and the CPU work simultaneously, and the multi-core or multi-channel characteristics of the hardware module are utilized to achieve parallel sorting and merging of multiple subsequences.

[0055] Preferably: when the TMU module receives the command inserted from the L2PA module, the VM module accesses the mapping relationship in the current dynamic random access memory according to the logical address, obtains the physical address of the original data, and updates VPC (Valid PageCount: the valid data size of the VB). Usually, the valid data size is stored in the static random access memory and can be updated according to the address set by the internal register.

[0056] Preferably: in the TU module, hardware controls access to the dynamic random access memory, the CPU does not directly access the dynamic random access memory, and the hardware and the CPU work synchronously.

[0057] The specific operation principle of the present invention is as follows: insert the command sequence into TU (Translayer Unit), the hardware will disassemble the logical address command sequence (starting logical address, starting physical address, command length) into a new mapping relationship between the logical address and the physical address with a granularity of 4KB according to the command length, and insert it into L2PA (L2P Array) and P2LA (P2L Array). The hardware sorts the mapping relationship passed in by TU according to the logical address by merge sorting, and then inserts it into TMU (Table Manage Unit). TMU interacts with VM (VPC Manage), updates the VPC of the VB, and interacts with dynamic random access memory at the same time, merges the physical address of the logical address sequence into the dynamic random access memory, and marks the modified primary table entry in the secondary table entry, so as to improve the performance of searching and updating the mapping relationship. Each command sequence only needs to be inserted into TU once, and all subsequent hardware FTL Cores are completed, which improves the utilization efficiency of dynamic random access memory. For high-performance SSDs, more idle time slices can be reserved for the CPU to process functions such as timed inspection, read interference and Garbage Collection, thereby improving CPU utilization.

[0058] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for full hardware acceleration module of FTL table entries based on logical address merge sorting, characterized in that: include: The TU module receives a logical address sequence and decomposes the logical address into a new valid mapping relationship; The commands disassembled by the TU module are merged and sorted by the L2PA module, and the logical address sequences of unknown states are sorted; The P2LA module disassembles the logical address generated by the TU module and saves the logical address information according to the actual physical unit writing order; The TMU module is a hardware module that actually interacts with the dynamic random access memory and updates the newly generated mapping relationship; The VM module interacts with the TMU module to update the effective data volume of the VB (Virtual Block).

2. The method of the FTL table entry full hardware acceleration module based on logical address merge sorting according to claim 1, characterized in that: After the TU module disassembles the logical address sequence, it is flashed to the L2PA module and the P2LA module at the appropriate time. The timing is as follows: 1) When the accumulated logical address sequence exceeds the size of the internal cache; 2) The accumulated number of logical addresses exceeds a certain fixed value; 3) Send the Flush command.

3. The method of the FTL table entry full hardware acceleration module based on logical address merge sorting according to claim 1, characterized in that: The L2PA module sorting method assumes that each physical unit is a mapping relationship between a logical address and a physical address. The first layer has N groups of sorted physical units. Except for the first layer, each layer has M groups of sorted physical unit sequences. There are K layers of logical address sorting in total. Then, the physical units that need to be stored in each layer are: S=N*MK-1 The physical units stored in each layer are merged and sorted before being moved to the next layer.

4. The method of the FTL table entry full hardware acceleration module based on logical address merge sorting according to claim 1, characterized in that: The L2PA module flushes the K-th layer data to the TMU module for table entry insertion cache operation each time. During the table entry insertion cache period, the lower K-1 layer continues to receive the data inserted by the TU module until all the data of the K-1 layer is full, then the TU module is paused. In addition, the L2PA continuously determines whether the currently inserted logical address is continuously inserted according to the sorting rules. If the logical address is a sequential operation, it is not sorted and directly merged into the next layer.

5. The method of full hardware acceleration module of FTL table entries based on logical address merge sorting according to claim 1, characterized in that: The logic address stored in the P2LA module is finally inserted into the storage location dynamic random access memory or static random access memory.

6. The method of full hardware acceleration module of FTL table entries based on logical address merge sorting according to claim 1, characterized in that: The TMU module can calculate the location of the first-level table entry that needs to be updated based on the table entry start address set by the internal register and the actual unit of the logical address in the L2PA. Since the table entries in the dynamic random access memory are stored in the order of the logical address, when the continuous logical addresses inserted out of order are sorted and merged, they can be merged and updated to the dynamic random access memory, thereby improving the data transmission efficiency of the dynamic random access memory.

7. The method of full hardware acceleration module of FTL table entries based on logical address merge sorting according to claim 1, characterized in that: When the TMU module receives the command inserted from the L2PA module, the VM module accesses the mapping relationship in the current dynamic random access memory according to the logical address, obtains the physical address of the original data, and updates the VPC (Valid Page Count: the valid data size of the VB). Usually, the valid data size is stored in the static random access memory and can be updated according to the address set by the internal register.

8. The method of full hardware acceleration module of FTL table entries based on logical address merge sorting according to claim 1, characterized in that: The hardware in the TU module controls access to the dynamic random access memory, the CPU does not directly access the dynamic random access memory, and the hardware and the CPU work synchronously.

9. The method of full hardware acceleration module of FTL table entries based on logical address merge sorting according to claim 5, characterized in that: The adjacent mapping relationships in the storage location (dynamic random access memory or static random access memory) can be updated once in burst units without being split into multiple commands for reading and writing the storage location.

10. The method of full hardware acceleration module of FTL table entries based on logical address merge sorting according to claim 1, characterized in that: The TU module disassembles the logical address command sequence (starting logical address, starting physical address, command length) into multiple pairs of mapping relationships between logical addresses and physical addresses in units of 4KB according to the command length, and inserts them into L2PA (L2P Array) and P2LA (P2L Array).

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