Photoelectric co-packaging structure based on embedded active silicon bridge

Abstract

The invention provides a photoelectric co-packaging structure based on an embedded active silicon bridge, and the photoelectric co-packaging structure based on the embedded active silicon bridge comprises the embedded active silicon bridge and a host chip, and the host chip is arranged on the embedded active silicon bridge. And a photonic integrated chip, an electronic integrated chip or a monolithic photoelectric integrated chip is integrated in the embedded active silicon bridge. According to the photoelectric co-packaging structure based on the embedded active silicon bridge provided by the embodiment of the invention, the communication efficiency between the host chip and the optical engine is improved; a signal path is shortened, and flexible and efficient signal transmission is realized; functional modules of power management, signal management, input and output expansion and the like can be integrated, and system signal integrity and power integrity are enhanced; and meanwhile, the preparation and integration cost of the large-size adapter plate is reduced, the yield is improved, and high-function-density integration is realized.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to an optoelectronic co-packaging structure based on an embedded active silicon bridge. Background Art

[0002] Chip technology is a technology that uses advanced packaging methods to heterogeneously integrate chips with different processes / functions. The key to silicon photonics system integration is to form effective signal interconnection between silicon photonics chips and electrical chips.

[0003] Co-Packaged Optics (CPO) is a multi-chip heterogeneous integrated packaging method used to achieve the integration between an optical engine (OE) composed of a photonic integrated chip (PIC) and an electronic integrated chip (EIC) and an application specific integrated circuit (ASIC). In the prior art, the OE structure and the host ASIC need to be interconnected using a packaging substrate or a passive adapter board assembly, and there is still a certain communication distance between the OE and the host ASIC. Therefore, how to propose an optoelectronic co-packaging structure that can further shorten the communication distance between the OE and the host ASIC has become an important issue that needs to be urgently solved in this field. Summary of the invention

[0004] In view of the problems in the prior art, an embodiment of the present invention provides an optoelectronic co-packaging structure based on an embedded active silicon bridge, which can at least partially solve the problems in the prior art.

[0005] The present invention proposes an optoelectronic co-packaging structure based on an embedded active silicon bridge, comprising an embedded active silicon bridge and a host chip, wherein:

[0006] The host chip is arranged on the embedded active silicon bridge, and a photonic integrated chip, an electronic integrated chip or a monolithic optoelectronic integrated chip is integrated in the embedded active silicon bridge.

[0007] Furthermore, the embedded active silicon bridge comprises a horizontal interconnection layer, and the horizontal interconnection layer is arranged on a surface of the embedded active silicon bridge.

[0008] Further, the horizontal interconnect layer includes a second redistribution layer and / or an optical waveguide.

[0009] Furthermore, a photonic integrated chip is integrated in the embedded active silicon bridge, the electronic integrated chip is arranged on the embedded active silicon bridge, and the host chip is electrically connected to the photonic integrated chip and the electronic integrated chip respectively.

[0010] Furthermore, an electronic integrated chip is integrated in the embedded active silicon bridge, the photon integrated chip is arranged on the embedded active silicon bridge, and the host chip is electrically connected to the photon integrated chip and the electronic integrated chip respectively.

[0011] Furthermore, the host chip includes computing unit core particles and / or storage unit core particles, and the computing unit core particles and / or storage unit core particles are respectively bonded to the embedded active silicon bridge, or integrated on the embedded active silicon bridge after three-dimensional stacking.

[0012] Furthermore, the optoelectronic co-packaging structure based on the embedded active silicon bridge provided by an embodiment of the present invention also includes a passive adapter board, which is arranged on the embedded active silicon bridge, and the passive adapter board includes a first redistribution layer, and the first redistribution layer is arranged on the surface of the passive adapter board; the host chip includes computing unit core particles and / or storage unit core particles, and the computing unit core particles and / or storage unit core particles are respectively bonded to the passive adapter board, or integrated on the passive adapter board after three-dimensional stacking.

[0013] Furthermore, through silicon vias are provided in the passive adapter board to realize electrical connection between the computing unit core grain and / or the storage unit core grain and the photonic integrated chip, electronic integrated chip or monolithic optoelectronic integrated chip integrated in the embedded active silicon bridge.

[0014] Furthermore, the passive adapter board is bonded to the embedded active silicon bridge.

[0015] Furthermore, the embedded active silicon bridge integrates passive components.

[0016] Furthermore, the embedded active silicon bridge integrates a through-hole structure for vertical interconnection.

[0017] Furthermore, the host chip is bonded to the embedded active silicon bridge via bump bonding, or hybrid bonding is performed on the embedded active silicon bridge.

[0018] Furthermore, at least one of a power management module, a signal management module and an electrostatic protection module is integrated on the embedded active silicon bridge.

[0019] The optoelectronic co-packaging structure based on the embedded active silicon bridge provided by the embodiment of the present invention includes an embedded active silicon bridge and a host chip, wherein the host chip is arranged on the embedded active silicon bridge, and the embedded active silicon bridge integrates a photonic integrated chip, an electronic integrated chip or a monolithic light engine, thereby shortening the communication distance between the host chip and the light engine and improving the communication efficiency between the host chip and the OE. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0021] Figure 1 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the first embodiment of the present invention.

[0022] Figure 2 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a second embodiment of the present invention.

[0023] Figure 3 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a third embodiment of the present invention.

[0024] Figure 4 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a fourth embodiment of the present invention.

[0025] Figure 5 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the fifth embodiment of the present invention.

[0026] Figure 6 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a sixth embodiment of the present invention.

[0027] Figure 7 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the seventh embodiment of the present invention.

[0028] Figure 8 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the eighth embodiment of the present invention.

[0029] Fig. 9 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the ninth embodiment of the present invention.

[0030] Fig.10 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the tenth embodiment of the present invention.

[0031] Fig.11 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the eleventh embodiment of the present invention.

[0032] Fig.12 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the twelfth embodiment of the present invention.

[0033] Fig.13 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by the thirteenth embodiment of the present invention.

[0034] Fig.14 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the fourteenth embodiment of the present invention.

[0035] Fig.15 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the fifteenth embodiment of the present invention.

[0036] Fig.16 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the sixteenth embodiment of the present invention.

[0037] Fig.17 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the seventeenth embodiment of the present invention.

[0038] Fig.18 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the eighteenth embodiment of the present invention.

[0039] Fig.19 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the nineteenth embodiment of the present invention.

[0040] Fig. 20 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the twentieth embodiment of the present invention.

[0041] Fig.21 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the twenty-first embodiment of the present invention.

[0042] Fig. 22 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the twenty-second embodiment of the present invention.

[0043] Fig.23 It is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided in the twenty-third embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other. The acquisition, storage, use, and processing of data in the technical scheme in this application all comply with the relevant provisions of laws and regulations.

[0045] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0046] In the prior art, the OE structure and the host ASIC need to use a packaging substrate or a passive adapter board component for interconnection. There is also a certain communication distance between the OE structure and the host ASIC, which affects signal transmission. At the same time, there are problems such as the difficulty in smooth compatibility between the chip interfaces and the difficulty in integrating functions such as power management and electrostatic protection.

[0047] Therefore, an embodiment of the present invention provides an optoelectronic co-packaging structure, which integrates EIC, PIC or monolithic optical engine into a molded rewiring layer, a glass adapter plate or a packaging substrate to prepare an active silicon bridge, realizes the integration of OE and host chip, shortens the signal transmission path, reduces the energy required for signal driving, reduces data delay, and achieves better electrical performance. Functional modules such as power management, signal conversion and equalization, and electrostatic protection can be integrated on the active silicon bridge, which can enhance the system signal integrity and power integrity, while reducing power consumption, cost and achieving high-density integration. At the same time, it reduces the preparation and integration costs of large-size adapter plates, improves yield, and achieves high-functional density integration.

[0048] Figure 1 is a structural schematic diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a first embodiment of the present invention, Figure 2 is a schematic structural diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a second embodiment of the present invention, Figure 3 is a schematic structural diagram of an optoelectronic co-packaging structure based on an embedded active silicon bridge provided by a third embodiment of the present invention, such as Figure 1 , Figure 2 and Figure 3 As shown, the optoelectronic co-packaging structure provided by the embodiment of the present invention includes an embedded active silicon bridge 1 and a host chip 2, wherein:

[0049] The host chip 2 is arranged on the embedded active silicon bridge 1 , in which the photonic integrated chip 3 , the electronic integrated chip 4 or the monolithic optoelectronic integrated chip 5 is integrated.

[0050] Specifically, the host chip 2 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology, or can be bonded on the embedded active silicon bridge 1 by bump bonding. The embedded active silicon bridge 1 can be prepared based on a molded rewiring layer, a glass transfer board or a packaging substrate, and the active chip is embedded in the molded rewiring layer, the glass transfer board or the packaging substrate to prepare the embedded active silicon bridge 1. The embedded active silicon bridge 1 can be divided into a PIC silicon bridge, an EIC silicon bridge and a monolithic optoelectronic integrated silicon bridge. The PIC silicon bridge can be obtained by embedding the photonic integrated chip 3 into the molded rewiring layer, the glass transfer board or the packaging substrate; the EIC silicon bridge can be obtained by embedding the electronic integrated chip 4 into the molded rewiring layer, the glass transfer board or the packaging substrate; the monolithic optoelectronic integrated chip 5 can be embedded in the molded rewiring layer, the glass transfer board or the packaging substrate to obtain a monolithic optoelectronic integrated silicon bridge. A through-hole structure and a redistribution layer (RDL) or an optical waveguide interconnection structure can be prepared in the embedded active silicon bridge 1. The through-hole includes but is not limited to through-silicon via (TSV), glass through-hole and molded through-hole. The host chip 2 includes but is not limited to a switch, a CPU, a GPU, an FPGA, a memory, etc. Among them, the bump bonding can be performed by solder bump bonding, micro bump bonding, etc., which can be selected according to actual needs and is not limited in the embodiment of the present invention.

[0051] When the embedded active silicon bridge 1 is a PIC silicon bridge, the host chip 2 is electrically connected to the photonic integrated chip 3 in the PIC silicon bridge, the electronic integrated chip 4 is arranged on the PIC silicon bridge and electrically connected to the photonic integrated chip 3, and the electronic integrated chip 4 can also be electrically connected to the host chip 2 through the PIC silicon bridge.

[0052] When the embedded active silicon bridge 1 is an EIC silicon bridge, the host chip 2 is electrically connected to the electronic integrated chip 4 in the EIC silicon bridge, the photon integrated chip 3 is arranged on the EIC silicon bridge and electrically connected to the electronic integrated chip 4, and the photon integrated chip 3 can also be electrically connected to the host chip 2 through the PIC silicon bridge.

[0053] When the embedded active silicon bridge 1 is a monolithic optoelectronic integrated silicon bridge, the host chip 2 is electrically connected to the monolithic optoelectronic integrated chip 5 in the monolithic optoelectronic integrated silicon bridge. As a type of OE, the monolithic optoelectronic integrated chip integrates components that realize the functions of the electronic integrated chip 4 and the photonic integrated chip 3 on a single chip.

[0054] The photonic integrated chip 3, the electronic integrated chip 4 or the monolithic optoelectronic integrated chip 5 is integrated into the embedded active silicon bridge 1, and the host chip 2 is arranged on the embedded active silicon bridge 1 to realize the integration of the OE and the host chip 2, shorten the electrical signal transmission path between the host chip 2 and the OE, and improve the communication efficiency.

[0055] The optoelectronic co-packaging structure based on the embedded active silicon bridge provided by the embodiment of the present invention includes an embedded active silicon bridge and a host chip, wherein the host chip is arranged on the embedded active silicon bridge, and the embedded active silicon bridge integrates a photonic integrated chip, an electronic integrated chip or a monolithic light engine, thereby shortening the communication distance between the host chip and the light engine, and improving the communication efficiency between the host chip and the OE; and shortening the signal path to achieve flexible and efficient signal transmission.

[0056] like Figure 1 ,like Figure 2 and Figure 3 As shown, on the basis of the above embodiments, the embedded active silicon bridge 1 further includes a horizontal interconnection layer 1-1, and the horizontal interconnection layer 1-1 is arranged on the surface of the embedded active silicon bridge 1. The host chip 2 can be electrically connected to the photonic integrated chip 3, the electronic integrated chip 4 or the monolithic optoelectronic integrated chip integrated in the embedded active silicon bridge 1 through the horizontal interconnection layer 1-1.

[0057] like Figure 1 and Figure 4 As shown, on the basis of the above embodiments, further, the photonic integrated chip 3 is integrated in the embedded active silicon bridge 1, the electronic integrated chip 4 is arranged on the embedded active silicon bridge 1, and the host chip 2 is electrically connected to the photonic integrated chip 3 and the electronic integrated chip 4 respectively.

[0058] Specifically, the photon integrated chip 3 is embedded in the embedded active silicon bridge 1. The electronic integrated chip 4 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology, or bonded on the embedded active silicon bridge 1 by bumps. The host chip 2 can be electrically connected to the photon integrated chip 3 in the embedded active silicon bridge 1, and the host chip 2 can be electrically connected to the electronic integrated chip 4 through the embedded active silicon bridge 1. The photon integrated chip 3 is electrically connected to the electronic integrated chip 4.

[0059] For example, Figure 1 As shown, the host chip 2 is bonded to the embedded active silicon bridge 1 through the first bump 2-0, and the electronic integrated chip 4 is bonded to the embedded active silicon bridge 1 through the second bump 4-1. The host chip 2 is electrically connected to the photon integrated chip 3 through the first bump 2-0, and the photon integrated chip 3 is electrically connected to the electronic integrated chip 4 through the second bump 4-1. The host chip 2 is electrically connected to the electronic integrated chip 4 through the first bump 2-0, the horizontal interconnection layer 1-1 included in the embedded active silicon bridge 1, and the second bump 4-1.

[0060] For example, Figure 4 As shown, the host chip 2 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology, and the electronic integrated chip 4 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology. The host chip 2 is electrically connected to the photonic integrated chip 3, and the photonic integrated chip 3 is electrically connected to the electronic integrated chip 4. The host chip 2 is electrically connected to the electronic integrated chip 4 through the embedded active silicon bridge 1.

[0061] like Figure 2 As shown, on the basis of the above embodiments, further, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the photonic integrated chip 3 is arranged on the embedded active silicon bridge 1, and the host chip 2 is electrically connected to the photonic integrated chip 3 and the electronic integrated chip 4 respectively.

[0062] Specifically, the electronic integrated chip 4 is embedded in the embedded active silicon bridge 1. The photonic integrated chip 3 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology, or bonded on the embedded active silicon bridge 1 by bump bonding. The host chip 2 can be electrically connected to the electronic integrated chip 4 in the embedded active silicon bridge 1, and the host chip 2 can also be electrically connected to the photonic integrated chip 3 through the embedded active silicon bridge 1. The photonic integrated chip 3 is electrically connected to the electronic integrated chip 4.

[0063] For example, Figure 2 As shown, the host chip 2 is bonded to the embedded active silicon bridge 1 through the first bump 2-0, and the photon integrated chip 3 is bonded to the embedded active silicon bridge 1 through the third bump 3-1. The host chip 2 is electrically connected to the electronic integrated chip 4 through the first bump 2-0, and the electronic integrated chip 4 is electrically connected to the photon integrated chip 3 through the third bump 3-1. The host chip 2 is electrically connected to the electronic integrated chip 4 through the first bump 2-0, the embedded active silicon bridge 1 and the third bump 3-1.

[0064] For example, Figure 5 As shown, the host chip 2 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology, and the photonic integrated chip 3 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology. The host chip 2 is electrically connected to the electronic integrated chip 4, and the photonic integrated chip 3 is electrically connected to the electronic integrated chip 4. The host chip 2 is electrically connected to the photonic integrated chip 3 through the embedded active silicon bridge 1.

[0065] like Figures 6 to 14 As shown, on the basis of the above embodiments, further, the host chip 2 includes a computing unit core particle 2-1 and / or a storage unit core particle 2-2, and the computing unit core particle 2-1 and the storage unit core particle 2-2 are respectively bonded to the embedded active silicon bridge 1, or the computing unit core particle 2-1 and the storage unit core particle 2-2 are three-dimensionally stacked and integrated on the embedded active silicon bridge 1.

[0066] Specifically, the host chip 2 may include a computing unit (Comp) core 2-1 and a memory unit (MEM) core 2-2. The host chip 2 may include only the computing unit core 2-1. Alternatively, the host chip 2 may include only the memory unit core 2-2.

[0067] The computing unit core particle 2-1 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology, or by bump bonding on the embedded active silicon bridge 1. The storage unit core particle 2-2 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology, or by bump bonding on the embedded active silicon bridge 1. The computing unit core particle 2-1 and the storage unit core particle 2-2 can be electrically connected through the embedded active silicon bridge 1.

[0068] The computing unit core grain 2-1 can be stacked on the storage unit core grain 2-2 to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated into the embedded active silicon bridge 1; or the storage unit core grain 2-2 is stacked on the computing unit core grain 2-1 to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated into the embedded active silicon bridge 1. Multiple computing unit core grains 2-1 can be stacked to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated into the embedded active silicon bridge 1; multiple storage unit core grains 2-2 can be stacked to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated into the embedded active silicon bridge 1. Among them, the computing unit core grain 2-1 can be stacked on the storage unit core grain 2-2 by hybrid bonding or bump bonding, and similarly, the storage unit core grain 2-2 can be stacked on the computing unit core grain 2-1 by hybrid bonding or bump bonding.

[0069] For example, Figure 6 As shown, the photon integrated chip 3 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the embedded active silicon bridge 1 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the embedded active silicon bridge 1 through the fifth bump 2-2-1, and the electronic integrated chip 4 is bonded to the embedded active silicon bridge 1 through the second bump 4-1. The computing unit core particle 2-1 is electrically connected to the photon integrated chip 3 through the fourth bump 2-1-1, and the storage unit core particle 2-2 is electrically connected to the photon integrated chip 3 through the fifth bump 2-2-1. The photon integrated chip 3 is electrically connected to the electronic integrated chip 4 through the second bump 4-1 6. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1, the embedded active silicon bridge 1 and the fifth bump 2-2-1.

[0070] For example, Figure 7As shown, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the embedded active silicon bridge 1 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the embedded active silicon bridge 1 through the fifth bump 2-2-1, and the electronic integrated chip 4 is bonded to the embedded active silicon bridge 1 through the second bump 4-1. The computing unit core particle 2-1 is electrically connected to the electronic integrated chip 4 through the fourth bump 2-1-1, and the storage unit core particle 2-2 is electrically connected to the electronic integrated chip 4 through the fifth bump 2-2-1. The photon integrated chip 3 is electrically connected to the electronic integrated chip 4 through the third bump 3-1. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1, the embedded active silicon bridge 1 and the fifth bump 2-2-1.

[0071] For example, Figure 8 As shown, the embedded active silicon bridge 1 integrates a monolithic optoelectronic integrated chip 5, the computing unit core particle 2-1 is bonded to the embedded active silicon bridge 1 through the fourth bump 2-1-1, and the storage unit core particle 2-2 is bonded to the embedded active silicon bridge 1 through the fifth bump 2-2-1. The computing unit core particle 2-1 is connected to the monolithic optoelectronic integrated chip 5 through the fourth bump 2-1-1, and the storage unit core particle 2-2 is connected to the monolithic optoelectronic integrated chip 5 through the fifth bump 2-2-1. The computing unit core particle 2-1 and the storage unit core particle 2-2 are electrically connected to the monolithic optoelectronic integrated chip 5 through the fourth bump 2-1-1, the embedded active silicon bridge 1 and the fifth bump 2-2-1.

[0072] For example, Fig. 9 As shown, the photonic integrated chip 3 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology, the storage unit core particle 2-2 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology, and the electronic integrated chip 4 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology. The computing unit core particle 2-1 is electrically connected to the photonic integrated chip 3, and the storage unit core particle 2-2 is electrically connected to the photonic integrated chip 3. The photonic integrated chip 3 is electrically connected to the electronic integrated chip 4. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the embedded active silicon bridge 1.

[0073] For example, Fig.10As shown, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology, the storage unit core particle 2-2 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology, and the electronic integrated chip 4 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology. The computing unit core particle 2-1 is electrically connected to the electronic integrated chip 4, and the storage unit core particle 2-2 is electrically connected to the electronic integrated chip 4. The photonic integrated chip 3 is electrically connected to the electronic integrated chip 4. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the embedded active silicon bridge 1.

[0074] For example, Fig.11 As shown, a monolithic optoelectronic integrated chip 5 is integrated in the embedded active silicon bridge 1, a computing unit chip 2-1 is integrated on the embedded active silicon bridge 1 by hybrid bonding technology, and a storage unit chip 2-2 is integrated on the embedded active silicon bridge 1 by hybrid bonding technology. The computing unit chip 2-1 is communicatively connected with the monolithic optoelectronic integrated chip 5, and the storage unit chip 2-2 is communicatively connected with the monolithic optoelectronic integrated chip 5. The computing unit chip 2-1 and the storage unit chip 2-2 are electrically connected through the embedded active silicon bridge 1.

[0075] For example, Fig.12 As shown, the photon integrated chip 3 is integrated in the embedded active silicon bridge 1, the storage unit core particle 2-2 is bonded to the computing unit core particle 2-1 through the fifth bump 2-2-1, the computing unit core particle 2-1 is bonded to the embedded active silicon bridge 1 through the fourth bump 2-1-1, and the electronic integrated chip 4 is bonded to the embedded active silicon bridge 1 through the second bump 4-1. The storage unit core particle 2-2 is electrically connected to the computing unit core particle 2-1 through the fifth bump 2-2-1, and the computing unit core particle 2-1 is electrically connected to the photon integrated chip 3 through the fourth bump 2-1-1. The photon integrated chip 3 is electrically connected to the electronic integrated chip 4 through the second bump 4-1.

[0076] For example, Fig.13 As shown, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the storage unit core particle 2-2 is bonded to the computing unit core particle 2-1 through the fifth bump 2-2-1, the computing unit core particle 2-1 is bonded to the embedded active silicon bridge 1 through the fourth bump 2-1-1, and the photon integrated chip 3 is bonded to the embedded active silicon bridge 1 through the third bump 3-1. The storage unit core particle 2-2 is electrically connected to the computing unit core particle 2-1 through the fifth bump 2-2-1, and the computing unit core particle 2-1 is electrically connected to the electronic integrated chip 4 through the fourth bump 2-1-1 and the embedded active silicon bridge 1. The photon integrated chip 3 is electrically connected to the electronic integrated chip 4 through the third bump 3-1.

[0077] For example, Fig.14As shown, the embedded active silicon bridge 1 integrates a monolithic optoelectronic integrated chip 5, the storage unit core particle 2-2 is bonded to the computing unit core particle 2-1 through the fifth bump 2-2-1, and the computing unit core particle 2-1 is bonded to the embedded active silicon bridge 1 through the fourth bump 2-1-1. The storage unit core particle 2-2 is electrically connected to the computing unit core particle 2-1 through the fifth bump 2-2-1, and the computing unit core particle 2-1 is communicatively connected to the monolithic optoelectronic integrated chip 5 through the fourth bump 2-1-1.

[0078] like Figures 15 to 23 As shown, on the basis of the above embodiments, further, the optoelectronic co-packaging structure based on the embedded active silicon bridge provided in the embodiment of the present invention also includes a passive adapter board 6, which is arranged on the embedded active silicon bridge 1; the passive adapter board 6 includes a first redistribution layer 6-1, and the first redistribution layer 6-1 is arranged on the surface of the passive adapter board 6; the host chip 2 includes a computing unit core particle 2-1 and / or a storage unit core particle 2-2, and the computing unit core particle 2-1 and / or the storage unit core particle 2-2 are respectively bonded to the passive adapter board 6, or integrated on the passive adapter board 6 after three-dimensional stacking.

[0079] Specifically, the passive adapter board 6 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology, or by bump bonding on the embedded active silicon bridge 1, and the passive adapter board 6 can be a silicon adapter board. The passive adapter board 6 includes a first rewiring layer 6-1, and the first rewiring layer 6-1 is used to realize the electrical connection between the computing unit core particle 2-1 and / or the storage unit core particle 2-2 and the photonic integrated chip 3, the electronic integrated chip 4 or the monolithic optoelectronic integrated chip integrated in the embedded active silicon bridge 1.

[0080] The host chip 2 may include a computing unit core particle 2-1 and a storage unit core particle 2-2. The host chip 2 may include only the computing unit core particle 2-1. Alternatively, the host chip 2 may include only the storage unit core particle 2-2.

[0081] The computing unit core particle 2-1 can be integrated on the first rewiring layer 6-1 of the passive adapter board 6 by hybrid bonding technology, or by bump bonding on the passive adapter board 6. The storage unit core particle 2-2 can be integrated on the passive adapter board 6 by hybrid bonding technology, or by bump bonding on the passive adapter board 6. The computing unit core particle 2-1 and the storage unit core particle 2-2 can be electrically connected through the first rewiring layer 6-1 included in the passive adapter board 6.

[0082] The computing unit core particles 2-1 can be stacked on the storage unit core particles 2-2 to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated onto the passive adapter board 6; the storage unit core particles 2-2 are stacked on the computing unit core particles 2-1 to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated onto the passive adapter board 6. Multiple computing unit core particles 2-1 can be stacked to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated onto the passive adapter board 6; multiple storage unit core particles 2-2 can be stacked to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated onto the passive adapter board 6. Among them, the computing unit core particles 2-1 can be stacked on the storage unit core particles 2-2 by hybrid bonding or bump bonding, and similarly, the storage unit core particles 2-2 can be stacked on the computing unit core particles 2-1 by hybrid bonding or bump bonding.

[0083] For example, Fig.15 As shown, the photonic integrated chip 3 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the first rewiring layer 6-1 of the passive adapter board 6 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the first rewiring layer 6-1 of the passive adapter board 6 through the fifth bump 2-2-1, the passive adapter board 6 includes the first rewiring layer 6-1, the passive adapter board 6 is bonded to the embedded active silicon bridge 1 through the sixth bump 6-2, and the electronic integrated chip 4 is bonded to the embedded active silicon bridge 1 through the second bump 4-1. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1, the first rewiring layer 6-1 included in the embedded active silicon bridge 1, and the fifth bump 2-2-1.

[0084] For example, Fig.16 As shown, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the first rewiring layer 6-1 of the passive adapter board 6 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the first rewiring layer 6-1 of the passive adapter board 6 through the fifth bump 2-2-1, and the photon integrated chip 3 is bonded to the embedded active silicon bridge 1 through the third bump 3-1. The passive adapter board 6 includes a first rewiring layer 6-1, and the passive adapter board 6 is bonded to the embedded active silicon bridge 1 through the sixth bump 6-2. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1, the first rewiring layer 6-1 and the fifth bump 2-2-1.

[0085] For example, Fig.17As shown, a monolithic optoelectronic integrated chip 5 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the passive adapter board 6 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the passive adapter board 6 through the fifth bump 2-2-1, the passive adapter board 6 includes a first rewiring layer 6-1, and the passive adapter board 6 is bonded to the embedded active silicon bridge 1 through the sixth bump 6-2. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1, the first rewiring layer 6-1 and the fifth bump 2-2-1.

[0086] For example, Fig.18 As shown, the photonic integrated chip 3 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is integrated on the passive adapter board 6 by hybrid bonding technology, the storage unit core particle 2-2 is integrated on the passive adapter board 6 by hybrid bonding technology, the passive adapter board 6 includes a first redistribution layer 6-1, and the passive adapter board 6 is integrated on the embedded active silicon bridge 1 by hybrid bonding technology. The electronic integrated chip 4 is integrated on the embedded active silicon bridge 1 by hybrid bonding technology. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the embedded active silicon bridge 1.

[0087] For example, Fig.19 As shown, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is integrated on the passive adapter board 6 through hybrid bonding technology, the storage unit core particle 2-2 is integrated on the passive adapter board 6 through hybrid bonding technology, and the photonic integrated chip 3 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology. The passive adapter board 6 includes a first rewiring layer 6-1, and the passive adapter board 6 is integrated on the embedded active silicon bridge 1 through hybrid bonding technology. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the first rewiring layer 6-1.

[0088] For example, Fig. 20 As shown, a monolithic optoelectronic integrated chip 5 is integrated in the embedded active silicon bridge 1, a computing unit core particle 2-1 is integrated on a passive adapter board 6 by hybrid bonding technology, and a storage unit core particle 2-2 is integrated on a passive adapter board 6 by hybrid bonding technology. The passive adapter board 6 includes a first rewiring layer 6-1, and the passive adapter board 6 is integrated on the embedded active silicon bridge 1 by hybrid bonding technology. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the first rewiring layer 6-1.

[0089] For example, Fig.21As shown, the embedded active silicon bridge 1 integrates a photonic integrated chip 3, the computing unit core particle 2-1 is bonded to the storage unit core particle 2-2 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the passive adapter board 6 through the fifth bump 2-2-1, the passive adapter board 6 includes a first redistribution layer 6-1, the passive adapter board 6 is bonded to the embedded active silicon bridge 1 through the sixth bump 6-2, and the electronic integrated chip 4 is bonded to the embedded active silicon bridge 1 through the second bump 4-1. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1.

[0090] For example, Fig. 22 As shown, the electronic integrated chip 4 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the storage unit core particle 2-2 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the passive adapter board 6 through the fifth bump 2-2-1, the passive adapter board 6 includes a first redistribution layer 6-1, the passive adapter board 6 is bonded to the embedded active silicon bridge 1 through the sixth bump 6-2, and the photon integrated chip 3 is bonded to the embedded active silicon bridge 1 through the third bump 3-1. The computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1.

[0091] For example, Fig.23 As shown, a monolithic optoelectronic integrated chip 5 is integrated in the embedded active silicon bridge 1, the computing unit core particle 2-1 is bonded to the storage unit core particle 2-2 through the fourth bump 2-1-1, the storage unit core particle 2-2 is bonded to the passive adapter board 6 through the fifth bump 2-2-1, the passive adapter board 6 includes a first redistribution layer 6-1, the passive adapter board 6 is bonded to the embedded active silicon bridge 1 through the sixth bump 6-2, and the computing unit core particle 2-1 is electrically connected to the storage unit core particle 2-2 through the fourth bump 2-1-1.

[0092] like Figures 15 to 23 As shown, on the basis of the above embodiments, further, a through silicon via 6-3 is provided in the passive adapter board 6 to realize the electrical connection between the computing unit core particle 2-1 and / or the storage unit core particle 2-2 and the photonic integrated chip 3, the electronic integrated chip 4 or the monolithic optoelectronic integrated chip 5 integrated in the embedded active silicon bridge 1.

[0093] like Fig.15 As shown, the passive adapter board 6 includes a through silicon via 6-3. The computing unit core particle 2-1 is electrically connected to the photon integrated chip 3 through the fourth bump 2-1-1, the first rewiring layer 6-1, the through silicon via 6-3, and the sixth bump 6-2. The storage unit core particle 2-2 is electrically connected to the photon integrated chip 3 through the fifth bump 2-2-1, the first rewiring layer 6-1, the through silicon via 6-3, and the sixth bump 6-2.

[0094] For example, Fig.16 As shown, the passive transfer board 6 includes a through silicon via 6-3. The computing unit core particle 2-1 is electrically connected to the electronic integrated chip 4 through the fourth bump 2-1-1, the first rewiring layer 6-1, the through silicon via 6-3, and the sixth bump 6-2. The storage unit core particle 2-2 is electrically connected to the electronic integrated chip 4 through the fifth bump 2-2-1, the first rewiring layer 6-1, the through silicon via 6-3, and the sixth bump 6-2.

[0095] For example, Fig.17 As shown, the passive transfer board 6 includes a through silicon via 6-3. The computing unit core particle 2-1 is electrically connected to the monolithic optoelectronic integrated chip 5 through the fourth bump 2-1-1, the first rewiring layer 6-1, the through silicon via 6-3, and the sixth bump 6-2. The storage unit core particle 2-2 is electrically connected to the monolithic optoelectronic integrated chip 5 through the fifth bump 2-2-1, the first rewiring layer 6-1, the through silicon via 6-3, and the sixth bump 6-2.

[0096] For example, Fig.18 As shown, the passive adapter board 6 includes a through silicon via 6-3. The computing unit core particle 2-1 is electrically connected to the photon integrated chip 3 through the first rewiring layer 6-1 and the through silicon via 6-3. The storage unit core particle 2-2 is electrically connected to the photon integrated chip 3 through the first rewiring layer 6-1 and the through silicon via 6-3.

[0097] For example, Fig.19 As shown, the passive transfer board 6 includes a through silicon via 6-3. The computing unit core particle 2-1 is electrically connected to the electronic integrated chip 4 through the first rewiring layer 6-1 and the through silicon via 6-3. The storage unit core particle 2-2 is electrically connected to the electronic integrated chip 4 through the first rewiring layer 6-1 and the through silicon via 6-3.

[0098] For example, Fig. 20 As shown, the passive adapter board 6 includes a through silicon via 6-3. The computing unit core particle 2-1 is electrically connected to the monolithic optoelectronic integrated chip 5 through the first rewiring layer 6-1 and the through silicon via 6-3. The storage unit core particle 2-2 is electrically connected to the monolithic optoelectronic integrated chip 5 through the first rewiring layer 6-1 and the through silicon via 6-3.

[0099] For example, Fig.21 As shown, the passive transfer board 6 includes a through silicon via 6-3, and the memory cell core particle 2-2 is electrically connected to the photonic integrated chip 3 through the fifth bump 2-2-1, the through silicon via 6-3 and the sixth bump 6-2.

[0100] For example, Fig. 22 As shown, the passive transfer board 6 includes a through silicon via 6-3, and the memory cell core particle 2-2 is electrically connected to the electronic integrated chip 4 through the fifth bump 2-2-1, the through silicon via 6-3, and the sixth bump 6-2.

[0101] For example, Fig.23As shown, the passive transfer board 6 includes a through silicon via 6-3, and the memory cell core particle 2-2 is electrically connected to the monolithic optoelectronic integrated chip 5 through the fifth bump 2-2-1, the through silicon via 6-3, and the sixth bump 6-2.

[0102] On the basis of the above embodiments, further, the passive adapter board 6 is bonded to the embedded active silicon bridge 1. The passive adapter board 6 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology. Alternatively, the passive adapter board 6 can be bonded to the embedded active silicon bridge 1 by bump bonding.

[0103] like Figure 1 , Figure 2 and Figure 3 As shown, based on the above embodiments, the embedded active silicon bridge 1 further integrates passive components (Integrated Passive Device, referred to as IPD) 1-2. The IPD may include components such as resistors, capacitors, and inductors. The size and weight of the circuit can be reduced, which helps to achieve the thinness of electronic devices. The IPD is essential for high-speed data operations in advanced logic circuits that require a stable voltage power supply, and the IPD can improve power integrity.

[0104] like Figure 1 , Figure 2 and Figure 3 As shown, based on the above embodiments, the embedded active silicon bridge 1 further integrates a through hole structure 1-3 for vertical interconnection, and the through hole structure 1-3 can be used to realize power supply and signal transmission. The through hole structure 1-3 can adopt silicon through hole, glass through hole and molded through hole and other structures, which can be selected according to actual needs, and the embodiment of the present invention does not limit it.

[0105] On the basis of the above embodiments, further, the horizontal interconnection layer 1 - 1 includes a second redistribution layer and an optical waveguide.

[0106] For example, when the embedded active silicon bridge 1 is a PIC silicon bridge, the horizontal interconnection layer 1 - 1 includes a second redistribution layer and an optical waveguide.

[0107] For example, when the embedded active silicon bridge 1 is a monolithic optoelectronic integrated silicon bridge, the horizontal interconnection layer 1 - 1 includes a second redistribution layer and an optical waveguide.

[0108] On the basis of the above embodiments, further, the horizontal interconnection layer 1 - 1 includes a second redistribution layer.

[0109] For example, when the embedded active silicon bridge 1 is an EIC silicon bridge, the horizontal interconnection layer 1 - 1 includes a second redistribution layer.

[0110] On the basis of the above embodiments, further, the horizontal interconnection layer 1 - 1 includes an optical waveguide.

[0111] For example, when the embedded active silicon bridge 1 is a PIC silicon bridge, the horizontal interconnection layer 1 - 1 includes an optical waveguide.

[0112] On the basis of the above embodiments, further, the host chip 2 can be bonded on the embedded active silicon bridge 1 through bumps.

[0113] On the basis of the above embodiments, further, the host chip 2 can be integrated on the embedded active silicon bridge 1 by hybrid bonding technology.

[0114] The host chip 2 is integrated on the embedded active silicon bridge 1 using hybrid bonding technology to realize the integration of OE and the host chip 2, which can achieve higher computing efficiency, wider data bandwidth and higher functional packaging density.

[0115] On the basis of the above embodiments, further, at least one of a power management module, a signal management module and an electrostatic protection module is integrated on the embedded active silicon bridge 1. For example, a power management module, a signal management module or an electrostatic protection module is set on the embedded active silicon bridge 1. For example, any two of the power management module, the signal management module and the electrostatic protection module are set on the embedded active silicon bridge 1. For example, a power management module, a signal management module and an electrostatic protection module are set on the embedded active silicon bridge 1.

[0116] The signal integrity and power integrity of the system can be enhanced by arranging a power management module, a signal management module and an electrostatic protection module on the embedded active silicon bridge 1 .

[0117] This patent proposes an optoelectronic co-packaging structure based on an active silicon bridge, which embeds EIC, PIC or monolithic optical engine into a molded rewiring layer, a glass adapter plate or a packaging substrate to prepare an active silicon bridge for integration of OE and host chip. This structure shortens the signal path, realizes flexible and efficient signal transmission, and can also integrate functional modules such as power management, signal conversion and equalization, and input and output expansion to enhance system signal integrity and power integrity; at the same time, it reduces the preparation and integration cost of large-size adapter plates, improves yield, and realizes high functional density integration.

[0118] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0119] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An optoelectronic co-packaging structure based on an embedded active silicon bridge, characterized in that: Includes embedded active silicon bridge and host chip, where: The host chip is arranged on the embedded active silicon bridge, and a photonic integrated chip, an electronic integrated chip or a monolithic optoelectronic integrated chip is integrated in the embedded active silicon bridge.

2. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The embedded active silicon bridge comprises a horizontal interconnection layer, and the horizontal interconnection layer is arranged on a surface of the embedded active silicon bridge.

3. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 2, characterized in that: The horizontal interconnect layer includes a second redistribution layer and / or an optical waveguide.

4. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The photon integrated chip is integrated in the embedded active silicon bridge, the electronic integrated chip is arranged on the embedded active silicon bridge, and the host chip is electrically connected to the photon integrated chip and the electronic integrated chip respectively.

5. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The electronic integrated chip is integrated in the embedded active silicon bridge, the photon integrated chip is arranged on the embedded active silicon bridge, and the host chip is electrically connected to the photon integrated chip and the electronic integrated chip respectively.

6. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The host chip includes a computing unit core particle and / or a storage unit core particle, and the computing unit core particles and / or the storage unit core particles are respectively bonded to the embedded active silicon bridge, or are integrated on the embedded active silicon bridge after three-dimensional stacking.

7. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: It also includes a passive adapter board, which is arranged on the embedded active silicon bridge, and the passive adapter board includes a first redistribution layer, and the first redistribution layer is arranged on the surface of the passive adapter board; the host chip includes computing unit core particles and / or storage unit core particles, and the computing unit core particles and / or storage unit core particles are respectively bonded to the passive adapter board, or integrated on the passive adapter board after three-dimensional stacking.

8. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 7, characterized in that: Through silicon vias are provided in the passive adapter board to realize electrical connection between the computing unit core grain and / or the storage unit core grain and the photonic integrated chip, electronic integrated chip or monolithic optoelectronic integrated chip integrated in the embedded active silicon bridge.

9. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 7, characterized in that: The passive adapter plate is bonded to the embedded active silicon bridge.

10. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The embedded active silicon bridge integrates passive components.

11. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The embedded active silicon bridge integrates a via structure for vertical interconnection.

12. The optoelectronic co-packaging structure based on embedded active silicon bridge according to claim 1, characterized in that: The host chip is bonded to the embedded active silicon bridge via bump bonding, or hybrid bonding is performed on the embedded active silicon bridge.

13. The optoelectronic co-packaging structure based on embedded active silicon bridge according to any one of claims 1 to 12, characterized in that: At least one of a power management module, a signal management module and an electrostatic protection module is integrated on the embedded active silicon bridge.

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