Single-particle-resistant reinforced P-GaN transistor with periodic PN junction laminated gate structure
By stacking periodic N-doped and P-doped GaN layers on the P-GaN layer, using the built-in electric field of the PN junction to bind electrons, the problem of fast electron injection channel speed of GaN HEMT devices after high-energy heavy ions is involved. The device's anti-single-particle burn-out capability and performance are significantly improved.
Patent Information
- Application Number
- CN202411437325.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-10
AI Technical Summary
The existing GaN HEMT devices have a fast electron injection into the two-dimensional electron gas channel after high-energy heavy ions are incident, resulting in a surge in transient current inside the device and are prone to burning.
Design a P-GaN transistor with a periodic PN junction stacked gate structure, and use the built-in electric field formed by PN junction to bind heavy ions incident by stacking periodic N-doped and P-doped GaN layers on the P-GaN layer. The generated electrons slow down the rate of electron injection into the channel.
It effectively reduces the instantaneous electron concentration and collision ionization rate in the channel, significantly improves the single-particle burn voltage of the device, and enhances the reliability and performance of the device.
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Figure CN119300397A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor devices and relates to a single particle reinforced P-GaN transistor with a periodic PN junction stacked gate structure. Background Art
[0002] Gallium nitride (GaN), as a representative of the third generation of semiconductor materials, has a wider bandgap and higher critical breakdown field strength than silicon or gallium arsenide, and its high electron mobility transistor (HEMT) demonstrates excellent high voltage and radiation resistance. In the space radiation environment, high-energy particles and cosmic rays will have a huge impact on the electrical parameters of electronic devices, and may even directly cause the device to fail permanently. For high-voltage devices, the single particle effect is a key factor affecting their space applications. After the high-energy heavy ion incident on the conventional enhanced P-GaN HEMT device in the off state, a large number of electron-hole pairs will be generated on the incident trajectory, and the electrons on the trajectory will be injected into the two-dimensional electron gas channel in a very short time, and then flow out from the drain through the channel. When the drain bias is high enough, the electrons will undergo collision ionization at the high field position inside the device during the migration of the electrons in the channel, thereby generating more electron-hole pairs, causing the transient current inside the device to surge, and eventually causing the device to burn out thermally.
[0003] Therefore, it is urgent to design a single-particle resistant enhanced GaN HEMT device to slow down the speed of electron injection into the two-dimensional electron gas channel after heavy ion incidence, reduce the instantaneous electron concentration in the channel, thereby reducing the impact ionization rate and preventing the device from burning out. Summary of the invention
[0004] In view of this, the purpose of the present invention is to provide a single-particle reinforced P-GaN transistor with a periodic PN junction stacked gate structure, by stacking periodic N-doped and P-doped GaN layers on the P-GaN layer, and utilizing the built-in electric field formed by the PN junction to effectively bind a large number of electrons generated by heavy ions incident from the gate, thereby solving the problem of weak single-particle burnout resistance of existing devices.
[0005] In order to achieve the above object, the present invention provides the following technical solutions:
[0006] A single-particle reinforced P-GaN transistor with a periodic PN junction stacked gate structure, the transistor comprising:
[0007] substrate;
[0008] a buffer layer formed on the surface of the substrate;
[0009] A barrier layer formed on a surface of the buffer layer;
[0010] A source electrode formed on a surface of the barrier layer;
[0011] a drain electrode formed on a surface of the barrier layer;
[0012] A P-GaN layer formed on the surface of the barrier layer and located between the source and the drain;
[0013] A periodic PN junction stacked gate structure formed on the surface of the P-GaN layer;
[0014] A gate formed on the surface of the periodic PN junction stacked gate structure; and
[0015] A passivation layer is formed on the surface of the barrier layer, the source electrode and the drain electrode.
[0016] Furthermore, the periodic PN junction stacked gate structure comprises a P-doped GaN layer and an N-doped GaN layer stacked in sequence. Wherein, each stacking of a P-doped GaN layer and an N-doped GaN layer forms a PN junction, and therefore, by stacking a plurality of P-doped GaN layers and N-doped GaN layers between the P-GaN layer and the gate, a plurality of PN junctions can be formed between the P-GaN layer and the gate.
[0017] Furthermore, in the periodic PN junction stacked gate structure, the number of P-doped GaN layers and the number of N-doped GaN layers are the same.
[0018] The P-type doping concentration of the P-doped GaN layer is 1×10 16 cm -3 ~4×10 18 cm -3 The thickness ranges from 25nm to 35nm, and the length ranges from 1.5μm to 2μm. The N-type doping concentration of the N-doped GaN layer is 1×10 16 cm -3 ~4×10 18 cm -3 , the thickness ranges from 25nm to 35nm, and the length ranges from 1.5μm to 2μm.
[0019] Furthermore, the periodic number of the periodic PN junction stacked gate structure (ie, the number of PN junctions) is 1 to 3.
[0020] Furthermore, the thickness of the P-GaN layer ranges from 30 nm to 50 nm, the length ranges from 1.5 μm to 2 μm, and the doping concentration is 3×10 17 cm -3 ~2×10 19 cm -3 .
[0021] The beneficial effects of the present invention are as follows: the present invention realizes effective confinement of a large number of electrons generated by the incidence of heavy ions from the gate by periodically stacking N-doped and P-doped GaN layers on the P-GaN layer and utilizing the built-in electric field formed by the PN junction, and the larger the number of periods of the periodic PN junction stacked gate structure, the more PN junctions there are, and the more significant the confinement effect on electrons. The present invention can significantly slow down the speed of electron injection into the channel and reduce the instantaneous electron concentration in the channel; by reducing the collision ionization rate, the present invention effectively reduces the instantaneous current inside the device, thereby significantly improving the single particle burnout voltage of the device and enhancing the reliability and performance of the device.
[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:
[0024] Figure 1 A schematic cross-sectional view of a single particle reinforced P-GaN transistor with a periodic PN junction stacked gate structure proposed in Example 1 of the present invention;
[0025] Figure 2 Schematic diagram of the cross-sectional structure of a conventional enhancement-mode P-GaN transistor;
[0026] Figure 3 The conventional enhancement mode P-GaN transistor in the off state is subjected to heavy ion irradiation (fluence LET = 63.8 MeV cm 2 / mg) after 1×10 -11 Electron concentration distribution near the gate at s;
[0027] Figure 4 The device of the present invention has a period number of 1 in the off state and is subjected to heavy ion incidence of 1×10 -11 Electron concentration distribution near the gate at s;
[0028] Figure 5 The conventional enhancement-mode P-GaN transistor in the off state is subjected to heavy ion incidence after 5×10 -11 Electron concentration distribution near the gate at s;
[0029] Figure 6 The device of the present invention has a period number of 1 in the off state and is subjected to heavy ion incidence after 5×10 -11Electron concentration distribution near the gate at s;
[0030] Figure 7 A comparison diagram of the simulated curves of drain current and time of the present invention and the conventional enhanced P-GaN transistor in the off state after heavy ion incidence;
[0031] Figure 8 It is a schematic cross-sectional view of a single particle reinforcement resistant P-GaN transistor with a periodic PN junction stacked gate structure proposed in Example 2 of the present invention.
[0032] Reference numerals: 101 - substrate layer, 102 - buffer layer, 103 - barrier layer, 104 - passivation layer, 105 - source electrode, 106 - gate electrode, 107 - drain electrode, 108 - P-GaN layer, 109 - periodic PN junction stacked gate structure. DETAILED DESCRIPTION
[0033] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.
[0034] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.
[0035] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
[0036] Example 1
[0037] like Figure 1As shown, this embodiment provides a single particle reinforcement resistant P-GaN transistor with a periodic PN junction stacked gate structure, which includes a substrate layer 101, a buffer layer 102, a barrier layer 103 and a passivation layer 104 from bottom to top, a source 105 and a drain 107 are respectively located at the two ends above the barrier layer 103, a P-GaN layer 108 is provided above the barrier layer 103 on the right side of the source 105, and a gate 106 is located above the P-GaN layer 108; a periodic PN junction stacked gate structure 109 is formed between the P-GaN layer 108 and the gate 106. The periodic PN junction stacked gate structure 109 includes periodically stacked N-doped and P-doped GaN layers, each stacking of an N-doped GaN layer and a P-doped GaN layer (recorded as one period), that is, forming a PN junction, and by stacking multiple N-doped and P-doped GaN layers, multiple PN junctions are formed between the gate 106 and the P-GaN layer 108.
[0038] The doping concentration of the P-GaN layer 108 is 4×10 18 cm -3 , the thickness is 50nm and the length is 2μm.
[0039] In this embodiment, the period number of the periodic PN junction stacked gate structure 109 is 1, wherein the thickness of the N-doped GaN is 25 nm, the length is 2 μm, and the doping concentration is 1×10 18 cm -3 The thickness of P-doped GaN is 25 nm, the length is 2 μm, and the doping concentration is 4×10 18 cm -3 .
[0040] The working principle of the device proposed in this embodiment is that by cleverly stacking periodic N-doped and P-doped GaN layers on the P-GaN layer 108, the built-in electric field formed by the PN junction is used to effectively bind a large number of electrons generated by heavy ions incident from the gate. This design can significantly slow down the speed of electron injection into the channel and reduce the instantaneous electron concentration in the channel. By reducing the collision ionization rate, the instantaneous current inside the device can be effectively reduced, thereby significantly improving the single particle burnout voltage of the device and enhancing the reliability and performance of the device.
[0041] like Figure 3 The conventional enhancement mode P-GaN transistor in the off state is shown (its structure is as follows Figure 2 As shown) when heavy ions are incident through 1×10 -11 The electron concentration distribution near the gate at s, where heavy ions are incident on the gate near the drain end. It can be found that when the heavy ions are incident for 1×10 -11s, the electron concentration inside the P-GaN layer 108 is low. This is because the P-GaN layer 108 has no binding effect on the electrons generated by the heavy ion incidence, and the electrons quickly transfer from the P-GaN layer 108 to the channel.
[0042] like Figure 4 The device of this embodiment is shown in the off state when heavy ions are incident through 1×10 -11 The electron concentration distribution near the gate at s, where heavy ions are incident on the gate near the drain end. It can be found that when the heavy ions are incident for 1×10 -11 s, a large number of electrons gather in the N-doped GaN layer of the device. This is because the built-in electric field formed by the stacked structure has a binding effect on the electrons generated by the heavy ion incidence, slowing down the speed of electron injection into the channel.
[0043] Figure 5 and Figure 6 They are the conventional enhancement-mode P-GaN transistor in the off state and the device of this embodiment after 5×10 -11 The electron concentration distribution near the gate at s. It can be found that after 5×10 -11 After s, the electrons in the P-GaN layer 108 of the conventional enhancement-mode P-GaN transistor are substantially all injected into the conductive channel, while the electron concentrations in the P-GaN layer 108 and the N-doped GaN layer in this embodiment are significantly higher than those in the former.
[0044] like Figure 7 The figure shows the simulated curve comparison of the drain current and time of the device of this embodiment (with a circular curve) and the conventional enhancement mode P-GaN transistor in the off state after heavy ion injection. It can be found that when the linear energy transfer value LET of the incident heavy ions is 63.8 MeV·cm 2 / mg, when the drain voltage of the conventional enhancement-mode P-GaN transistor is 275V, its drain current suddenly increases after a period of time and cannot be recovered, that is, single-particle burnout occurs; while when the drain voltage of the device in this embodiment is 275V, its drain current can still recover to a normal value after a period of time, and no single-particle burnout occurs, indicating that the device's ability to resist single-particle burnout is improved.
[0045] Example 2
[0046] In this embodiment, the period number of the periodic PN junction stacked gate structure 109 is set to 2. Figure 8 As shown. The thickness of the single N-doped GaN layer is 12.5 nm, the length is 2 μm, and the doping concentration is 1×10 18 cm -3 The thickness of the single P-doped GaN layer is 12.5 nm, the length is 2 μm, and the doping concentration is 4×10 18cm -3 .
[0047] After heavy ion injection, the electron concentration distribution near the gate in different time periods of the device of this embodiment is similar to that of embodiment 1, except that the electron concentration bound in the P-GaN layer 107 and the N-doped GaN layer is higher than that in embodiment 1.
[0048] like Figure 7 As shown, the simulation curves of drain current and time of this embodiment (cycle number is 2, with a triangular curve), embodiment 1 (cycle number is 1, with a circular curve) and a conventional enhancement mode P-GaN transistor after heavy ion irradiation are compared. It can be seen that the transient current curve of the device in this embodiment is lower than that in embodiment 1, indicating that the more cycles there are, the more significant the effect of improving the single particle burnout voltage of the device.
[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.
Claims
1. A single particle reinforced P-GaN transistor with a periodic PN junction stacked gate structure, characterized in that: The transistor includes: substrate; a buffer layer formed on the surface of the substrate; A barrier layer formed on a surface of the buffer layer; A source electrode formed on a surface of the barrier layer; a drain electrode formed on a surface of the barrier layer; A P-GaN layer formed on the surface of the barrier layer and located between the source and the drain; A periodic PN junction stacked gate structure formed on the surface of the P-GaN layer; A gate formed on the surface of the periodic PN junction stacked gate structure; and A passivation layer is formed on the surface of the barrier layer, the source electrode and the drain electrode.
2. The single particle reinforced P-GaN transistor according to claim 1, characterized in that: The periodic PN junction stacked gate structure comprises a P-doped GaN layer and an N-doped GaN layer stacked in sequence.
3. The single particle reinforced P-GaN transistor according to claim 2, characterized in that: In the periodic PN junction stacked gate structure, the number of P-doped GaN layers and the number of N-doped GaN layers are the same.
4. The single particle reinforced P-GaN transistor according to claim 2 or 3, characterized in that: In the periodic PN junction stacked gate structure, the P-type doping concentration of the P-doped GaN layer is 1×10 16 cm -3 ~4×10 18 cm -3 .
5. The single particle reinforced P-GaN transistor according to claim 2 or 3, characterized in that: In the periodic PN junction stacked gate structure, the N-type doping concentration of the N-doped GaN layer is 1×10 16 cm -3 ~4×10 18 cm -3 .
6. The single particle reinforced P-GaN transistor according to claim 1, characterized in that: The thickness of the P-GaN layer ranges from 30 nm to 50 nm, and the length ranges from 1.5 μm to 2 μm.
7. The single particle reinforced P-GaN transistor according to claim 1, characterized in that: The P-type doping concentration of the P-GaN layer is 3×10 17 cm -3 ~2×10 19 cm -3 .