High-frequency input signal buffer stage circuit

Abstract

The embodiment of the invention relates to the technical field of image processing, and discloses a high-frequency input signal buffer stage circuit. The high-frequency input signal buffer stage circuit comprises a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, the grid electrode of the first transistor M1 is connected with an input signal Vin, the source electrode of the first transistor M1 is connected with the drain electrode of the third transistor M3, the source electrode of the third transistor M3 is connected with the drain electrode of the fourth transistor M4, the drain electrode of the first transistor M1 is connected with the source electrode of the second transistor M2, and the source electrode of the first transistor M1 is connected with an output signal Vout; wherein a first capacitor C1 is connected between the grid electrode of the first transistor M1 and the source electrode of the third transistor M3. By adopting the scheme, the jitter of the output signal can be effectively reduced when the high-frequency input signal is input, so that the analog-to-digital converter has good linearity under the high-frequency signal, the performance of the analog-to-digital converter under the 4G / 5GHz sub6G scene is greatly improved, and the high-precision transmission of the high-frequency signal is realized.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a high-frequency input signal buffer stage circuit. Background Art

[0002] In recent years, with the rapid development of mobile communication technology, the demand for integrated circuits has also increased. For example, in the aerospace field, in order to speed up data transmission rate and data accuracy, high-speed, high-precision analog-to-digital converter chips are usually required to support effective data transmission. Specifically, the chip quantizes and encodes the analog signal of the previous stage, so that it can transmit unaffected digital signals in various extreme scenarios. In this process, the processing of analog signals becomes particularly important. Due to the transistor characteristics of the chip, the analog signal exhibits a large nonlinear state of the transistor at high frequencies, which ultimately leads to the presence of undesirable harmonics in the transmitted signal, thereby affecting the quantization encoding process.

[0003] The current input buffer stage circuit adopts a conventional buffer stage gain circuit architecture and exhibits good linearity at low frequencies. However, when the signal frequency is in the sub6G frequency band of 4G / 5GHz, it will exhibit large nonlinearity, causing the signal and the harmonics caused by the signal nonlinearity to be processed together during signal processing, ultimately resulting in poor quality of the digital signal after quantization encoding. Summary of the invention

[0004] One purpose of the present application is to provide a high-frequency input signal buffer stage circuit, at least to solve the problem of poor digital signal quality caused by nonlinear output signal. The present application is provided with a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4 in the high-frequency input signal buffer stage circuit; the gate of the first transistor M1 is connected to the input signal Vin, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the source of the first transistor M1 is connected to the output signal Vout; wherein, a first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3. By adopting this scheme, the jitter of the output signal can be effectively reduced when the high-frequency input signal is input, so that it has good linearity under high-frequency signals, greatly improving the performance of the analog-to-digital converter in the sub6G scenario of 4G / 5GHz, and realizing high-precision transmission of high-frequency signals.

[0005] To achieve the above objectives, some embodiments of the present application provide the following aspects:

[0006] In a first aspect, some embodiments of the present application further provide a high-frequency input signal buffer stage circuit, the circuit comprising:

[0007] A first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0008] The gate of the first transistor M1 is connected to the input signal Vin, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the source of the first transistor M1 is connected to the output signal Vout;

[0009] A first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3 .

[0010] Furthermore, a second capacitor C2 is connected between the gate of the first transistor M1 and the gate of the second transistor M2.

[0011] Furthermore, the output signal Vout is connected to a switch φ_btst, the other end of the switch φ_btst is connected to a capacitor Cs, the other end of the capacitor Cs is connected to a switch φ_1a, and the other end of the switch φ_1a is grounded.

[0012] Furthermore, the capacitance of the first capacitor C1 is 1 / 2 of the capacitance of the capacitor Cs.

[0013] In a second aspect, some embodiments of the present application further provide an electronic device, comprising the high-frequency input signal buffer stage circuit as described above.

[0014] Compared with the related art, the solution provided by the embodiment of the present application is that a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4 are provided in the high-frequency input signal buffer stage circuit; the gate of the first transistor M1 is connected to the input signal Vin, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the source of the first transistor M1 is connected to the output signal Vout; wherein a first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3. By adopting this solution, the jitter of the output signal can be effectively reduced when a high-frequency input signal is input, so that it has good linearity under high-frequency signals, greatly improving the performance of the analog-to-digital converter in the 4G / 5GHz sub6G scenario, and realizing high-precision transmission of high-frequency signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0016] Figure 1 An exemplary flow chart of a high-frequency input signal buffer stage circuit provided according to some embodiments of the present application;

[0017] Figure 2 A circuit diagram of a comparative solution provided according to some embodiments of the present application;

[0018] Figure 3 An exemplary structural diagram of the electronic device is disclosed. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] First embodiment

[0021] The first embodiment of the present application relates to a high-frequency input signal buffer stage circuit. Figure 1 As shown, the circuit may include:

[0022] A first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0023] The gate of the first transistor M1 is connected to the input signal Vin, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the source of the first transistor M1 is connected to the output signal Vout;

[0024] A first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3 .

[0025] The first transistor M1 , the second transistor M2 , the third transistor M3 , and the fourth transistor M4 may be MOS transistors.

[0026] The full name of MOS transistor is Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOS tube.

[0027] From the perspective of physical structure, taking the common planar MOS tube as an example, there is an insulating silicon dioxide (SiO2) layer on the semiconductor substrate (such as P-type or N-type silicon wafer), which is called the gate oxide layer. There is a metal or polysilicon electrode on the gate oxide layer, which is called the gate (G). There are two other areas on the substrate, which are heavily doped by doping and are connected to the source (S) and drain (D) respectively.

[0028] From the perspective of material composition, metal gate materials are usually metals such as aluminum and copper or polysilicon; the gate oxide layer is an insulating material such as silicon dioxide; the material of the source and drain regions is different from the doping type of the substrate. For example, in an N-channel MOS tube, the substrate is a P-type semiconductor, and the source and drain are N-type heavily doped regions. The electric field controls the formation of the conductive channel: by applying a voltage to the gate, an electric field is generated to control the conductive channel between the source and the drain. When the gate voltage reaches a certain threshold, an inversion layer will be formed on the surface of the semiconductor, allowing conduction between the source and the drain.

[0029] Working principle of N-channel MOS tube: When the gate-source voltage (VGS) is greater than the threshold voltage (VT), an inversion layer of electrons (i.e., N-type channel) is formed on the surface of the P-type substrate. Electrons, as majority carriers, can move between the source and the drain, forming a current (IDS) from the source to the drain. At this time, if a voltage (VDS) is added between the drain and the source, the electrons will flow from the source to the drain under the action of the electric field. As VDS increases, IDS will also increase, but when VDS increases to a certain extent, saturation will occur, and IDS will basically no longer change with the increase of VDS.

[0030] Working principle of P-channel MOS tube: Contrary to N-channel, when the gate-source voltage (VGS) is less than the threshold voltage (VT), an inversion layer of holes (i.e., P-type channel) is formed on the surface of the N-type substrate, and holes move between the source and the drain as majority carriers to form current.

[0031] The input signal Vin here may be a high-frequency input signal, which is represented here as a voltage input signal.

[0032] A first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3 , which can stabilize the voltage difference between the gate and the source of the first transistor M1 , thereby achieving a more linear effect on the output signal Vout to a certain extent.

[0033] In this embodiment, optionally, a second capacitor C2 is connected between the gate of the first transistor M1 and the gate of the second transistor M2.

[0034] Among them, by setting the second capacitor, the gate voltage Vb1 of the second transistor M2 can be made to be in phase with the input signal Vin through the second capacitor. Because under normal circumstances, the gate and drain of the first transistor M1 have opposite phases, the drain of the first transistor M1 can be placed in a stable state through the setting of the second capacitor C2, thereby making the output signal Vout more linear.

[0035] Through such a configuration, the present solution can improve the linearity effect of the output signal Vout under the input of a high-frequency signal.

[0036] In this embodiment, optionally, the output signal Vout is connected to a switch φ_btst, the other end of the switch φ_btst is connected to a capacitor Cs, the other end of the capacitor Cs is connected to a switch φ_1a, and the other end of the switch φ_1a is grounded.

[0037] The switch φ_btst and the switch φ_1a can be opened and closed at the same time during operation. In the sampling phase of analog-to-digital conversion, the two switches are closed to collect the received output signal Vout through the capacitor Cs, and in the quantization phase, the two switches are opened to further process the collected output signal Vout through the capacitor Cs.

[0038] Through such a setting, the present solution can realize analog-to-digital conversion, thereby collecting and processing the output signal Vout to obtain corresponding results.

[0039] In this embodiment, optionally, the capacitance of the first capacitor C1 is 1 / 2 of the capacitance of the capacitor Cs.

[0040] In this solution, the capacitance of the first capacitor C1 can be set to 1 / 2 of the capacitance of the capacitor Cs. Through such a setting, not only the phase of the input signal Vin can be collected, so that the voltage difference between the gate and the source of the first transistor M1 is stable, but also the input signal Vin can be prevented from being excessively attenuated due to the intervention of the first capacitor C1, thereby affecting subsequent data collection and processing.

[0041] Figure 2 A circuit diagram of a comparison scheme provided according to some embodiments of the present application, comparing Figure 1 and Figure 2 , from the perspective of current, the comparison scheme adopts the classic buffer stage circuit architecture. The circuit mainly uses an N-type transistor to drive the current. According to Kirchhoff's law, the total current of each node is constant. When the current of the next stage appears iL When the current flowing through the first transistor M1 is no longer constant, it becomes i L +i b Therefore, the linearity of the first transistor M1 is affected by the subsequent stage i L The influence of current size, due to i L There is a capacitor Cs on the circuit. The capacitive reactance of the capacitor decreases as the frequency increases. Therefore, at high frequencies, i L It will show violent fluctuation characteristics.

[0042] In the solution of the first embodiment, a capacitor C1 is connected across the signal terminals of the first transistor M1. According to Kirchhoff's law, i L From C1 through M3 to Vout, due to the i L The current direction and the subsequent fluctuations at the Vout node cause the i L The current direction is opposite to that of the first transistor M1, and the disturbance caused by the subsequent fluctuation is approximately offset. Finally, the voltage Vout at the output end of the first transistor M1 is in a constant state. In addition, the existence of C2 makes Vb1 carry the information of the input signal Vin, which can ensure that the difference between the gate and the drain of the M1 tube is in a constant state. Therefore, when the signal is at a high frequency, the high-frequency signal is preferentially transmitted to Cs through the path of C1, and the state of the first transistor M1 is not affected by the subsequent stage i L impact.

[0043] In actual design, in order to take into account the matching characteristics of the Vin terminal, the magnitude of the first capacitor C1 is set to 1 / 2 of the capacitor Cs, which can not only improve the linearity of the high-frequency signal, but also appropriately reduce the matching characteristics requirements of the module for the previous stage. Since C2 only plays the role of capacitive coupling, its value is in the pF level. In this article, the value is 5pF, so that the signal on Vin will be transmitted to the gate end of M2 through the voltage divider of C2 and the parasitic capacitance of M2.

[0044] The solution provided by the embodiment of the present application is that a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4 are provided in a high-frequency input signal buffer stage circuit; the gate of the first transistor M1 is connected to the input signal Vin, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the source of the first transistor M1 is connected to the output signal Vout; wherein a first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3. By adopting this solution, the jitter of the output signal can be effectively reduced when a high-frequency input signal is input, so that the output signal has good linearity under high-frequency signals, greatly improving the performance of the analog-to-digital converter in the 4G / 5GHz sub6G scenario, and realizing high-precision transmission of high-frequency signals.

[0045] In addition, some embodiments of the present application also provide an electronic device. The electronic device may be a digital computer in various forms, such as a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, etc. The electronic device may also be a mobile device in various forms, such as a personal digital processing, a cellular phone, a smart phone, a wearable device, and other similar computing devices.

[0046] The electronic device comprises: the electronic device comprises the high-frequency input signal buffer stage circuit as described above. Figure 3 An exemplary structural diagram of the electronic device is disclosed. Figure 3 As shown, the electronic device includes: one or more processors 301, memory 302, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Among them, the components shown in this article, their connections and relationships, and their functions are only used as examples, and are not intended to limit the implementation of the present application described and / or required herein.

[0047] The electronic device may further include: an input device 303 and an output device 304. The processor 301, the memory 302, the input device 303 and the output device 304 may be connected via a bus or other means. Figure 3 The example of connecting through bus is taken in the following.

[0048] The input device 303 can receive input digital or character information, and generate key signal input related to the user settings and function control of the electronic device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick and other input devices. The output device 304 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The display device may include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display and a plasma display. In some embodiments, the display device may be a touch screen.

[0049] To provide interaction with a user, the electronic device may be a computer. The computer has: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball), through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0050] In the embodiments of the present application, a computer program / instruction is stored on a computer-readable medium, and when the computer program / instruction is executed by a processor, the steps of the method provided by any one or more of the above embodiments are implemented. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently without being assembled into the device. The above computer-readable medium carries one or more computer-readable instructions.

[0051] The memory 302 can be used as a non-transient computer-readable storage medium, which can be used to store non-transient software programs, non-transient computer executable programs and modules. The processor 301 executes various functional applications and data processing of the server by running the non-transient software programs, instructions and modules stored in the memory 302, so as to implement the program instructions / modules corresponding to the method provided by any one or more of the above embodiments in the embodiments of the present application.

[0052] The memory 302 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 302 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory 302 may optionally include a memory remotely arranged relative to the processor 301, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0053] It should be noted that the computer-readable medium described in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device.

[0054] Computer readable media include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0055] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0056] In the above-described embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. For example, it can be implemented by using an application specific integrated circuit (ASIC), a general-purpose computer or any other similar hardware device. In certain embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including relevant data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the present application can be implemented by hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0057] The computer program product provided in the embodiment of the present application includes one or more computer programs / instructions, and when the computer program / instructions are executed by the processor, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from a computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0058] The flow chart or block diagram in the accompanying drawings shows the possible architecture, function and operation of the equipment, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated system for hardware that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0059] The scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the equivalent elements of the claims are included in the present application. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in the device claim may also be implemented by one unit or device through software or hardware. The words "first", "second", etc. are only used to distinguish the description, and do not indicate any particular order, nor can they be understood as indicating or implying relative importance.

[0060] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily mention changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims, and the above embodiments should be regarded as exemplary and non-restrictive.

Claims

1. A high-frequency input signal buffer stage circuit, characterized in that: The circuit comprises: a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4; The gate of the first transistor M1 is connected to the input signal V in, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the source of the first transistor M1 is connected to the output signal Vout; A first capacitor C1 is connected between the gate of the first transistor M1 and the source of the third transistor M3.

2. The method according to claim 1, characterized in that A second capacitor C2 is connected between the gate of the first transistor M1 and the gate of the second transistor M2.

3. The method according to claim 1, characterized in that The output signal Vout is connected to a switch φ_btst, the other end of the switch φ_btst is connected to a capacitor Cs, the other end of the capacitor Cs is connected to a switch φ_1a, and the other end of the switch φ_1a is grounded.

4. The method according to claim 3, characterized in that: The capacitance of the first capacitor C1 is 1 / 2 of the capacitance of the capacitor Cs.

5. An electronic device, characterized in that: The electronic device comprises the high-frequency input signal buffer stage circuit as claimed in any one of claims 1 to 4.

Images