Formation method of semiconductor structure
By forming a sacrificial layer and a multi-layer oxide layer structure in the semiconductor structure, and using anisotropic etching process, the problems of oxide layer thickness and threshold voltage adjustment in the prior art are solved, and the performance and device stability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202310842978.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-10
- Publication Date
- 2025-01-14
AI Technical Summary
The performance of existing semiconductor structures has not yet reached its best state, especially with challenges in the thickness and threshold voltage regulation of the oxide layer, resulting in insufficient device performance and reliability.
A semiconductor structure forming method is adopted, including forming an oxide layer of the first and second regions on the substrate, and forming a sacrificial layer on the second region to expose the first region; forming a second on the oxide layer exposed by the sacrificial layer The oxide layer covers its side walls; the sacrificial layer and the first oxide layer at the bottom are removed by an anisotropic etching process to form an opening, and a third oxide layer is formed at the bottom of the opening for adjusting the thickness and voltage characteristics of the oxide layer .
Through this method, the steepness of the side wall of the oxide layer is improved, the side digging and slope problems are reduced, the performance of the device and threshold voltage stability are enhanced, and the read speed and life of the memory are improved.
Smart Images
Figure CN119317168A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] With the continuous improvement of semiconductor device manufacturing technology and the rapid development of integrated circuits, more special requirements are put forward for device processing technology. Among them, the requirements for the oxide layer of MOS device feature size entering the nano era are an obvious challenge. The preparation process of the oxide layer is a key technology in the semiconductor manufacturing process, which directly affects and determines the electrical characteristics and reliability of the device.
[0003] The key performance indicator of MOSFET devices is the threshold voltage, which is related to the thickness of the gate oxide layer. Generally speaking, the thicker the gate oxide layer, the higher the threshold voltage. Therefore, in the semiconductor field, adjusting the thickness of the gate oxide layer has become an important means of adjusting the threshold voltage of the device. At the same time, in order to meet the needs of devices with different threshold voltages, gate oxide layers of different thicknesses are usually formed.
[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region for forming a first device and a second region for forming a second device, the threshold voltage of the first device being greater than the threshold voltage of the second device; forming a first oxide layer on the substrate; forming a sacrificial layer on the first oxide layer in the second region, the sacrificial layer exposing the first region; forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, the second oxide layer covering part of the side wall of the sacrificial layer; using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer, so that the side walls of the first oxide layer and the second oxide layer in the first region and the top surface of the substrate in the second region form an opening; forming a third oxide layer on the substrate at the bottom of the opening, the top surface of the third oxide layer being lower than the top surface of the second oxide layer.
[0007] Optionally, in the step of forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, the first oxide layer and the second oxide layer in the first region are used as a first tunneling oxide layer; in the step of forming a third oxide layer on the substrate at the bottom of the opening, the third oxide layer is used as a second tunneling oxide layer; the method for forming the semiconductor structure also includes: forming a gate structure on the first tunneling oxide layer and the second tunneling oxide layer, the gate structure covering a portion of the top of the first tunneling oxide layer and a portion of the top of the second tunneling oxide layer, the gate structure including a floating gate layer, a gate inter-dielectric layer located on the floating gate layer, and a control gate layer located on the gate inter-dielectric layer.
[0008] Optionally, in the step of forming the sacrificial layer, the material of the sacrificial layer includes polysilicon.
[0009] Optionally, the process of forming the first oxide layer includes a dry oxygen oxidation process.
[0010] Optionally, the process of forming the second oxide layer is a high temperature oxidation process.
[0011] Optionally, in the step of forming the second oxide layer, the second oxide layer is also formed on the top surface and side wall of the sacrificial layer; in the step of removing the sacrificial layer and the first oxide layer at the bottom of the sacrificial layer in sequence using an anisotropic etching process, the second oxide layer at the top surface of the sacrificial layer, the sacrificial layer and the first oxide layer at the bottom of the sacrificial layer are removed in sequence.
[0012] Optionally, the steps of using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer include: using an anisotropic etching process to perform main etching treatment to remove the sacrificial layer; using an anisotropic etching process to perform over-etching treatment to remove the first oxide layer in the second area.
[0013] Optionally, the steps of sequentially removing the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer by using an anisotropic etching process include: forming a graphic layer covering the second oxide layer on the first area, a graphic opening being formed in the graphic layer, and the graphic opening exposing the top of the sacrificial layer; using the graphic layer as a mask, sequentially removing the sacrificial layer exposed by the graphic opening and the first oxide layer located at the bottom of the sacrificial layer by using an anisotropic etching process; and removing the graphic layer.
[0014] Optionally, the anisotropic etching process includes an anisotropic dry etching process.
[0015] Optionally, the method for forming the semiconductor structure also includes: after forming the second oxide layer and before using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer, heat treating the second oxide layer to improve the density of the second oxide layer.
[0016] Optionally, the heat treatment is performed using an annealing process.
[0017] Optionally, the annealing process includes a rapid thermal annealing process.
[0018] Optionally, the step of forming the sacrificial layer includes: forming a sacrificial material layer on the first oxide layer; forming a mask layer on the sacrificial material layer in the second area; using the mask layer as a mask, patterning the sacrificial material layer, and the remaining sacrificial material layer in the second area is used as the sacrificial layer.
[0019] Optionally, in the step of forming the sacrificial layer, a thickness ratio between the sacrificial layer and the first oxide layer is 50:1 to 80:1.
[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0021] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a sacrificial layer is formed on the first oxide layer of the second region; a second oxide layer is formed on the first oxide layer exposed by the sacrificial layer, and the second oxide layer covers part of the side wall of the sacrificial layer, so that the second oxide layer is only formed on the first oxide layer of the first region; in the step of removing the first oxide layer of the second region, the sacrificial layer can protect the substrate, so an anisotropic etching process can be used to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer. The anisotropic etching process has an anisotropic etching process and has a high control ability over the etching profile, which is beneficial to reducing the probability of side digging problems. In addition, there is no need to etch the second oxide layer, and it is also beneficial to reduce the probability of a slope problem on the side wall of the opening due to the difference in etching rates of the second oxide layer and the first oxide layer, thereby reducing the width of the slope formed on the side wall of the opening or eliminating the slope, thereby improving the steepness of the side wall of the opening, and correspondingly improving the performance of the semiconductor structure.
[0022] In an optional solution, in the step of forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, the first oxide layer and the second oxide layer in the first region are used as a first tunneling oxide layer; in the step of forming a third oxide layer on the substrate at the bottom of the opening, the third oxide layer is used as a second tunneling oxide layer; the method for forming the semiconductor structure further includes: forming a gate structure on the first tunneling oxide layer and the second tunneling oxide layer, the gate structure covering a portion of the top of the first tunneling oxide layer and a portion of the top of the second tunneling oxide layer, the gate structure including a floating gate layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer. The embodiment of the present invention reduces the probability of a slope on the side wall of the first tunneling oxide layer at the boundary between the first region and the second region, improves the steepness of the side wall of the first tunneling oxide layer and the thickness consistency of the boundary of the first tunneling oxide layer, correspondingly reduces the problem of threshold voltage shift (Vt Shift) of the first device, improves the stability of the threshold voltage of the first device, and is also conducive to reducing the probability of electron leakage, correspondingly improves the speed of reading and erasing the memory, and ensures the life of the memory.
[0023] In an optional scheme, the method for forming the semiconductor structure also includes: after forming the second oxide layer and before using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer, heat treating the second oxide layer to increase the density of the second oxide layer, thereby increasing the hardness and etching resistance of the second oxide layer. In the subsequent step of sequentially removing the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer using an anisotropic etching process, the probability of damage to the side wall of the second oxide layer can be further reduced, thereby further reducing the probability of side hollowing in the step of removing the first oxide layer at the bottom of the sacrificial layer, and further improving the steepness of the side wall of the opening. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 to Figure 2 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0025] Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0026] As can be seen from the background technology, the performance of the current semiconductor structure needs to be improved. Taking the formation of EEPROM (Electrically Erasable Programmable read only memory) as an example, the reasons why the performance of the semiconductor structure needs to be improved are analyzed in combination with a method for forming a semiconductor structure.
[0027] Figure 1 to Figure 2 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0028] refer to Figure 1 , providing a substrate 11, wherein the substrate 11 includes a first region 10a for forming a first device and a second region 10b for forming a second device, wherein a threshold voltage of the first device is greater than a threshold voltage of the second device.
[0029] Continue to refer Figure 1 , forming a first oxide layer 12 on the substrate 11 ; and forming a second oxide layer 13 on the first oxide layer 12 .
[0030] refer to Figure 2 , using a wet etching process to remove the second oxide layer 13 and the first oxide layer 12 of the second region 10b, and the remaining first oxide layer 12 and the second oxide layer 13 located in the first region 10a are used to form a first tunneling oxide layer (not marked), and the first tunneling oxide layer and the substrate 11 of the second region 10b form an opening 14.
[0031] Subsequent steps further include: forming a second tunneling oxide layer on the substrate 11 at the bottom of the opening 14 , wherein the thickness of the second tunneling oxide layer is smaller than the thickness of the first tunneling oxide layer.
[0032] The method for forming a semiconductor structure is used to form an EEPROM. In the step of removing the second oxide layer 13 and the first oxide layer 12 of the second region 10b by a wet etching process, the wet etching process is an isotropic etching process, and the control ability of the etching profile is poor. It is easy to etch the first oxide layer 12 and the second oxide layer 13 in the lateral direction, and the etching rates of the first oxide layer 12 and the second oxide layer 13 are different, which easily leads to poor quality of the profile morphology of the opening, and a large slope (such as Figure 2 The opening 14 is used as a tunnel oxide window (Tunnel Oxide Window, TOW), and its boundary forms a relatively large slope, which is easy to reduce the reading and erasing speed of the memory and also the life of the memory.
[0033] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region for forming a first device and a second region for forming a second device, the threshold voltage of the first device being greater than the threshold voltage of the second device; forming a first oxide layer on the substrate; forming a sacrificial layer on the first oxide layer in the second region, the sacrificial layer exposing the first region; forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, the second oxide layer covering part of the side wall of the sacrificial layer; using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer, so that the side walls of the first oxide layer and the second oxide layer in the first region and the top surface of the substrate in the second region form an opening; forming a third oxide layer on the substrate at the bottom of the opening, the top surface of the third oxide layer being lower than the top surface of the second oxide layer.
[0034] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a sacrificial layer is formed on the first oxide layer of the second region; a second oxide layer is formed on the first oxide layer exposed by the sacrificial layer, and the second oxide layer covers part of the side wall of the sacrificial layer, so that the second oxide layer is only formed on the first oxide layer of the first region; in the step of removing the first oxide layer of the second region, the sacrificial layer can protect the substrate, so an anisotropic etching process can be used to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer. The anisotropic etching process has an anisotropic etching process and has a high control ability over the etching profile, which is beneficial to reducing the probability of side digging problems. In addition, there is no need to etch the second oxide layer, and it is also beneficial to reduce the probability of a slope problem on the side wall of the opening due to the difference in etching rates of the second oxide layer and the first oxide layer, thereby reducing the width of the slope formed on the side wall of the opening or eliminating the slope, thereby improving the steepness of the side wall of the opening, and correspondingly improving the performance of the semiconductor structure.
[0035] In an optional solution, in the step of forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, the first oxide layer and the second oxide layer in the first region are used as a first tunneling oxide layer; in the step of forming a third oxide layer on the substrate at the bottom of the opening, the third oxide layer is used as a second tunneling oxide layer; the method for forming the semiconductor structure further includes: forming a gate structure on the first tunneling oxide layer and the second tunneling oxide layer, the gate structure covering a portion of the top of the first tunneling oxide layer and a portion of the top of the second tunneling oxide layer, the gate structure including a floating gate layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer. The embodiment of the present invention reduces the probability of a slope on the side wall of the first tunneling oxide layer at the boundary between the first region and the second region, improves the steepness of the side wall of the first tunneling oxide layer and the thickness consistency of the boundary of the first tunneling oxide layer, correspondingly reduces the problem of threshold voltage shift (Vt Shift) of the first device, improves the stability of the threshold voltage of the first device, and is also conducive to reducing the probability of electron leakage, correspondingly improves the speed of reading and erasing the memory, and ensures the life of the memory.
[0036] In an optional scheme, the method for forming the semiconductor structure also includes: after forming the second oxide layer and before using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer, heat treating the second oxide layer to increase the density of the second oxide layer, thereby increasing the hardness and etching resistance of the second oxide layer. In the subsequent step of sequentially removing the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer using an anisotropic etching process, the probability of damage to the side wall of the second oxide layer can be further reduced, thereby further reducing the probability of side hollowing in the step of removing the first oxide layer at the bottom of the sacrificial layer, and further improving the steepness of the side wall of the opening.
[0037] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0038] Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0039] refer to Figure 3 , providing a substrate 100, wherein the substrate 100 includes a first region 100a for forming a first device and a second region 100b for forming a second device, wherein a threshold voltage of the first device is greater than a threshold voltage of the second device.
[0040] The substrate 100 is used to provide a process platform for subsequent process steps.
[0041] In this embodiment, the substrate 100 is used to provide a process platform for forming an EEPROM (Electrically Erasable Programmable read only memory) as an example for description. In other embodiments, the substrate can also be used to form other types of memory devices.
[0042] In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.
[0043] In this embodiment, the substrate 100 includes a first region 100a for forming a first device and a second region 100b for forming a second device. The threshold voltage of the first device is greater than the threshold voltage of the second device. The threshold voltages of the first device and the second device are different, thereby meeting the needs of devices with different threshold voltage types.
[0044] refer to Figure 3 , a first oxide layer 110 is formed on the substrate 100 .
[0045] The first oxide layer 110 is used to form an oxide layer of the first region 100 a.
[0046] In this embodiment, the material of the first oxide layer 110 is silicon oxide.
[0047] In this embodiment, the process of forming the first oxide layer 110 includes a dry oxidation process. The oxide film generated by the dry oxidation process has high density and few defects, which is conducive to improving the density and electrical properties of the first oxide layer 110.
[0048] In other embodiments, based on actual process requirements, other processes may be used to form the first oxide layer.
[0049] refer to Figure 4 , a sacrificial layer 120 is formed on the first oxide layer 110 in the second region 100 b , and the sacrificial layer 120 exposes the first region 100 a .
[0050] The sacrificial layer 120 is used to protect the substrate 100 in the subsequent step of removing the first oxide layer 110 in the second region 100 b , so that an anisotropic etching process can be used to remove the first oxide layer 110 in the second region 100 b .
[0051] In addition, the sacrificial layer 120 is also used to define the formation position of the subsequent second oxide layer, so that the subsequent second oxide layer can be formed only on the first area 100a, thereby eliminating the subsequent step of removing the second oxide layer located in the second area 100b. Moreover, the side wall of the sacrificial layer 120 is also used to provide support for the edge of the second oxide layer, which is beneficial to improve the steepness and cross-sectional morphology quality of the side wall of the subsequent second oxide layer, and correspondingly helps to further reduce the probability of generating a slope at the edge of the second oxide layer.
[0052] The material selected for the sacrificial layer 120 is different from the materials of the first oxide layer 110 and the substrate 100, so that in the subsequent step of removing the sacrificial layer 120, the sacrificial layer 120 can have an etching selectivity ratio with the first oxide layer 110 and with the substrate 100, thereby reducing the probability of the process of removing the sacrificial layer 120 causing damage to the first oxide layer 110 and the substrate 100.
[0053] As an example, the material of the sacrificial layer 120 is polysilicon. Polysilicon is a commonly used material in semiconductor processes. By selecting polysilicon as the material of the sacrificial layer 120, it is beneficial to improve process compatibility, reduce process costs and process risks; moreover, polysilicon has a relatively hard texture, which is beneficial to improve the protective effect of the sacrificial layer 120 on the substrate 100 in the subsequent step of removing the first oxide layer 110 located in the second region 100b, and further reduce the probability of damage to the substrate 100.
[0054] In other embodiments, based on actual process requirements, the material of the sacrificial layer may also be other suitable materials.
[0055] It should be noted that the thickness ratio of the sacrificial layer 120 to the first oxide layer 110 should not be too small, otherwise in the subsequent step of removing the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120, after removing the sacrificial layer 120 to expose the first oxide layer 110, the first oxide layer 110 is still relatively thick, which may easily lead to the process of removing the first oxide layer 110 in the second area 100b. The effect of reducing the probability of damage to the substrate 100 is not obvious. For this reason, in this embodiment, in the step of forming the sacrificial layer 120, the thickness ratio between the sacrificial layer 120 and the first oxide layer 110 is at least 50:1.
[0056] It should also be noted that the thickness ratio of the sacrificial layer 120 to the first oxide layer 110 should not be too large, otherwise, when the thickness of the first oxide layer 110 remains unchanged, the thickness of the sacrificial layer 120 is likely to be too large, which in turn may lead to a long time required for subsequent removal of the sacrificial layer 120, which may reduce production efficiency and cause unnecessary waste of materials. To this end, in this embodiment, the thickness ratio of the sacrificial layer 120 to the first oxide layer 110 is 50:1 to 80:1.
[0057] In this embodiment, the step of forming the sacrificial layer 120 includes: forming a sacrificial material layer (not shown) on the first oxide layer 110; forming a mask layer (not shown) on the sacrificial material layer in the second area 100b; using the mask layer as a mask, patterning the sacrificial material layer, and the remaining sacrificial material layer located in the second area 100b is used as the sacrificial layer 120.
[0058] The sacrificial material layer is used to form a sacrificial layer 120 through a patterning process.
[0059] As an example, the sacrificial material layer is formed by using a chemical vapor deposition process, which has high process maturity, high process compatibility, and low process cost.
[0060] The mask layer is used as a mask for patterning the sacrificial material layer.
[0061] In this embodiment, the material of the mask layer includes photoresist.
[0062] In this embodiment, the mask layer is used as a mask and an anisotropic etching process is used to pattern the sacrificial material layer. The anisotropic etching process has high pattern transfer accuracy. Specifically, the anisotropic etching process can be an anisotropic dry etching process.
[0063] refer to Figure 5 A second oxide layer 130 is formed on the first oxide layer 110 exposed by the sacrificial layer 120 , and the second oxide layer 130 covers a portion of the sidewall of the sacrificial layer 120 .
[0064] The second oxide layer 130 and the first oxide layer 110 form an oxide layer of the first region 100 a .
[0065] Specifically, in this embodiment, in the step of forming the second oxide layer 130 on the first oxide layer 110 exposed by the sacrificial layer 120 , the first oxide layer 110 and the second oxide layer 130 in the first region 100 a are used as a first tunneling oxide (TOX) layer 210 .
[0066] Subsequent steps also include: forming a gate structure on the first tunneling oxide layer 210, the gate structure including a floating gate layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer. The first tunneling oxide layer 210 is used to provide a tunneling channel for electrons from the substrate 100 to the floating gate layer, and the first tunneling oxide layer 210 is also used to isolate the gate structure from the substrate of the first region 100a.
[0067] In the present embodiment, since a sacrificial layer is formed on the first oxide layer in the second region before forming the second oxide layer 130, the second oxide layer 130 is only formed on the first oxide layer in the first region. Accordingly, there is no need to subsequently etch the second oxide layer, thereby reducing the probability of damage to the second oxide layer. In addition, the second oxide layer 130 covers the side wall of the sacrificial layer 120, which is also beneficial to improving the steepness of the side wall of the sacrificial layer 120.
[0068] In this embodiment, the material of the second oxide layer 130 is silicon oxide. In this embodiment, the material of the adhesive layer 103 is HTO. Specifically, the material of the adhesive layer 103 is silicon oxide.
[0069] In this embodiment, the process of forming the second oxide layer 130 includes a high temperature oxidation (HTO) process. The film formed by the HTO process has high thickness uniformity and density, which is conducive to improving the film quality of the second oxide layer 130 and further improving the electrical performance of the first tunneling oxide layer 210.
[0070] In other embodiments, based on actual process requirements, other suitable processes may be used to form the second oxide layer.
[0071] In this embodiment, in the step of forming the second oxide layer 130 , the second oxide layer 130 is also formed on the top surface and sidewalls of the sacrificial layer 120 (not shown).
[0072] In this embodiment, the method for forming the semiconductor structure also includes: after forming the second oxide layer 130 and before using an anisotropic etching process to sequentially remove the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120, heat treating the second oxide layer 130 to improve the density of the second oxide layer 130.
[0073] By heat treating the second oxide layer 130 to improve the density of the second oxide layer 130, not only the film quality of the second oxide layer 130 is improved, and then the electrical properties of the first tunneling oxide layer 210 are improved, but also the etching resistance of the second oxide layer 130 is improved. In the subsequent steps of using an anisotropic etching process to sequentially remove the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120, the probability of damage to the second oxide layer 130 can be further reduced, and then the side wall steepness and cross-sectional morphology quality of the subsequently formed opening are further improved, and the slope problem of the side wall of the opening is further improved accordingly.
[0074] In this embodiment, an annealing process is used to perform the heat treatment.
[0075] As an example, the annealing process includes a rapid thermal annealing process.
[0076] refer to Figure 6 The sacrificial layer 120 and the first oxide layer 110 at the bottom of the sacrificial layer 120 are removed in sequence by an anisotropic etching process, so that the side walls of the first oxide layer 110 and the second oxide layer 130 in the first area 100a and the top surface of the substrate 100 in the second area 100b form an opening 140.
[0077] In this embodiment, before forming the second oxide layer 130, a sacrificial layer 120 is also formed on the first oxide layer 110 of the second region 100b, so that in the step of forming the second oxide layer 130, the second oxide layer 130 is formed only on the first oxide layer 110 exposed by the sacrificial layer 120, and the second oxide layer 130 covers a portion of the side wall of the sacrificial layer 120, so that the second oxide layer 130 is only formed on the first oxide layer 110 of the first region 100a.
[0078] Correspondingly, in the step of removing the first oxide layer 110 of the second area 100b, the sacrificial layer 120 can protect the substrate 100, so an anisotropic etching process can be used to remove the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120 in sequence. The anisotropic etching process has an anisotropic etching process, and has a high control ability over the etching profile, which is beneficial to reducing the probability of side digging problems. There is no need to etch the second oxide layer 130, and it is also beneficial to reduce the probability of a slope problem on the side wall of the opening 140 caused by the difference in etching rate between the second oxide layer 130 and the first oxide layer 110, thereby reducing the width of the slope formed on the side wall of the opening 140 or eliminating the slope, thereby improving the steepness of the side wall of the opening 140 and correspondingly improving the performance of the semiconductor structure.
[0079] The opening 140 is used to provide a space for subsequently forming a third oxide layer on the substrate in the second region 100 b.
[0080] In this embodiment, the formation of a memory is used as an example for explanation. The opening 140 is used as a tunnel oxide window (TOW), and the cross-sectional morphology quality of its boundary is crucial to the read and erase speed and life of the memory. In this embodiment, the sidewall steepness and cross-sectional morphology quality of the opening 140 are high, which correspondingly improves the read and erase speed of the memory and is also conducive to extending the life of the memory; and the threshold voltage is related to the thickness of the gate oxide layer. In this embodiment, the thickness of the third oxide layer formed subsequently is less than the thickness of the first tunnel oxide layer 210, so that the threshold voltage of the first device is greater than the threshold voltage of the second device. The cross-sectional morphology of the opening 140 is good, and the probability of generating a slope at the boundary of the opening 140 is low, which is conducive to adjusting the threshold voltage of the first device and the second device by forming tunnel oxide layers of different thicknesses in the first region 100a and the second region 100b, and the threshold voltage stability of the first device and the second device at the boundary is good.
[0081] In this embodiment, in the step of forming the second oxide layer 130, the second oxide layer 130 is also formed on the top surface and side wall of the sacrificial layer 120. Therefore, in the step of removing the sacrificial layer 120 and the first oxide layer 110 at the bottom of the sacrificial layer 120 in sequence using an anisotropic etching process, the second oxide layer 130 located on the top surface of the sacrificial layer 120, the sacrificial layer 120 and the first oxide layer 110 at the bottom of the sacrificial layer 120 are removed in sequence.
[0082] In this embodiment, an anisotropic etching process is used to sequentially remove the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120, including: using an anisotropic etching process to perform a main etching process to remove the sacrificial layer 120; using an anisotropic etching process to perform an over-etching (Over Etch, OE) process to remove the first oxide layer 110 of the second region 100b.
[0083] In this embodiment, during the main etching process, the sacrificial layer 120 can protect the substrate 100 .
[0084] In this embodiment, compared with the thickness of the sacrificial layer 120, the thickness of the first oxide layer 110 is smaller. Therefore, after the main etching process, the first oxide layer 110 of the second area 100b can be removed during the over-etching process, and the time required to remove the first oxide layer 110 of the second area 100b is shorter, and the probability of damaging the second oxide layer 130 is low.
[0085] In this embodiment, an anisotropic etching process is used to sequentially remove the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120, including the following steps: forming a graphic layer (not shown) covering the second oxide layer 130 on the first area 100a, wherein a graphic opening (not shown) is formed in the graphic layer, and the graphic opening exposes the top of the sacrificial layer 120; using the graphic layer as a mask, an anisotropic etching process is used to sequentially remove the sacrificial layer 120 exposed by the graphic opening and the first oxide layer 110 located at the bottom of the sacrificial layer 120; and removing the graphic layer.
[0086] The pattern layer is used to protect the first region 100 a in the subsequent step of removing the sacrificial layer 120 and the first oxide layer 110 located at the bottom of the sacrificial layer 120 .
[0087] In this embodiment, the material of the pattern layer includes photoresist.
[0088] In this embodiment, the anisotropic etching process includes an anisotropic dry etching process. The dry etching process is easy to achieve anisotropic etching, has high controllability over the etching profile, and is easy to achieve a high etching selectivity, thereby further reducing the probability of damage to the second oxide layer 130 and the substrate 100.
[0089] In this embodiment, the process of removing the graphic layer includes one or both of an ashing process and a wet stripping process.
[0090] refer to Figure 7 The method for forming the semiconductor structure further includes: forming a third oxide layer 150 on the substrate 100 at the bottom of the opening 140 , wherein a top surface of the third oxide layer 150 is lower than a top surface of the second oxide layer 130 .
[0091] In this embodiment, the third oxide layer 150 is used as the second tunnel oxide layer 220, and the thickness of the second tunnel oxide layer 220 is less than the thickness of the first tunnel oxide layer 210, so that the threshold voltage of the first device and the second device can be adjusted by adjusting the thickness of the tunnel oxide layer, thereby making the threshold voltage of the first device greater than the threshold voltage of the second device.
[0092] In this embodiment, the material of the third oxide layer 150 includes silicon oxide.
[0093] In this embodiment, the method for forming the semiconductor structure also includes: forming a gate structure (not shown) on the first tunneling oxide layer 210 and the second tunneling oxide layer 220, the gate structure covering a portion of the top of the first tunneling oxide layer 210 and a portion of the top of the second tunneling oxide layer 220, the gate structure including a floating gate layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer.
[0094] In the present embodiment, the probability of a slope being generated on the side wall of the first tunneling oxide layer at the boundary between the first region and the second region is reduced, the steepness of the side wall of the first tunneling oxide layer and the thickness consistency of the boundary of the first tunneling oxide layer are improved, and the problem of threshold voltage shift (Vt Shift) generated by the first device is correspondingly reduced, and the stability of the threshold voltage of the first device is improved. Moreover, it is also beneficial to reduce the probability of electron leakage, and correspondingly improve the reading and erasing speed of the memory, and ensure the life of the memory.
[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region for forming a first device and a second region for forming a second device, wherein a threshold voltage of the first device is greater than a threshold voltage of the second device; forming a first oxide layer on the substrate; forming a sacrificial layer on the first oxide layer in the second region, wherein the sacrificial layer exposes the first region; forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, wherein the second oxide layer covers a portion of the sidewall of the sacrificial layer; Using an anisotropic etching process, sequentially remove the sacrificial layer and the first oxide layer at the bottom of the sacrificial layer, so that the side walls of the first oxide layer and the second oxide layer in the first region and the top surface of the substrate in the second region form an opening; A third oxide layer is formed on the substrate at the bottom of the opening, wherein a top surface of the third oxide layer is lower than a top surface of the second oxide layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming a second oxide layer on the first oxide layer exposed by the sacrificial layer, the first oxide layer and the second oxide layer in the first region are used as a first tunneling oxide layer; In the step of forming a third oxide layer on the substrate at the bottom of the opening, the third oxide layer is used as a second tunneling oxide layer; The method for forming the semiconductor structure also includes: forming a gate structure on the first tunneling oxide layer and the second tunneling oxide layer, the gate structure covering a portion of the top of the first tunneling oxide layer and a portion of the top of the second tunneling oxide layer, the gate structure including a floating gate layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer.
3. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the sacrificial layer, the material of the sacrificial layer includes polysilicon.
4. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first oxide layer includes a dry oxygen oxidation process.
5. The method for forming a semiconductor structure according to claim 1, wherein: The second oxide layer is formed by a high temperature oxidation process.
6. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the second oxide layer, the second oxide layer is also formed on the top surface and side walls of the sacrificial layer; In the step of sequentially removing the sacrificial layer and the first oxide layer at the bottom of the sacrificial layer by using an anisotropic etching process, the second oxide layer on the top surface of the sacrificial layer, the sacrificial layer and the first oxide layer at the bottom of the sacrificial layer are sequentially removed.
7. The method for forming a semiconductor structure according to claim 1, wherein: The steps of using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer include: using an anisotropic etching process to perform main etching treatment to remove the sacrificial layer; using an anisotropic etching process to perform over-etching treatment to remove the first oxide layer in the second area.
8. The method for forming a semiconductor structure according to claim 1, wherein: The step of sequentially removing the sacrificial layer and the first oxide layer at the bottom of the sacrificial layer by an anisotropic etching process comprises: forming a pattern layer covering the second oxide layer on the first area, wherein a pattern opening is formed in the pattern layer, and the pattern opening exposes the top of the sacrificial layer; Using the pattern layer as a mask, an anisotropic etching process is used to sequentially remove the sacrificial layer exposed by the pattern opening and the first oxide layer located at the bottom of the sacrificial layer; The graphic layer is removed.
9. The method for forming a semiconductor structure according to claim 1, wherein: The anisotropic etching process includes an anisotropic dry etching process.
10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure also includes: after forming the second oxide layer and before using an anisotropic etching process to sequentially remove the sacrificial layer and the first oxide layer located at the bottom of the sacrificial layer, heat treating the second oxide layer to improve the density of the second oxide layer.
11. The method for forming a semiconductor structure according to claim 10, wherein: The heat treatment is performed by an annealing process.
12. The method for forming a semiconductor structure according to claim 11, wherein: The annealing process includes a rapid thermal annealing process.
13. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the sacrificial layer includes: forming a sacrificial material layer on the first oxide layer; forming a mask layer on the sacrificial material layer in the second area; using the mask layer as a mask, patterning the sacrificial material layer, and the remaining sacrificial material layer in the second area is used as the sacrificial layer.
14. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the sacrificial layer, a thickness ratio between the sacrificial layer and the first oxide layer is 50:1 to 80:1.