Method, controller and memory for grouping memory blocks in memory

Abstract

Disclosed are a method, controller, and memory for grouping memory blocks in a memory. The method includes: calculating, based on the memory, the minimum number of die required for the maximum performance of a die combination in a single channel to be greater than or equal to the preset performance of the single channel; and determining whether the minimum number of die is less than half the number of die connected to a single channel of the memory. If so, grouping the memory blocks based on the minimum number of die. This method improves memory stability by constructing smaller super blocks without compromising performance.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of storage technology, and in particular to a method for grouping storage blocks in a memory, a controller, and a memory. Background Art

[0002] Solid-state drives (SSDs) are storage hard drives made with solid-state electronic memory chips. These hard drives include a controller and storage media. Currently, the most popular SSDs use NAND flash chips as the storage medium to store data.

[0003] As NAND flash capacity grows, the number of dies it contains increases. Generally, in SSDs, read and write operations process multiple different storage blocks on multiple dies belonging to the same Super Block in parallel. However, garbage collection is performed on the entire Super Block. Therefore, the organization of the Super Block must balance overall system performance (including read and write operations and garbage collection performance). The organization of the Super Block also significantly impacts SSD stability. Specifically, when writing data to the individual storage blocks within a Super Block, the Super Block is closed only after all the storage blocks in the Super Block have been written. Because a closed Super Block is more stable than an unclosed Super Block, writing to a Super Block containing too many storage blocks takes a long time. During this time, the storage blocks within the Super Block are unstable. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a method, a controller, and a memory for grouping memory blocks in a memory, so as to improve the stability of the memory by constructing smaller super blocks without affecting the performance.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for grouping storage blocks in a memory is provided. The memory includes a storage medium and a controller. The storage medium is composed of multiple dies, each die is divided into multiple planes, and each plane is divided into multiple storage blocks. The controller connects the multiple dies via multiple channels. The method is executed by the controller and includes grouping the multiple storage blocks to form a super block. The grouping includes:

[0006] Based on the memory, calculating the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the single channel; and

[0007] It is determined whether the minimum number of dies is less than or equal to half of the number of dies connected to a single channel of the memory; if so, the memory blocks are grouped based on the minimum number of dies.

[0008] Optionally, the method further includes: if the minimum number of dies is greater than half of the number of dies connected to a single channel, grouping the storage blocks according to the number of dies in each channel to form a super block.

[0009] Optionally, the preset performance of each channel is equal to a preset performance index of the memory divided by the number of the multiple channels.

[0010] Optionally, the minimum number of dies required to be included when calculating the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the single channel includes:

[0011] Multiplying the sum of the transmission time of data transmitted by a single die and the writing time of the data from the single die to the storage block by the preset performance of the single channel, and dividing the obtained product by the total transmission data volume of the single die to obtain the target number of dies;

[0012] The target number of dies is rounded up to obtain the minimum number of dies.

[0013] Optionally, the controller performs a write operation, a read operation, or garbage collection on the storage medium based on the super block.

[0014] Optionally, the same number of dies are selected in parallel from the dies connected to each channel according to the minimum number of dies to form a super block.

[0015] Optionally, grouping the memory blocks based on the minimum number of dies includes: if the number of dies connected to a single channel is an integer multiple of the minimum number of dies, evenly dividing the memory blocks in the same row contained in multiple dies of the minimum number of dies.

[0016] Optionally, the grouping of storage blocks based on the minimum number of dies includes: if the number of dies connected to the same channel is not an integer multiple of the minimum number of dies, first evenly dividing the number of storage blocks in the same row contained in multiple dies with the minimum number of dies, and then adding the remaining storage blocks to any group.

[0017] According to a second aspect of an embodiment of the present disclosure, a memory controller is provided, wherein the memory includes a storage medium and the controller, wherein the storage medium is composed of a plurality of dies, each of which is divided into a plurality of planes, each of which is divided into a plurality of storage blocks, and the controller connects the plurality of dies through a plurality of channels, and the controller executes the method described in the first aspect to group the storage blocks to form a super block.

[0018] According to a third aspect of an embodiment of the present disclosure, a memory is provided, comprising the above-mentioned controller and a storage medium.

[0019] The method for grouping storage blocks provided by the embodiments of the present disclosure constructs smaller super blocks while ensuring no performance loss, thereby reducing, for example, the unit time of garbage collection and the recovery time of system startup, saving the flash memory capacity occupied by the system, and improving the stability of the flash memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the embodiments of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1 shows a schematic block diagram of a solid state drive;

[0022] Figure 2 is an example diagram illustrating the relationship between dies, planes, memory blocks, and super blocks;

[0023] Figure 3 and Figure 4 Describes the timing diagram of write operations in two different situations;

[0024] Figure 5 It is used to illustrate the embodiment of the present invention. Figure 2 The flash memory chip 230 is shown as a redesigned super block;

[0025] Figure 6 is a flowchart of a method for operating a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0027] The following describes the embodiments of the present disclosure based on examples, but the embodiments of the present disclosure are not limited to these examples. In the detailed description of the embodiments of the present disclosure below, certain specific details are described in detail. Those skilled in the art can fully understand the embodiments of the present disclosure without the description of these details. To avoid obscuring the essence of the embodiments of the present disclosure, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0028] Unless the context clearly requires otherwise, throughout the specification and claims, words such as "include," "comprising," and similar expressions should be interpreted as inclusive rather than exclusive or exhaustive; that is, as meaning "including but not limited to." In the description of the embodiments of the present disclosure, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the embodiments of the present disclosure, unless otherwise specified, "a plurality" means two or more.

[0029] The following is a further detailed description of the specific implementation of the embodiments of the present disclosure in conjunction with the accompanying drawings and examples. However, before describing the embodiments in detail, it should be noted that the various embodiments of the present disclosure are applicable to both solid-state drives and other storage products such as UFS.

[0030] Figure 1 A schematic block diagram of a solid-state drive according to an embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, the computer system 100 includes a host 110 and a solid-state drive. The solid-state drive includes a controller 120 and a storage medium 130. The controller 120 is connected to the host 110 and is configured to receive read and write commands from the host 110. The controller 120 is connected to the storage medium 130 and is configured to read data from and write data to the storage medium 130. The controller 120 is also configured to return read data to the host 110 in response to a read command, or to receive data from the host 110 to be written to the storage medium 130.

[0032] The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a media controller 128. The host interface 121 of the controller 120 is connected to the host 110 to transmit data and read and write commands. The processor 123 is connected to the host interface 121, the cache unit 124, and the media controller 128. The processor 123 parses the read and write commands and performs read and write operations. The cache unit 124 is, for example, an SRAM, which is used to store a mapping table. The processor 123 is also used to execute the core software layer of memory control, namely the FTL (Flash Translation Layer). The FTL consists of several programs. The processor 123 executes the programs so that when a read or write command is received, it can convert the command to complete the reading and writing of the storage medium 130, allowing the file system and operating system of the host 110 to access the storage medium as if it were accessing its own memory. The FTL also has features such as support for bad storage block management, wear leveling, garbage collection, power failure recovery, and write balancing technology.

[0033] The cache unit 124 can use SRAM and / or DRAM. In comparison, SRAM has a speed advantage as a cache, but it is more expensive and has a smaller storage capacity per unit space. Accordingly, to improve cache space utilization, DRAM-less solid-state drives (without DRAM) use a two-level mapping table for address management, that is, the first-level mapping table is stored in SRAM, and the second-level mapping table is stored in the storage medium 130.

[0034] The media controller 128 controls data transmission with the storage medium 130. When the storage medium 130 is, for example, a flash memory chip array, to improve data read and write performance, the media controller 128 can read and write the flash memory chips of the storage medium 130 in parallel via multiple channels (e.g., CH0 and CH2), where each channel connects to a group of flash memory chips.

[0035] Figure 2 It is an example diagram for illustrating the relationship between the die, plane, storage block and super block. As shown in the figure, the flash memory chip 230 (corresponding to Figure 1The storage medium 130) includes 4 dies, which are marked as die 0 to die 3 in the figure. Each die is divided into four planes, which are marked as p0 to p3 in the figure. Each plane is divided into 10 storage blocks, which are marked as b0 to b9 in the figure. Therefore, each die in the figure is divided into 40 storage blocks. The size of a storage block is generally 4096 bytes. The figure shows the connection channels channel0 and channel1 between the controller 220 and the flash memory chip 230. The dies die0 and die1 share channel channel0, so the planes p0 to p3 of the dies die0 and die1 respectively share channel channel0, and the dies die2 and die3 share channel channel1, so the planes p0 to p3 of the dies die0 and die1 respectively share channel channel1. Relying on channels channel0 to channel1, the controller 220 (corresponding to Figure 1 The controller 120) can access each storage block of the flash memory chip 230. Table 1 is Figure 2 Schematic diagram of the corresponding storage block.

[0036] Table 1

[0037]

[0038] In Table 1, a memory block is identified by the coding of channel, die, plane and memory block, for example<channel0,die0,p0,b0> It indicates the memory block with the pattern on the diagram.

[0039] It should be understood that although Figure 2 The flash memory chip 230 is shown to include four dies and each die is divided into four planes, but this is only an example. Based on design and operation considerations, the number of dies in the flash memory chip 230 can be any appropriate number, and the number of planes in each die can also be the same. Figure 2 The number of planes shown is different, and the set or predetermined number of memory blocks in each plane may also be different.

[0040] Instead of dividing memory blocks according to physical locations, the controller 220 may group the memory blocks divided by rows and manage the memory blocks in the same group as a super block.

[0041] refer to Figure 2As shown in Table 1, the 16 memory blocks indicated by the rows are divided into the same super block. The figure shows an exemplary super block A1. Super block A1 includes 16 memory blocks, which are<channel0,die0,p0,b0> 、<channel0,die0,p1,b0> 、<channel0,die0,p2,b0> 、<channel0,die0,p3,b0> 、<channel0,die1,p0,b0> 、<channel0,die1,p1,b0> 、<channel0,die1,p2,b0> 、<channel0,die1,p3,b0> 、<channel1,die2,p0,b0> 、<channel1,die2,p1,b0> 、<channel1,die2,p2,b0> 、<channel1,die2,p3,b0> 、<channel1,die3,p0,b0> 、<channel1,die3,p1,b0> 、<channel1,die3,p2,b0> and<channel1,die3,p3,b0> The identified storage block.

[0042] based on Figure 2 When controller 220 writes data to flash memory chip 230, it writes row-by-row within each die, plane, block, and page. For example, for Super Block A1, all 16 blocks must be written before the Super Block is stable.

[0043] In addition, in order to improve performance, when writing data to the above super block, it can be processed in parallel, such as using channels channel0 and chanel1 for parallel transmission and parallel writing.<channel0,die0,p0,b0> and<channel1,die2,p0,b0> The data of the indicated storage block. The more channels, the more conducive to parallel processing. However, the number of channels does not increase with the increase in the number of dies. Generally, the number of channels is only 2, 4 or 8, which is less than the number of dies. Multiple dies need to share channels. Therefore, the parallel performance of multiple dies does not increase linearly with the increase in the number of dies. Moreover, as the capacity of flash memory chips becomes larger and larger, a flash memory chip (for example, NAND Flash contains 32 or even more dies), when the parallel processing of multiple dies can no longer improve the performance, the super block cannot gain performance benefits by adding dies. As the super block increases, the unfavorable factors become more obvious. For example, the garbage collection and write operation time of a super block will be particularly long, and the super block will take a long time to complete the write operation of all the storage blocks in it and then close the super block, causing the super block to be in an unstable state for a long time.

[0044] Based on this, the embodiment of the present invention proposes how to reduce the size of the super block without affecting performance. The following calculation method can be used for performance calculation.

[0045] Assume that the transmission time per plane is ts, and each die has m planes. After the entire die completes data transmission, the time it takes for the die to write the transmitted data to the storage medium (e.g., flash memory) is tprog. The page size within each plane is represented by PAGE_SIZE (e.g., 16KB). Assume that the number of channels in the entire flash memory chip is n, and the number of die connected to each channel is u. Assume that the preset performance is V MB / s.

[0046] Figure 3 and Figure 4 The following diagram describes the timing diagram of write operation in two different situations. Figure 3 and 4 In this example, u dies share a channel, and each channel shares a set of transmission signal lines. Therefore, when one of the u dies is transmitting data, the other dies cannot. Therefore, ensuring that the channel is always operational—that is, that the signal lines are constantly transmitting data signals—maximum performance is achieved. The diagram divides the write operation for each die into a data transfer phase and a programming phase, labeled ts*m and tprog, respectively.

[0047] like Figure 3As shown, during the ts*m phase of die0, die0 transmits data, then enters the tprog phase of die0 and the ts*m phase of die1. Then, it enters the tprog phase of die1 and the ts*m phase of die2. By the time die2's ts*m phase ends, die0 has completed the tprog phase. In this example, a channel with three die per channel ensures that the channel remains operational. In other words, in this example, the performance is maximized when a channel with three die per channel is used.

[0048] like Figure 4 As shown in the figure, when die(u-1) completes the ts*m stage, die0 has not yet completed the tprog stage. It needs to wait for die0 to complete the tprog stage before entering the ts*m stage. Therefore, in this example, the performance does not reach the maximum when one channel corresponds to u dies. Figure 3 For example, the way to optimize the super block is to reduce the number of tube cores corresponding to a super block to 3 tube cores, which can achieve the purpose of reducing the size of the super block without affecting the speed. Figure 4 For example, if you want to increase the size of the superblock.

[0049] The size of the super block can be estimated using the following formula.

[0050] Assume that the total transmission data of T dies is: T*m*PAGE_SIZE, where m is the number of planes contained in each die, and PAGE_SIZE is the amount of data transmitted on each plane. Because after a single channel transmits the data of T dies, die0 needs to complete the tprog time before it can be transmitted again. Therefore, the total time for a single channel to use T dies for write operations is the total time it takes to complete die0: ts*m+trog. Then, the maximum performance of the die combination under a single channel can be obtained: (T*m*PAGE_SIZE) / (ts*m+trog), and this performance unit is converted into M / S. Assuming that the performance requirement of T dies is VM / S, the preset performance requirement of each channel is V / n. As long as the following inequality (1) holds, then T is the number of dies that does not affect performance:

[0051] V / n<=(T * m * PAGE_SIZE) / ( ts * m + tprog) Formula (1)

[0052] In some embodiments, the sum of the transmission time for a single die to transmit data and the write time for the data from the single die to a storage block is multiplied by the preset performance of a single channel, and the resulting product is divided by the total amount of data transmitted by the single die to obtain the target number of dies. The target number of dies is then rounded up to obtain the minimum number of dies T. See formula (2).

[0053] T>=V / n*(ts*m+tprog) / (m*PAGE_SIZE) formula (2)

[0054] T can only be an integer. The optimal solution for T is a positive integer that is larger than V / n*(ts*m+tprog) / (T*m*PAGE_SIZE) and closest to V / n*(ts*m+tprog) / (T*m*PAGE_SIZE). In the above formula, you can determine the values ​​of tprog and ts through experimentation or by referring to the specifications in the manufacturer's user manual.

[0055] Figure 5 It is used to illustrate the embodiment of the present invention. Figure 2 As shown in the figure, assuming that according to the above formula, the size of the super block is calculated to be greater than or equal to 1 tube core, the performance meets the preset performance requirements, and 1 is equal to half of the number of tube cores connected by a single channel 2, then the reference Figure 5 In one embodiment, the memory blocks corresponding to die0 and die2 are grouped into a super block (i.e., A3 in the figure) by row, and the memory blocks corresponding to die1 and die3 are grouped into a super block (not shown in the figure) by row. In another embodiment, the memory blocks corresponding to die0 and die3 are grouped into a super block (not shown in the figure) by row, and the memory blocks corresponding to die1 and die2 are grouped into a super block (not shown in the figure) by row. It should be understood that in the above embodiment, super blocks in the same row of the same die must be allocated to the same super block.

[0056] An embodiment of the present invention also provides a method for operating a memory, wherein the memory includes a storage medium and a controller, wherein the storage medium is composed of multiple dies, each of which is divided into multiple planes, each of which is divided into multiple storage blocks, and the controller connects the multiple dies through one or more channels. The method for operating the memory is executed by the controller and includes grouping the multiple storage blocks to form a super block and performing various operations on the storage medium based on the super block. The various operations referred to here include but are not limited to read operations, write operations, and garbage collection. In this method, if Figure 6 As shown, the operation of grouping multiple storage blocks to form a super block includes the following steps:

[0057] In step S601 , the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the channel is calculated.

[0058] In step S602, it is determined whether the minimum number of dies is less than or equal to half of the number of dies connected to the same channel. If so, step S603 is executed; otherwise, step S604 is executed.

[0059] In step S603 , the memory blocks are grouped based on the minimum number of dies to form a super block.

[0060] In step S604 , the memory blocks are grouped according to the number of dies in each channel to form a super block.

[0061] For step S601, the preset performance achieved by each channel can be calculated by V / n, where V is a preset performance index of the memory. The preset performance index V can be determined according to the protocol, for example, the preset performance index is determined to be 560MB / s based on the SATA protocol, or it can be determined according to a received user performance instruction. n is the number of channels of the multiple dies used to connect the controller and the storage medium. Then, the maximum performance of the die combination of T dies under a single channel is calculated, that is, the data volume of all storage blocks under the T dies is divided by the sum of the time required to transmit the data volume and the write time of a single storage block. Then, an inequality is set: V / n <= the maximum performance of the die combination of T dies under a single channel. By solving the inequality, the minimum value T that satisfies the inequality is obtained. Continuing with formula (1), in some embodiments, the inequality is: V / n <= (T*m*PAGE_SIZE) / (ts*m+tprog), and the minimum positive integer T that satisfies the inequality is obtained by solving. The minimum value T is the minimum number of dies required to ensure that the maximum performance of the die combination in a single channel is greater than or equal to the preset performance. It should be understood that the maximum performance here corresponds to the performance value when the channel is always busy.

[0062] For steps S603 to S604, refer to Figure 3 and Figure 4 , Figure 3 The example shows that the minimum number of dies required to meet the performance of the die combination under a single channel is 3 when it is greater than or equal to the preset performance, and 3 is less than u / 2. Then the storage blocks under u dies can be grouped according to 3 to form a super block. Figure 4 The example shows that when the performance of the die combination under a single channel meets the requirement of being greater than or equal to the preset performance, the minimum number of dies required to be included is greater than u, so all storage blocks in the same row of u dies are grouped into the same group.

[0063] It should be understood that in step S603, the grouping of storage blocks based on the minimum number of die to form a super block can be performed by selecting the same number of die in parallel from the die connected to each channel based on the minimum number of die to form a super block. Specifically, X die are selected in one channel (T≤X≤u / 2), and the same number of die are selected in another channel, that is, X die, that is, the same number of die are selected in parallel from each channel to form a super block in a parallel relationship. Similarly, another Y die can be selected in one channel (T≤Y≤u / 2, and X+Y≤u), and another Y die can be selected in another channel to form another super block. Using the above-mentioned super blocks for parallel write operations can shorten the time required for super block stabilization without affecting the preset performance requirements, making the flash memory more stable and achieving a balance between performance and stability. It should be understood that this does not necessarily mean that the number of die contained in each super block is equal to the minimum number of die; and the fact that a super block contains the same number of die in each channel does not necessarily mean that the number of die contained in each super block is the same. In other words, X and Y are not necessarily equal. X may be equal to Y or not, and this is not limited here.

[0064] In some embodiments, if the number of dies connected to the same channel is an integer multiple of the minimum number of dies, the number of memory blocks in the same row contained in multiple dies with the minimum number of dies can be evenly divided. For example, if there are M channels and each channel has N dies, and N is a multiple of T, then T dies are selected from the N dies in each channel of the M channels to form a super block (for example, Figure 5 ). However, if in this example, N is not a multiple of T, then you can do this: repeatedly select T die from the N die in each channel of the M channels to form a super block until the remaining die in each channel is less than T, at which point the remaining die in each channel are added to any of the already formed super blocks. For example, if the number of channels is 4, there are 10 die in each channel, and the calculated T is 3, then the die are first allocated according to 3, and 3 die are selected from each channel to form a super block, thus forming 3 super blocks, and then the remaining 1 die in each channel is arbitrarily added to any of the 3 super blocks. It should be understood that although the sizes of super blocks can be different, forming super blocks in a manner that is of the same size is more conducive to the controller's operation.

[0065] According to this embodiment, a smaller superblock is constructed without sacrificing performance, thereby reducing, for example, the unit time for garbage collection and the recovery time for system startup, saving the flash memory capacity occupied by the system, and improving the stability of the flash memory chip. This disclosed embodiment is particularly suitable for large-capacity flash memory chips, that is, flash memory chips containing a large number of dies.

[0066] It should be understood that in this embodiment and the above embodiments, it is mentioned that the inequality: V / n<=(T*m*PAGE_SIZE) / (ts*m+tprog) can be used to compare performance, but this embodiment is not limited to this. Other algorithms can be used to obtain the preset performance of each channel and the maximum performance of the die combination under a single channel, so as to estimate the minimum number of dies required to be included when the preset performance is greater than or equal to the preset performance. For example, data can be obtained by conducting experiments on solid-state drives and calculations can be performed to obtain the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance.

[0067] In addition, an embodiment of the present disclosure further provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above embodiment are implemented.

[0068] Furthermore, an embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above embodiments are implemented.

[0069] The embodiments of the present disclosure are described above. These embodiments do not describe all details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present disclosure, so that those skilled in the art can make good use of the embodiments of the present disclosure and the modifications based on the embodiments of the present disclosure. The embodiments of the present disclosure are limited only by the claims and their full scope and equivalents.

Claims

1. A method for grouping memory blocks in a memory, the memory comprising a storage medium and a controller, the storage medium comprising a plurality of dies, each die being divided into a plurality of planes, each plane being divided into a plurality of memory blocks, the controller interconnecting the plurality of dies via a plurality of channels, the method being executed by the controller and comprising grouping the plurality of memory blocks to form a super block, the grouping comprising: Based on the memory, calculating the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the single channel; as well as It is determined whether the minimum number of dies is less than or equal to half of the number of dies connected to a single channel of the memory; if so, the plurality of memory blocks are grouped based on the minimum number of dies.

2. The method according to claim 1, further comprising: If the minimum number of dies is greater than half of the number of dies connected to a single channel, the memory blocks are grouped according to the number of dies in each channel to form a super block.

3. The method according to claim 1, wherein The preset performance of each channel is equal to the preset performance index of the memory divided by the number of the multiple channels.

4. The method according to claim 1, wherein calculating the minimum number of dies required to ensure that the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the single channel comprises: Multiplying the sum of the transmission time of data transmitted by a single die and the writing time of the data from the single die to the storage block by the preset performance of the single channel, and dividing the obtained product by the total transmission data volume of the single die to obtain the target number of dies; The target number of dies is rounded up to obtain the minimum number of dies.

5. The method according to claim 1, wherein The controller performs a write operation, a read operation, or garbage collection on the storage medium based on the super block.

6. The method according to claim 1, wherein The same number of dies is selected in parallel from the dies connected to each channel according to the minimum number of dies to form a super block.

7. The method according to claim 6, wherein: The grouping of the memory blocks based on the minimum number of dies includes: if the number of dies connected to a single channel is an integer multiple of the minimum number of dies, evenly dividing the memory blocks in the same row contained in multiple dies of the minimum number of dies.

8. The method according to claim 6, wherein: The grouping of storage blocks based on the minimum number of dies includes: if the number of dies connected to the same channel is not an integer multiple of the minimum number of dies, first dividing the storage blocks in the same row contained in multiple dies with the minimum number of dies equally, and then adding the remaining storage blocks to any group.

9. A memory controller, the memory comprising a storage medium and the controller, the storage medium consisting of a plurality of dies, each die being divided into a plurality of planes, each plane being divided into a plurality of storage blocks, the controller connecting the plurality of dies via a plurality of channels, the controller executing the method according to any one of claims 1 to 8 to group the storage blocks to form a super block.

10. A memory comprising the controller according to claim 9 and a storage medium.

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