Semiconductor package

Abstract

A semiconductor package includes a first die and a second die that transmit and / or receive signals to each other. The semiconductor package includes: a package substrate; at least one first die on and connected to the package substrate, with an interposer between the at least one first die and the package substrate; and at least one second die on and connected to the package substrate. Each of the first die and the second die includes a transmitter and a receiver each including a data channel, and a number of data channels of the transmitter and / or receiver of the first die is different from a number of data channels of the transmitter and / or receiver of the second die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2023-0094522 filed on Jul. 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments of the present disclosure described herein relate to semiconductor packages, and more particularly, to semiconductor packages including a plurality of dies. Background Art

[0004] Recently, various types of chiplets are being developed to improve the performance of semiconductor devices and to manufacture semiconductor devices with a high yield in the semiconductor manufacturing industry.

[0005] Small chips including multiple dies communicate with each other through die-to-die interconnects. The die-to-die interconnects between the dies are implemented through bumps. However, die-to-die communication is limited according to the pitch of the bumps, and therefore, it is difficult to configure the small chips. Summary of the invention

[0006] Example embodiments of the present disclosure provide a semiconductor package capable of allowing dies having different types of interconnects to communicate with each other.

[0007] According to some example embodiments, a semiconductor package includes a first die and a second die that transmit and / or receive signals to each other, the semiconductor package including: a package substrate; at least one first die on the package substrate and connected to the package substrate, with an interposer between the at least one first die and the package substrate; and at least one second die on the package substrate and connected to the package substrate. Each of the first die and the second die includes a transmitter and a receiver each including a data channel, and the number of data channels of the transmitter and / or receiver of the first die is different from the number of data channels of the transmitter and / or receiver of the second die.

[0008] The semiconductor package also includes: first bumps connected to data channels corresponding to the transmitter and receiver of the first die; and second bumps connected to data channels corresponding to the transmitter and receiver of the second die.

[0009] The first bumps have a pitch different from a pitch of the second bumps.

[0010] The first bump is between the first die and the interposer, and the second bump is between the second die and the package substrate, and between the package substrate and the interposer. The interposer includes a plurality of vias through which the first bump is connected to the second bump.

[0011] The number of data channels of the second die is less than the number of data channels of the first die.

[0012] The semiconductor package also includes a remapping unit, which is configured to: in response to sending a signal between a data channel of the first tube core and a data channel of the second tube core, remap the signal in an order different from the input order of the signal input to the remapping unit, and output the remapped signals to the corresponding data channels respectively.

[0013] The transmitter and / or receiver of each of the first die and the second die includes: an input data channel configured to receive a signal; a remapping unit configured to remap the signal of the input data channel and provide the signal of the input data channel to an output data channel; and an output data channel configured to receive the remapped signal from the remapping unit and output the remapped signal.

[0014] A remapping unit is provided to each of the transmitter and the receiver of the first die.

[0015] The remapping unit includes: a first remapping unit and a second remapping unit, which are respectively provided to the transmitter and the receiver of the first die; and a third remapping unit and a fourth remapping unit, which are respectively provided to the transmitter and the receiver of the second die.

[0016] The output data lanes of the transmitter of the first die are physically connected to the input data lanes of the receiver of the second die.

[0017] The first remapping unit is configured to select a data channel physically connected to an input data channel of a receiver of the second die among output data channels of a transmitter of the first die and provide a signal.

[0018] The semiconductor package also includes at least one third die on the interposer and / or the package substrate and connected to at least one of the first die and the second die.

[0019] Each of the first die and / or the second die includes at least one of a logic semiconductor device or a memory semiconductor device.

[0020] According to some example embodiments, a semiconductor package includes: a package substrate; a first die on the package substrate and connected to the package substrate through a first interconnect; and a second die on the package substrate and connected to the package substrate through a second interconnect. The first interconnect includes first bumps arranged at a first pitch, the second interconnect includes second bumps arranged at a second pitch different from the first pitch, and at least one of the first die and the second die includes a remapping unit configured to assign signals arranged in a first order to the first bumps of the first interconnect and / or the second bumps of the second interconnect in a second order different from the first order.

[0021] Each of the first die and the second die includes a transmitter and a receiver each including a data lane, and the number of data lanes of the transmitter and / or receiver of the first die is different from the number of data lanes of the transmitter and / or receiver of the second die.

[0022] The transmitter and / or receiver of each of the first die and the second die includes: an input data channel configured to receive a signal; a remapping unit configured to remap the signal of the input data channel and provide the signal of the input data channel to an output data channel; and an output data channel configured to receive the remapped signal from the remapping unit and output the remapped signal.

[0023] Based on the fact that the number of data channels of the transmitter and the receiver of the first die is n and the number of data channels of the transmitter and the receiver of the second die is m which is less than n (n>m), the remapping unit is configured to: select m data channels of the first die corresponding to the situation where the first bump is physically connected to the second bump from among the n data channels of the first die, and provide signals.

[0024] The remapping unit includes: a first remapping unit and a second remapping unit, which are respectively provided to the transmitter and the receiver of the first die; and a third remapping unit and a fourth remapping unit, which are respectively provided to the transmitter and the receiver of the second die.

[0025] According to some example embodiments, a method of sending a signal from a first die to a second die includes: allowing input data channels to be set in a first order corresponding to a signal to be sent in a transmitter of the first die; allowing a first remapping unit to select an output data channel in a second order; outputting the signal to a receiver of the second die through the selected output data channel; allowing the receiver of the second die to receive the signal output from the first die through the input data channel in a third order; and allowing the second remapping unit to select the output data channel in the first order and output the signal.

[0026] According to some example embodiments, there is provided a semiconductor package capable of achieving die-to-die communication between dies having different types from each other.

[0027] According to some example embodiments, the semiconductor package may enable die-to-die communication between a 2.5D type die and a 2D type die. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects and features of the present disclosure will become apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0029] Figure 1A is a plan view illustrating a semiconductor package according to some example embodiments of the present disclosure.

[0030] Figure 1B is along Figure 1A A cross-sectional view taken along line AA′.

[0031] Figure 2A and Figure 2B 1 and 2 are plan views schematically showing the first bump and the second bump, respectively.

[0032] Figure 3 is a diagram schematically illustrating signal transmission between a first die and a second die in a semiconductor package according to some example embodiments of the present disclosure.

[0033] Figure 4A and Figure 4B is a diagram schematically illustrating an interface between a first die and a second die having a data channel.

[0034] Figure 5A and Figure 5B is a diagram showing the physical connection relationship between the first bump and the second bump, Figure 5A It shows the possible physical connection relationship, and Figure 5B Shows physically impossible connection relationships.

[0035] Fig. 6A and Figure 6B is a diagram schematically illustrating a signal transmission process from a first die to a second die in a semiconductor package according to some example embodiments of the present disclosure.

[0036] Fig. 7A and Figure 7B is a diagram schematically illustrating a signal transmission process from a first die to a second die in a semiconductor package according to some example embodiments of the present disclosure.

[0037] Fig. 8A and Figure 8Bis a diagram schematically illustrating a signal transmission process from a first die to a second die in a semiconductor package according to some example embodiments of the present disclosure.

[0038] Fig.9A is a diagram showing a semiconductor package in which six dies are disposed on a package substrate according to some example embodiments of the present disclosure.

[0039] Fig. 9B is along Fig.9A A cross-sectional view taken along line BB′.

[0040] Fig. 10A and Fig. 10B is a diagram showing a semiconductor package according to some example embodiments of the present disclosure, and some dies on an interposer are three-dimensionally stacked 3D devices.

[0041] Fig.11 is a cross-sectional view illustrating an electronic system employing a semiconductor package according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] The present disclosure may be variously modified and implemented in a variety of different forms, and therefore, specific example embodiments will be shown in the drawings and described in detail below. However, the present disclosure should not be limited to the specific disclosed form, and should be interpreted as including all modifications, equivalents or replacements included in the spirit and scope of the present disclosure.

[0043] According to some example embodiments of the present disclosure, a chiplet-type semiconductor package includes at least two dies, and at least two dies and an interposer are arranged on a package substrate. According to some example embodiments of the present disclosure, one of the at least two dies is arranged on an interposer, and another of the two or more dies is arranged on a package substrate. That is, the semiconductor package according to some example embodiments of the present disclosure corresponds to a hybrid semiconductor package, which is a mixture of a two-dimensional (2D) semiconductor package in which dies of various functions are arranged on a package substrate and a two-dimensional and a half (2.5D) semiconductor package in which dies of various functions are arranged by using an interposer. According to some example embodiments of the present disclosure, the semiconductor package includes a remapping unit that selects and remaps a data channel between two dies arranged on different substrates (package substrate and interposer), so that signal transmission between a die arranged on an interposer and a die arranged on a package substrate can be achieved. For example, according to some example embodiments, the speed, accuracy and / or power efficiency of chip-to-chip communication and device operation can be increased based on the above method. Thus, the improved devices and methods overcome the deficiencies of conventional devices and methods for chiplet-type semiconductor packages associated with including different types of semiconductor packages while reducing resource consumption and increasing data clarity. In addition, as discussed herein, by providing the ability for different types of semiconductor packages to communicate on a chiplet-type semiconductor package, there are size and / or compactness improvements.

[0044] Hereinafter, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0045] Figure 1A is a plan view showing a semiconductor package according to some example embodiments of the present disclosure, and Figure 1B is along Figure 1A A cross-sectional view taken along line AA'.

[0046] Reference Figure 1A and Figure 1B , a semiconductor package may include: a package substrate 100; an interposer 400 disposed above the package substrate 100; at least one first die 200 disposed above the package substrate 100 and connected to the package substrate 100, with the interposer 400 interposed therebetween; and at least one second die 300 disposed above the package substrate 100 and connected to the package substrate 100.

[0047] The package substrate 100 may be a support substrate on which the first die 200, the second die 300, and the interposer 400 are mounted. The package substrate 100 may include at least one layer of wiring therein or may include multiple layers of wiring. In the case where the wiring is provided in multiple layers, the wiring provided on different layers may be connected to each other by vertical contacts. According to some example embodiments, the package substrate 100 may include various wirings, and may further include, for example, a bridge wire BR connecting a second interconnect 520 and a third interconnect 530 described later.

[0048] The package substrate 100 may have various types of redistribution lines formed on one or both surfaces of a core layer, the core layer being formed of, for example, an organic material (such as phenolic resin, epoxy resin, polyimide, etc.) or reinforced fiber glass. However, the material for the core layer of the package substrate 100 should not be limited thereto or thereby. According to some example embodiments, the package substrate 100 may be a substrate of a ceramic material (e.g., a silicon wafer). In some example embodiments, the redistribution lines may include a conductive material (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof), however, the material for the redistribution lines should not be limited thereto or thereby. The redistribution lines may be disposed on the upper and lower surfaces of the core layer, as well as inside the core layer.

[0049] The pads 110 may be provided on the upper surface and / or the lower surface of the package substrate 100 for connection with other components.

[0050] The interposer 400 may convert or transmit a digital signal between the first die 200 and the package substrate 100. The first die 200 may be stacked on the package substrate 100 with the interposer 400 interposed therebetween.

[0051] The interposer 400 may include a silicon substrate or a glass substrate, however, the interposer 400 should not be limited thereto or thereby. As an example, an organic substrate may be used to manufacture the interposer 400. In some example embodiments, a silicon substrate will be described as the interposer 400.

[0052] The interposer 400 may include a plurality of lines and a plurality of vias 401 connecting the upper surface and the lower surface of the interposer 400. The vias 401 may be through silicon vias (TSVs). The interposer 400 may have a back-end-of-line (BEOL) structure, however, the interposer 400 should not be limited thereto or thereby. According to some example embodiments, the interposer 400 may have a front-end-of-line (FEOL) structure. The redistribution lines may be provided on the upper and / or lower surfaces of the interposer 400 in various forms, and the interposer 400 may include not only redistribution lines but also active devices or passive devices.

[0053] The first die 200 and / or the second die 300 may be various integrated circuit (IC) devices. The IC device may include active devices and / or passive devices, and may include various devices, such as logic semiconductor devices, storage semiconductor devices, etc. The logic semiconductor device may perform various signal processing operations, such as analog signal processing operations, analog-to-digital (A / D) conversion operations, control operations, etc. For example, the logic semiconductor device may be an application processor (AP), a microprocessor, a central processing unit (CPU), a controller, a graphics processor unit (GPU), or an application-specific integrated circuit (ASIC). In addition, the storage semiconductor device may be, for example, a volatile memory (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.) or a non-volatile memory (e.g., a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), a resistive random access memory (RRAM)).

[0054] The first die 200, the second die 300, the interposer 400, and the package substrate 100 may be connected to each other through interconnections, and thus may be electrically connected to each other. The interconnections may include pads and bumps.

[0055] Interconnections may be provided between the interposer 400 and the first die 200 , between the package substrate 100 and the interposer 400 , and between the second die 300 and the package substrate 100 .

[0056] When the interconnection between the interposer 400 and the first die 200, the interconnection between the package substrate 100 and the interposer 400, and the interconnection between the second die 300 and the package substrate 100 are respectively referred to as the first interconnection 510, the second interconnection 520, and the third interconnection 530, the first interconnection 510 may include pads 210 and 410a, and a first bump 510bp, which are respectively arranged on the first die 200 and the interposer 400 facing the first die 200, and the first bump 510bp is arranged between the pad 210 of the first die 200 and the pad 410a on the interposer 400, so as to connect the pad 210 of the first die 200 and the pad 410a of the interposer 400. The second interconnect 520 may include pads 410b and 110, which are respectively disposed on the interposer 400 and the package substrate 100 facing the interposer 400, and a second bump 520bp, which is disposed between the pad 410b of the interposer 400 and the pad 110 of the package substrate 100 for connecting the pad 410b of the interposer 400 and the pad 110 of the package substrate 100. According to some example embodiments, the third interconnect 530 may be disposed on the same package substrate 100 as the second interconnect 520. The third interconnect 530 may include pads 310 and 110, and a second bump 520bp, wherein the pads 310 and 110 are respectively arranged on the second tube core 300 and the packaging substrate 100 facing the second tube core 300, and the second bump 520bp is arranged between the pad 310 of the second tube core 300 and the pad 110 of the packaging substrate 100, so as to connect the pad 310 of the second tube core 300 and the pad 110 of the packaging substrate 100.

[0057] The first bump 510bp may transmit a signal between the first die 200 and the interposer 400, and may be connected to a data channel (not shown) of the first die 200 and a data channel (not shown) of the interposer 400. The second bump 520bp may transmit a signal between the interposer 400 and the package substrate 100, and may be connected to a data channel (not shown) of the interposer 400 and a data channel (not shown) of the package substrate 100. In addition, the second bump 520bp may transmit a signal between the second die 300 and the package substrate 100, and may be connected to a data channel (not shown) of the second die 300 and a data channel (not shown) of the package substrate 100.

[0058] In some example embodiments, the first bumps 510bp and the second bumps 520bp may be disposed to correspond to data lanes of components to be connected (ie, the first die 200 , the second die 300 , the package substrate 100 , the interposer 400 , etc.).

[0059] The number of data channels of each of the first die 200, the second die 300, the package substrate 100, and the interposer 400 may vary according to the configuration and specifications of the interface. As an example, in the case of sending signals through the first interconnect, the number of data channels may be 39, and in the case of sending signals through the second interconnect, the number of data channels may be ten (10). However, the number of data channels should not be particularly limited and may vary according to the interface adopted when sending signals.

[0060] In this case, the first bump 510bp and the second bump 520bp may correspond to the data lanes of the components to be connected (e.g., the first die 200, the second die 300, the package substrate 100, and the interposer 400) in a one-to-one correspondence or a one-to-many correspondence. The number of bumps corresponding to and connected to the data lanes should not be particularly limited and may be greater than the number of data lanes.

[0061] According to the present disclosure, each of the first bump 510bp and the second bump 520bp may be a solder bump, however, the first bump 510bp and the second bump 520bp should not be limited thereto or thereby. According to some example embodiments, other types of connection elements may be applied, for example, Cu to Cu direct bonding.

[0062] At least one of the first interconnect 510, the second interconnect 520, and the third interconnect 530 may be different from the remaining interconnects in arrangement of bumps for signal transmission and data channels connected to the bumps. As an example, the first bump 510bp and the second bump 520bp may be arranged at different pitches from each other.

[0063] Figure 2A and Figure 2B are plan views schematically showing the first bump 510 bp and the second bump 520 bp, respectively.

[0064] Reference Figure 2A and Figure 2B , each of the first bump 510bp and the second bump 520bp can be arranged in a two-dimensional matrix form. The arrangement of the first bump 510bp and the second bump 520bp should not be limited to this or thereby limited, and the first bump 510bp and the second bump 520bp can be arranged in other forms other than the two-dimensional matrix form. Hereinafter, the matrix form will be described as a representative example.

[0065] According to some example embodiments, the first bump 510bp may have a size different from that of the second bump 520bp, and may be arranged at a spacing different from that of the second bump 520bp. According to some example embodiments, each second bump 520bp may be larger than each first bump 510bp. In addition, when it is assumed that the first bump 510bp is arranged at the same spacing in the row and column directions and the second bump 520bp is arranged at the same spacing in the row and column directions, the spacing between two adjacent first bumps 510bp is referred to as the first spacing D1, and the spacing between two adjacent second bumps 520bp is referred to as the second spacing D2. In this case, the second spacing D2 may be larger than the first spacing D1.

[0066] According to some example embodiments, the first spacing D1 between the first bumps 510bp may be in the range of about or exactly 10 microns to about or exactly 70 microns (e.g., about or exactly 25 microns to about or exactly 55 microns), and the second spacing D2 between the second bumps 520bp may be in the range of about or exactly 75 microns to about or exactly 200 microns (e.g., about or exactly 100 microns to about or exactly 130 microns). According to some example embodiments, the first bump 510bp and the second bump 520bp may be selected from various types of bumps. As an example, each first bump 510bp may be a microbump including a metal column (e.g., a copper column) and a metal cap (e.g., SnAg), and each second bump 520bp may be a C4 bump. However, the spacing and type of the first bump 510bp and the second bump 520bp should not be limited thereto or thereby limited, and may be changed in various ways.

[0067] As described above, the first bumps 510 bp may be arranged at a pitch different from that of the second bumps 520 bp, and therefore, in the same unit area, the number of the first bumps 510 bp may be greater than the number of the second bumps 520 bp. Figure 2A and Figure 2B As shown, for the same unit area, thirty-six first bumps 510 bp can be arranged, and nine second bumps 520 bp can be arranged.

[0068] As described above, the number of first bumps 510bp and second bumps 520bp may vary according to the design rules of the semiconductor package, however, basically, the number of second bumps 520bp must be less than the number of first bumps 510bp that can be used. Therefore, when sending a signal from a data channel connected to the first bump 510bp through the second bump 520bp, it is important to determine the physical connection between the data channels, that is, which data channels among the data channels of the first interconnect 510 are connected to which data channels among the data channels of the second interconnect 520.

[0069] Figure 3 Schematically illustrates signal transmission between a first die 200 and a second die 300 in a semiconductor package according to some example embodiments of the present disclosure (shown by Figure 1A The part indicated by the double-headed arrow in the figure).

[0070] Reference Figure 3 , the first die 200 and the second die 300 may include an interface for signal transmission therebetween, and each of the first die 200 and the second die 300 may include a data channel, a clock channel, a sideband channel, and various other channels to bidirectionally or unidirectionally transmit various signals (clock signals, sideband signals, etc.) between the transmitter TX and the receiver RX. According to the present disclosure, various types of signals are transmitted through the interface between the first die 200 and the second die 300, and various types of channels are used to transmit various signals. For ease of explanation, various types of signals are collectively referred to as "signals", and various types of channels are collectively referred to as "data channels". Some example embodiments of the present disclosure described below may be applied to various other signals and channels for transmitting various other signals, as long as they do not depart from the concept of the present disclosure.

[0071] According to the present disclosure, a signal from a transmitter TX of the first die 200 may be transmitted to a receiver RX of the second die 300, and a signal from a transmitter TX of the second die 300 may be transmitted to a receiver RX of the first die 200. In this case, a first interconnect 510 and a second interconnect 520 may be provided between the first die 200 and the second die 300, and a signal may be transmitted from the first die 200 to the second die 300, and vice versa, according to physical line connections within the first interconnect 510 and the second interconnect 520.

[0072] In this case, signal transmission between the first die 200 and the second die 300 may be performed through physical line connection. The number of data lanes connected to the first interconnect 510 and the second interconnect 520 may be determined according to the arrangement and number of the first bumps 510bp and the second bumps 520bp of the first interconnect 510 and the second interconnect 520, and the transmitted signal may be limited according to the number of data lanes.

[0073] Figure 4A and Figure 4B is a diagram schematically showing an interface between a first die 200 and a second die 300 having a data channel.

[0074] Reference Figure 4A and Figure 4B, signals may be sent from a transmitter of a first die to a receiver of a second die and from a transmitter of a second die to a receiver of the first die, and each signal may be sent through its corresponding data channel.

[0075] However, as described above, whether the data channels of the first die and the second die can be used may vary due to physical constraints caused by the difference in the pitch and number of the first bumps and the second bumps.

[0076] In more detail, when a signal is sent from the first die 200 to the second chip 300, when the number of first data channels through which the first die 200 sends signals is n and the number of second data channels through which the second die 300 sends signals is m (m<n), since the number of data channels of the receiver RX of the second die 300 is only m, nm (n minus m) data channels among the data channels may not be used (indicated by x).

[0077] When a signal is sent from the second die 300 to the first die 200, since the number of data channels of the receiver RX of the first die 200 is n but the number of data channels of the transmitter of the second die 300 is only m, the number of data channels through which the signal is sent from the transmitter TX of the second die 300 to the receiver RX of the first die 200 is only m, and nm of the data channels may not be used.

[0078] However, when the first interconnect and the second interconnect are connected to each other through the vias of the interposer 400 or through the bridge wires of the package substrate, the first interconnect and the second interconnect can be connected to each other only within physically possible limits, and as a result, in the arrangement of the bumps, the order and / or position of the data channels of the first interconnect may not correspond to the order and / or position of the data channels of the second interconnect. Specifically, since the number of data channels of the first interconnect 510 is different from the number of data channels of the second interconnect 520, the number and position of the data channels of the first interconnect 510 that can be physically connected to the data channels of the second interconnect 520 may be further limited. Here, the expression "physical connection" refers not only to two adjacent elements being directly and physically connected to each other in actual physical shape, but also to two elements being connected to each other while at least one element having a different actual physical shape is interposed between the two elements.

[0079] Figure 5A and Figure 5B is a diagram showing a physical connection relationship between a first bump 510 bp and a second bump 520 bp in a first interconnect 510 and a second interconnect 520 as a representative example. Figure 5A It shows the possible physical connection relationship, and Figure 5BIn this case, each of the first bump 510 bp and the second bump 520 bp is actually connected two-dimensionally, but for ease of explanation, the following description is made on the assumption that they are connected one-dimensionally in the cross section in the drawing.

[0080] Reference Figure 5A , the first interconnect 510 may be connected to the second interconnect 520 through the via 401, and the interposer 400 is interposed between the first interconnect 510 and the second interconnect 520. In this case, the first bump 510bp located first from the right may be connected to the second bump 520bp located first from the right, and the first bump 510bp located second from the right may be connected to the second bump 520bp located second from the right. Therefore, when the first interconnect 510 is connected to the second interconnect 520 through the via 401, the vias 401 may not intersect with each other, and therefore, the first bumps 510bp may be electrically connected to the second bumps 520bp, respectively, without defects.

[0081] Reference Figure 5B , the first interconnect 510 may be connected to the second interconnect 520 through the via 401, and the interposer 400 is interposed between the first interconnect 510 and the second interconnect 520. In this case, the first bump 510bp located first from the right may be connected to the second bump 520bp located second from the right, and the first bump 510bp located second from the right may be connected to the second bump 520bp located first from the right. However, in this case, the vias 401 may intersect with each other, and as a result, the first bumps 510bp may not be electrically connected to the second bumps 520bp, respectively.

[0082] When the first bump 510bp and the second bump 520bp are arranged two-dimensionally, the first interconnect and the second interconnect are connected to each other based on physical arrangement possibility (i.e., the first bump 510bp and the second bump 520bp are connected in a manner not determined by proximity (see, for example, Figure 5B Compared to Figure 5A )), the number of connection situations between the first bump 510bp and the second bump 520bp is more complicated. Therefore, according to the connection relationship of the vias 401 in the interposer 400, the first bump 510bp may match the second bump 520bp located at different positions in the matrix arrangement, but not match the second bump 520bp located at the same position in the matrix arrangement, and according to the number of the first bump 510bp and the number of the second bump 520bp, there may even be mismatched bumps.

[0083] The connection relationship of the bumps between the second interconnect 520 and the third interconnect 530 in the package substrate 100 may also be restricted according to the above-mentioned physical connection relationship. However, since the second interconnect 520 and the third interconnect 530 share the same interface (e.g., the second bump 520bp), the restriction on the number and position of the second bump 520bp when connecting the second interconnect 520 and the third interconnect 530 may be less than the restriction on the number and position of the first bump and the second bump when connecting the first interconnect 510 and the second interconnect 520, or the restriction may not exist.

[0084] The semiconductor package disclosed herein may include a remapping unit that selects a data channel by considering the limitation of physical connection caused by the difference in the number of bumps connected to the data channel when performing signal transmission between two dies, and remaps the output signal to the selected data channel, and thus, the above-mentioned defects and considerations caused by the limitation of physical connection can be solved or improved. For example, according to some example embodiments, the speed, accuracy and / or power efficiency of chip-to-chip communication and device operation can be increased based on the above-mentioned method. Therefore, the improved device and method overcome the defects of conventional devices and methods of chiplet-type semiconductor packages associated with including different types of semiconductor packages, while reducing resource consumption and increasing data clarity. In addition, as discussed herein, by providing the ability for different types of semiconductor packages to communicate on a chiplet-type semiconductor package, there are size and / or compactness improvements.

[0085] In detail, in a case where the number of data channels of the transmitter and / or receiver of the first die 200 is different from the number of data channels of the transmitter and / or receiver of the second die 300, the remapping unit may allow a signal input to an initial transmitter that sends / receives signals to / from the first bump 510bp and the second bump 520bp to be output to the receiver as is.

[0086] Fig. 6A and Figure 6B Schematically illustrates a signal transmission process from a first die 200 to a second die 300 or from a second die 300 to a first die 200 in a semiconductor package according to some example embodiments of the present disclosure, and shows a sequential arrangement of data channels. Fig. 6A shows the arrangement of data channels when a signal is sent from the first die 200 to the second die 300, and Figure 6B The arrangement of data channels when a signal is transmitted from the second die 300 to the first die 200 is shown.

[0087] Reference Fig. 6A and Figure 6B, the first die 200 and the second die 300 may respectively include a transmitter TX and a receiver RX for signal transmission.

[0088] The transmitter TX of the first die 200 may include an input data channel DLi that inputs a signal to be transmitted, an output data channel DLo that outputs a signal to be transmitted, and a first remapping unit 610 that remaps the signal from the input data channel DLi and provides the remapped signal to the output data channel DLo selected based on a predetermined (or alternatively, desired or selected) standard. The first remapping unit 610 may select the output data channel DLo in an order different from the order of the signal input to the input data channel DLi and match the output data channel DLo with the input data channel DLi. In the case where the order of the input data channels DLi inputted with the signal and the order of the signal corresponding to the input data channels DLi are referred to as the first order, the order of the selected output data channels DLo and the order of the signal corresponding to the selected output data channels DLo are referred to as the second order different from the first order. In this case, the second order of the output data channels DLo may be determined according to the physical connection relationship between the first interconnect and the second interconnect (e.g., between the first bump and the second bump), and the second order of the output data channels DLo may be different from the first order.

[0089] For example, according to some example embodiments of the present disclosure, in the case where the first die 200 includes n data channels, the number of data channels used for transmitting signals may be set to m which is less than n. This is because the number of data channels of the receiver RX of the second die 300 is less than the number of data channels of the transmitter TX of the first die 200, and therefore, the number of data channels used may be equal to or less than the number of data channels of the second die 300. That is, the number of data channels of the input signal in the first die 200 may be equal to or less than the number of second bumps.

[0090] In some example embodiments, where data channels sequentially arranged from bottom to top are respectively referred to as a first data channel, a second data channel, a third data channel, a fourth data channel, ..., an (m-2)th data channel, an (m-1)th data channel, an m-th data channel, ..., an (n-1)th data channel, and an n-th data channel, the first remapping unit 610 may select only some data channels (the first data channel, the second data channel, the third data channel, the fourth data channel, ..., the (m-2)th data channel, the (m-1)th data channel, the m-th data channel, ..., the (n-1)th data channel, and the n-th data channel) among the data channels (the first data channel, the second data channel, the third data channel, the fourth data channel, ..., the (m-2)th data channel, the (m-1)th data channel, and the m-th data channel) to send signals to the second die 300, and may output signals corresponding to the selected data channels to the corresponding data channels.

[0091] In this case, the first remapping unit 610 may select a data channel from data channels available for physical connection by considering the physical connection relationship between the first bump and the second bump. Among the data channels, a data channel that cannot connect the first bump and the second bump may not be selected. Fig. 6A and Figure 6B In the example, a data channel selected from data channels available for physical connection is displayed as a halftone dot pattern.

[0092] Therefore, the input data channels DLi to which the signals are initially assigned and the output data channels DLo selected and remapped by the first remapping unit 610 may be arranged in different orders. As an example, in the case where the first to nth data channels of the input data channels DLi are assigned i_tx_d(1) to i_tx_d(n), the first to mth data channels i_tx_d(1) to i_tx_d(m) may be selected and remapped by the first remapping unit 610. Therefore, as shown in the figure, the output data channels DLo may be arranged in an order different from that of the input data channels DLi. The selected data channels may output the signals to the second die 300 through the physical connection between the first interconnect and the second interconnect.

[0093] The receiver RX of the second die 300 may include an input data channel DLi for inputting a signal to be received, an output data channel DLo for outputting a received signal, and a second remapping unit 620, which remaps the signal of the input data channel DLi and provides the remapped signal to an output data channel DLo selected based on a predetermined (or alternatively, desired or selected) standard.

[0094] The second remapping unit 620 may select the output data channel DLo and match the output data channel DLo with the input data channel DLi in an order different from the order of the signals input to the input data channel DLi. The second remapping unit 620 may operate in a manner substantially the same as or the same as the first remapping unit 610. In the case where the order of the input data channels DLi to which the signals are input or the order of the signals corresponding to the input data channels DLi is referred to as a third order, the third order may be determined based on the physical connection relationship between the first bump and the second bump, and the third order may be different from the second order. Then, the second remapping unit 620 may set the order of the selected output data channels DLo and the order of the signals corresponding to the selected output data channels DLo to a first order different from the third order.

[0095] Similarly, refer to Figure 6B , each of the second die 300 and the first die 200 may include a transmitter TX and a receiver RX for signal transmission.

[0096] You can refer to the above Fig. 6A Signal transmission from the second die 300 to the first die 200 is performed in substantially the same or identical manner as described.

[0097] The transmitter TX of the second die 300 may include an input data channel DLi that inputs a signal to be transmitted, an output data channel DLo that outputs a signal to be transmitted, and a third remapping unit 630 that remaps the signal of the input data channel DLi and provides the remapped signal to the output data channel DLo selected based on a predetermined (or alternatively, desired or selected) standard. The third remapping unit 630 may select the output data channel DLo in an order different from the order of the signals input to the input data channel DLi and match the output data channel DLo with the input data channel DLi.

[0098] In this case, the order of outputting the data channels DLo may be determined according to the physical connection relationship between the first interconnection and the second interconnection (eg, between the first bump and the second bump).

[0099] The receiver RX of the first die 200 may include an input data channel DLi to which a signal to be received is input, an output data channel DLo to which a received signal is output, and a fourth remapping unit 640 that remaps the signal of the input data channel DLi and provides the remapped signal to the output data channel DLo selected based on a predetermined (or alternatively, desired or selected) standard. The fourth remapping unit 640 may output the signal input to the input data channel DLi in an order that matches the order of the initially transmitted signal.

[0100] According to the present disclosure, the input data channel DLi of the transmitter TX may exist as a physical component, however, the present disclosure should not be limited thereto or thereby. That is, the input data channel DLi of the transmitter TX may not exist as a physical component. The output data channel DLo of the receiver RX may exist as a physical component or may not exist as a physical component. On the contrary, the output data channel DLo of the transmitter TX and the input data channel DLi of the receiver RX may exist as physical components and may be physically connected to each other. Therefore, the signal output to the first bump connected to the selected data channel can be sent to the second bump physically connected to the first bump through the via of the interposer and / or the bridge wire of the package substrate. Since the connecting wire between the first bump and the second bump (e.g., the via of the interposer and / or the bridge wire of the package substrate) is physically connected to other components, the connection relationship of the connecting wire may not change, and the connection relationship may be substantially fixed or completely fixed (unchangeable).

[0101] As described above, in the case where the initially input transmission signal is output to the second die 300 as it is without remapping the transmission signal, although the connection relationship between the transmitter TX of the first die 200 and the receiver RX of the second die 300 through the first bump and the second bump is determined by the physical connection PC between the first bump and the second bump, the signal assigned to the data channel that is not physically connected cannot be transmitted. In addition, although the signal is assigned to the physically connected data channel, the signal may be applied to other channels instead of the channel corresponding to the signal.

[0102] According to the present disclosure, the second remapping unit 620 can select and remap the unmatched data channel considering the physical connection between the first bump and the second bump, and can output the signal of the final determined data channel. In this way, the initially input signal can be sent from the first die 200 to the second die 300 through the remapping of the signal by the first remapping unit 610 and the second remapping unit 620.

[0103] According to some example embodiments, in a case where the second die 300 includes m data channels and the data channels sequentially arranged from bottom to top are respectively referred to as a first data channel, a second data channel, a third data channel, a fourth data channel, ..., an (m-2)th data channel, an (m-1)th data channel, and an mth data channel, the third remapping unit may select a data channel that can achieve physical connection among the data channels (e.g., the first data channel, the second data channel, the third data channel, the fourth data channel, ..., the (m-2)th data channel, the (m-1)th data channel, and the mth data channel) considering the physical connection relationship between the second bump and the first bump to send a signal to the first die 200, and may remap the signal applied to the selected data channel.

[0104] Therefore, based on the order in which the same signal is applied, the data channels initially assigned and input with signals and the data channels selected by the third remapping unit are arranged in different orders from each other. The selected data channels can be connected to different second bumps from each other, and the signals can be output to the first die 200 through the different second bumps from each other.

[0105] The sequentially changed signal may be output through the corresponding second bump, and may be sent to the first bump physically connected to the second bump through the via 401 of the interposer 400 and / or the bridge wire of the package substrate 100. Since the connection line between the second bump and the first bump (e.g., the via 401 of the interposer 400 and / or the bridge wire of the package substrate 100) is physically connected, the connection relationship of the line may not change, and may be substantially fixed or completely fixed (unchangeable).

[0106] Since the connection relationship of the first bump of the receiver RX of the first die 200 is determined by the physical connection between the first bump and the second bump, only some data channels selected from the data channels of the receiver RX of the first die 200 may correspond to the data channels of the transmitted signals. Therefore, the order of the signals transmitted through the selected data channels or the corresponding data channels may not match the order of the transmission signals initially input or the corresponding data channels. The fourth remapping unit may select and remap the unmatched data channels in consideration of the physical connection between the second bump and the first bump, and may output the signals of the finally determined data channels.

[0107] As described above, since the connection relationship between the transmitter TX of the second die 300 and the receiver RX of the first die 200 through the second bump and the first bump is determined by the physical connection between the first bump and the second bump, the third remapping unit and the fourth remapping unit according to the present disclosure can select and remap the unmatched data channel in consideration of the physical connection between the first bump and the second bump, and can output the signal of the finally determined data channel. In this way, the initially input signal can be sent from the second die 300 to the first die 200 in the same order.

[0108] According to conventional semiconductor packaging, the interface for signal transmission between two dies is limited to a structure in which the two dies include the same number of data channels and bumps connected to the data channels. This is because when the types of bumps of the two dies are different from each other (for example, when the pitch of bumps adjacent to each other or the number of bumps is different from each other), physical connection is difficult.

[0109] According to the semiconductor package of the present invention, under the limitation of the current physical connection (i.e., without changing the physical connection relationship), the signals are remapped and assigned to the bumps respectively by considering the physical connection relationship through logical operations, and thus, signals can be sent between two tube cores with different types of bumps.

[0110] In some example embodiments, the first die 200 and the second die 300 provided with the interposer 400 interposed therebetween are described as representative examples, however, the present disclosure may be applied to any case where it is difficult to arrange a data channel to be used due to physical differences between interconnected bumps or due to limitations on the physical connection relationship of the wires connecting the dies. Specifically, according to the semiconductor package of the present disclosure, a signal may be transmitted between a 2.5D type die and a 2D type die.

[0111] Specifically, according to the present disclosure, a high-cost device having a difficult and complicated manufacturing process and a low-cost device having a simple manufacturing process can be placed separately from each other on an interposer or a package substrate, and thus, the manufacturing cost of a semiconductor package can be reduced.

[0112] According to some example embodiments of the present disclosure, the number of data channels selected from the transmitter TX or the receiver RX in the first die 200 or the second die 300 may be greater than the number of data channels of the above-described embodiments. This is because in addition to signal transmission using the transmitter TX and the receiver RX, the data channels may also transmit various signals, and additional data channels may be provided for transmission of various signals. Therefore, the number of data channels of the transmitter TX and the receiver RX after the remapping process may be greater than the number of data channels of the transmitter TX and the receiver RX before the remapping process. In this case, the first remapping unit 610 and the second remapping unit 620 may select valid data channels from among the larger number of data channels.

[0113] Fig. 7A and Figure 7B is a diagram schematically illustrating a signal transmission process from a first die 200 to a second die 300 or from a second die 300 to a first die 200 in a semiconductor package according to some example embodiments of the present disclosure. Fig. 7A shows signal transmission from the first die 200 to the second die 300, and Figure 7B 2 shows the signal transmission from the second die 300 to the first die 200. Fig. 7A and Figure 7B , the number of data channels of the transmitter TX of the first die 200 and the number of data channels of the receiver RX of the second die 300 are different from the reference Fig. 6A and Figure 6B The number of data channels of the transmitter TX of the first die 200 and the number of data channels of the receiver RX of the second die 300 of the semiconductor package are described.

[0114] In the following, we will focus on Fig. 6A and Figure 6B Features of the described semiconductor package are described differently to avoid redundancy.

[0115] Reference Fig. 7A , a signal to be transmitted from the first die 200 to the second die 300 may be selected in the first die 200 and may be allocated to a data channel to be transmitted, and in the transmitter TX of the first die 200, the number of output data channels DLo may be greater than the number of input data channels DLi. As an example, when the number of input data channels DLi required for the signal to be transmitted is n, the number of output data channels DLo of the transmitter TX may be n+a. In this case, as in the above-described embodiment, when the number of data channels required for the signal to be transmitted is set to m in some example embodiments, the remapping unit may select m data channels from n+a data channels, and may output the signal to the first bump.

[0116] The signals output to the first bump (the first signal, the second signal, the third signal, the fourth signal, ..., the (m-2)th signal, the (m-1)th signal and the mth signal) can be sent to the second bump through a physical connection PC (for example, the via 401 of the interposer 400 and / or the bridge wire of the package substrate 100).

[0117] In a case where the number of input data channels required for signals to be received in the receiver RX of the second die 300 is m, the number of input data channels DLi of the receiver RX may be m+b. Fig. 7A The addition of two further data channels is shown (eg, b=2).

[0118] The second remapping unit 620 may select and remap a mismatched data channel by considering a physical connection PC between the first interconnect and the second interconnect, and may output a remapped signal.

[0119] In this manner, an initially input signal may be transmitted from the first die 200 to the second die 300 through remapping of the signal by the first remapping unit 610 and the second remapping unit 620 .

[0120] Reference Figure 7B , the second die 300 may include a second bump connected to the m+b data channels, and a third remapping unit 630 that remaps the signal input to the data channel and outputs the remapped signal. The first die 200 may include a first bump connected to the n+a data channels, and a fourth remapping unit 640 that remaps the received signal to the first bump and outputs the remapped signal.

[0121] A signal transmitted from the second die 300 to the first die 200 may be transmitted through substantially the same or identical path as a signal transmitted from the first die 200 to the second die 300 .

[0122] According to some example embodiments of the present disclosure, in the case where a data channel matching a data channel corresponding to the first bump and a data channel of a signal to be transmitted is obtained in a receiver of the second die through a physical connection relationship between the first bump and the second bump, the second remapping unit or the third remapping unit may be omitted.

[0123] Fig. 8A and Figure 8B is a diagram schematically illustrating a signal transmission process from a first die 200 to a second die 300 or from a second die 300 to a first die 200 in a semiconductor package according to some example embodiments of the present disclosure.

[0124] Reference Fig. 8A, the first die 200 may include a first remapping unit 610 that remaps signals input to n data channels and outputs the remapped signals to the second die 300. The first remapping unit 610 may select m data channels among the n data channels, and may output the remapped signals to the first bump. The first remapping unit 610 may select a data channel among the data channels that can be physically connected by considering the physical connection relationship between the first interconnect and the second interconnect. In the case where the output result obtained by selecting the data channel by the first remapping unit 610 is the same as the signal transmission through the initial data channel in the receiver RX of the second die 300, the second remapping unit may be omitted. Therefore, the signal of the input data channel DLi provided to the receiver RX of the second die 300 may be directly output to the output data channel DLo without remapping.

[0125] Reference Figure 8B , the third remapping unit can be omitted in the case where the same output result as the signal transmission through the initial data channel in the receiver RX of the first die 200 is obtained by considering the physical connection relationship between the second bump and the first bump and the remapping result of the first remapping unit 610 of the first die 200. Therefore, the signal received in the input data channel DLi of the transmitter TX of the second die 300 can be immediately output to the output data channel DLo without remapping.

[0126] In the above embodiments, the semiconductor package includes a first die and a second die, however, the present disclosure should not be limited thereto or thereby, and the semiconductor package may include three or more dies. As an example, the semiconductor package may further include an additional die disposed on the interposer and / or the package substrate and connected to at least one of the first die and the second die by interconnection.

[0127] Fig.9A is a diagram showing a semiconductor package in which six dies are disposed on a package substrate according to some example embodiments of the present disclosure, and Fig. 9B is along Fig.9A A cross-sectional view taken along line BB'.

[0128] Reference Fig.9A and Fig. 9B , the semiconductor package may include a package substrate 100 , an interposer 400 , and a first die 200 , a second die 300 , a third die 730 , a fourth die 740 , a fifth die 750 , and a sixth die 760 .

[0129] The first die 200 and the third die 730 may be disposed on the package substrate 100 with the interposer 400 interposed therebetween, and the second die 300 , the fourth die 740 , the fifth die 750 , and the sixth die 760 may be directly disposed on the package substrate 100 .

[0130] When the first die 200, the second die 300, the third die 730, the fourth die 740, the fifth die 750, and the sixth die 760 are connected to each other in various forms, signals may be transmitted between them. As an example, the first die 200 and the third die 730 disposed on the interposer 400 may be connected to each other, the second die 300 and the fourth die 740 may be connected to each other on the package substrate 100, and the fifth die 750 and the sixth die 760 may be connected to each other on the package substrate 100. In addition, the first die 200 disposed on the interposer 400 may be connected to the second die 300 disposed on the package substrate 100, and the first die 200 disposed on the interposer 400 may be connected to the fifth die 750 disposed on the package substrate 100.

[0131] In some example embodiments, the first die 200 and the second die 300 may be connected to each other with the interposer 400 interposed therebetween, and the first die 200 and the second die 300 may be connected to the interposer 400 through bumps different from each other. The first die 200 and the fifth die 750 may be connected to each other with the interposer 400 interposed therebetween, and the first die 200 and the fifth die 750 may be connected to the interposer 400 through bumps different from each other. In detail, the first die 200 and the interposer 400 may be connected to each other through the first interconnect 510, and the third die 730 and the interposer 400 may be connected to each other through the first interconnect 510 including the first bump 510bp. The interposer 400 and the package substrate 100 may be connected to each other through the second interconnect 520, and the package substrate 100 and the second die 300 may be connected to each other through the second interconnect 520 including the second bump 520bp.

[0132] Therefore, the data channels that can be actually connected may be limited according to the connection relationship between the vias 401 of the interposer 400 and the bumps with different pitches, and in this case, the data channels can be selected by the remapping unit. Therefore, signals can be transmitted mutually between the first die 200 and the second die 300.

[0133] Since the first die 200 and the third die 730 disposed on the interposer 400 are connected to each other via the first bridge line BR1 in the interposer 400 and use the same type of data channel and the bump corresponding to the same type of data channel, remapping of the data channel may not be required. The second die 300 and the fourth die 740 disposed on the package substrate 100 may be connected to each other through the second bridge line BR2 and may use the same type of data channel and the bump corresponding to the same type of data channel, and the fifth die 750 and the sixth die 760 disposed on the package substrate 100 may be connected to each other through the second bridge line BR2 and may use the same type of data channel and the bump corresponding to the same type of data channel, and therefore, remapping of the data channel may not be required. In this case, the first bridge line BR1 may be configured to include a line within the interposer 400, however, it should not be limited thereto or thereby. According to some example embodiments, the first bridge line BR1 may include a separate silicon bridge and may be embedded in the interposer 400. The second bridge line BR2 may also be configured to include a line within the package substrate 100, however, it should not be limited thereto or thereby. According to some example embodiments, the second bridge line BR2 may include a separate silicon bridge, and may be embedded in the interposer 400 .

[0134] According to some example embodiments of the present disclosure, when the die is provided in plurality, communication between the dies may be implemented in various forms and should not be limited to the above-described embodiments. As an example, the third die 730 and the second die 300 may communicate with each other, however, according to some example embodiments, the third die 730 may be connected to and communicate with the fifth die 750.

[0135] In some example embodiments, the first die 200 and the third die 730 may be IC (integrated circuit) devices having the same or similar functions, or may be IC devices having different functions. The second die 300 and the fourth to sixth dies 740 to 760 may be IC devices having the same or similar functions, or may be IC devices having different functions.

[0136] In some example embodiments of the present disclosure, when multiple dies are included, a semiconductor package with hybrid interconnects may have various types of 2D and / or 2.5D structures. As an example, a semiconductor package with hybrid interconnects may include TSMC's Chip on Wafer on Substrate (CoWoS), Cadence's High-Bandwidth Interconnect (HBI), Intel's Universal Chiplet Interconnect Express (UCIe), Samsung's High-Bandwidth Bridge (HBB), and the like. When the above-mentioned different types of interconnects are used, the selection of a data channel may be difficult due to the limitation of the physical connection, and in this case, a remapping unit according to some example embodiments of the present disclosure may be adopted. Specifically, when it is difficult to select a data channel due to the use of different types of interconnects, even if the semiconductor package does not have a 2.5D structure including the interposer 400, a remapping unit according to some example embodiments of the present disclosure may be adopted.

[0137] According to some example embodiments of the present disclosure, some dies connected to a semiconductor package may be 3D IC devices. The 3D IC device may be a package-on-package (PoP) device using a connection method (e.g., wire bonding or flip chip), and specifically, the 3D IC device may be a sequentially stacked system-level package (SiP) or a sequentially stacked wafer-level package (WLP).

[0138] Fig. 10A and Fig. 10B is a diagram showing a semiconductor package according to some example embodiments of the present disclosure, and some dies on an interposer are three-dimensionally stacked 3D devices.

[0139] Reference Fig. 10A and Fig. 10B , the semiconductor package may include a first die 200 , a second die 300 , and a third die 730 . The first die 200 and the third die 730 may be disposed on the interposer 400 , and the second die 300 may be disposed on the package substrate 100 .

[0140] Fig. 10A The second die 300 and Fig. 10BThe third die 730 may be a 3D semiconductor device. As an example, the 3D semiconductor device may be a memory device having the following structure: five semiconductor chips 320 are vertically stacked on a logic substrate 340, or five semiconductor chips 720 and a memory control chip are vertically stacked on a logic substrate 740. In some example embodiments, five semiconductor chips are vertically stacked, however, the number and stacking direction of each of the semiconductor chips 320 and 720 should not be limited thereto or thereby limited. The number of each of the semiconductor chips 320 and 720 may be less than or more than five as required. The semiconductor chips 320 and 720 may be arranged on the logic substrates 340 and 740, respectively, in a horizontal direction, or may be arranged in a connection structure obtained by combining vertical mounting and horizontal mounting. In some example embodiments, the memory control chip 330 may be omitted. The semiconductor chips 320 and 720 may include via structures 322 and 722, respectively, and the via structures 322 and 722 may be electrically connected by interconnections (e.g., bumps). In some example embodiments, the via structures 322 and 722 may be omitted from the memory control chips 330 and 730 .

[0141] Each of the semiconductor chips 320 and 720 may include a system LSI, a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, or an RRAM. The memory control chip 330 may include a logic circuit, for example, a SerDes (Serializer / Deserializer) circuit.

[0142] The semiconductor package of the present disclosure may be applied or employed in a wide variety of electronic systems.

[0143] Fig.11 is a cross-sectional view showing an electronic system using a semiconductor package according to some example embodiments of the present disclosure. Fig. 10A An electronic system of a semiconductor package will be described as a representative example.

[0144] Reference Fig.11 , the electronic system 10 may include a main board 11 and a semiconductor package mounted on the main board 11 .

[0145] The third interconnect 530 may be disposed between the main board 11 and the semiconductor package. The third interconnect 530 may be an interconnect having substantially the same or the same type of bumps as the second interconnect 520, or may be an interconnect having different types of bumps than the first and second interconnects 510 and 520.

[0146] exist Fig.11, the electronic system is schematically shown, however, various electronic components including the semiconductor package according to some example embodiments of the present disclosure may be arranged on the above-mentioned main board 11. As an example, in addition to the above-mentioned semiconductor package, the electronic system may also be physically and / or electrically connected to a network component or other components.

[0147] The semiconductor package according to some example embodiments of the present disclosure may include various logic semiconductor devices and storage semiconductor devices, and may also include other types of related components. Network components may include IEEE 802.11 series (Wi-Fi), IEEE 802.16 series (WiMAX), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols specified thereafter, however, it should not be limited thereto or thereby limited. According to some example embodiments, the network component may include any one of a plurality of wireless or wired standards or protocols. In addition, network-related components may be combined with the semiconductor package in various ways.

[0148] As other components, high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. may be included, however, the present disclosure should not be limited thereto or thereby. According to some example embodiments, passive components for various other purposes may also be included. These other components may also be combined with the above-mentioned semiconductor packages and network-related components in various ways.

[0149] In addition, the electronic system may include other components, which may or may not be physically and / or electrically connected to the motherboard depending on their type. As other components, cameras, antennas, displays, batteries, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, and mass storage devices (e.g., hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.) may be used, however, they should not be limited thereto or thereby. In addition, depending on the type of electronic device, other components for various purposes may be included.

[0150] The electronic system may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook computer, a television, a video game, a smart watch, an automotive component, etc.

[0151] However, the present disclosure should not be limited thereto or thereby, and the electronic system may be any other electronic device that processes data in addition to those described above.

[0152] Although some example embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these example embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present disclosure as defined by the appended claims.

[0153] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0154] As described herein, any electronic device and / or portion thereof according to any example embodiment may include, may be included in, and / or may be implemented by one or more instances of: a processing circuit such as hardware including a logic circuit; a hardware / software combination such as a processor executing software; or any combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include: a non-transitory computer-readable storage device (e.g., a memory) storing a program of instructions, such as a DRAM device; and a processor (e.g., a CPU) configured to execute the program of instructions to implement the functions and / or methods and / or any portion thereof performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portion thereof according to any example embodiment.

[0155] Accordingly, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined in accordance with the following claims.

Claims

1. A semiconductor package, comprising a first die and a second die that transmit and / or receive signals to each other, the semiconductor package comprising: Package substrate; at least one first die on the package substrate and connected to the package substrate, with an interposer between the at least one first die and the package substrate; as well as At least one second die is on the packaging substrate and connected to the packaging substrate, each of the first die and the second die includes a transmitter and a receiver each including a data channel, and the number of data channels of the transmitter and / or the receiver of the first die is different from the number of data channels of the transmitter and / or the receiver of the second die.

2. The semiconductor package according to claim 1, further comprising: a first bump connected to a data channel corresponding to the transmitter and the receiver of the first die; as well as The second bumps are connected to data channels corresponding to the transmitter and the receiver of the second die.

3. The semiconductor package according to claim 2, wherein: The first bumps have a pitch different from a pitch of the second bumps.

4. The semiconductor package according to claim 3, wherein: The first bump is between the first die and the interposer, and the second bump is between the second die and the package substrate, and between the package substrate and the interposer.

5. The semiconductor package according to claim 4, wherein: The interposer includes a plurality of vias, and the first bump is connected to the second bump through the plurality of vias.

6. The semiconductor package according to claim 3, wherein: The number of data channels of the second die is smaller than the number of data channels of the first die.

7. The semiconductor package according to claim 1 further includes a remapping unit, which is configured to: in response to sending the signal between the data channel of the first tube core and the data channel of the second tube core, remap the signal in an order different from the input order of the signal input to the remapping unit, and output the remapped signals to the corresponding data channels respectively.

8. The semiconductor package according to claim 7, wherein: The transmitter and / or the receiver of each of the first die and the second die comprises: An input data channel configured to receive a signal; the remapping unit is configured to remap the signal of the input data channel and provide the signal of the input data channel to an output data channel; and The output data channel is configured to receive the remapped signal from the remapping unit and output the remapped signal.

9. The semiconductor package according to claim 8, wherein: The remapping unit is provided to each of the transmitter and the receiver of the first die.

10. The semiconductor package according to claim 8, wherein The remapping unit comprises: a first remapping unit and a second remapping unit provided to the transmitter and the receiver of the first die, respectively; and A third remapping unit and a fourth remapping unit are provided to the transmitter and the receiver of the second die, respectively.

11. The semiconductor package according to claim 10, wherein: The output data lanes of the transmitter of the first die are physically connected to the input data lanes of the receiver of the second die.

12. The semiconductor package according to claim 11, wherein The first remapping unit is configured to select a data channel physically connected to the input data channel of the receiver of the second die among the output data channels of the transmitter of the first die, and provide the signal. 13 . The semiconductor package of claim 1 , further comprising at least one third die on the interposer and / or the package substrate and connected to at least one of the first die and the second die.

14. The semiconductor package according to claim 1, wherein: Each of the first die and / or the second die includes at least one of a logic semiconductor device or a memory semiconductor device.

15. A semiconductor package, comprising: Package substrate; a first die on the packaging substrate and connected to the packaging substrate via a first interconnect; as well as a second die on the package substrate and connected to the package substrate via a second interconnect, The first interconnect includes first bumps arranged at a first pitch, the second interconnect includes second bumps arranged at a second pitch different from the first pitch, and At least one of the first die and the second die includes a remapping unit configured to assign signals arranged in a first order to the first bumps of the first interconnects and / or the second bumps of the second interconnects in a second order different from the first order.

16. The semiconductor package according to claim 15, wherein: Each of the first die and the second die includes a transmitter and a receiver each including a data channel, and the number of data channels of the transmitter and / or the receiver of the first die is different from the number of data channels of the transmitter and / or the receiver of the second die.

17. The semiconductor package according to claim 16, wherein: The transmitter and / or the receiver of each of the first die and the second die comprises: An input data channel configured to receive a signal; the remapping unit is configured to remap the signal of the input data channel and provide the signal of the input data channel to an output data channel; and The output data channel is configured to receive the remapped signal from the remapping unit and output the remapped signal.

18. The semiconductor package according to claim 16, wherein: Based on the fact that the number of data channels of the transmitter and the receiver of the first die is n and the number of data channels of the transmitter and the receiver of the second die is m (n>m) which is less than n, the remapping unit is configured to: select m data channels of the first die corresponding to the situation where the first bump is physically connected to the second bump from among the n data channels of the first die, and provide the signal.

19. The semiconductor package according to claim 16, wherein: The remapping unit comprises: a first remapping unit and a second remapping unit provided to the transmitter and the receiver of the first die, respectively; and A third remapping unit and a fourth remapping unit are provided to the transmitter and the receiver of the second die, respectively.

20. A method of sending a signal from a first die to a second die, comprising: allowing input data lanes to be arranged in a first order corresponding to signals to be transmitted in a transmitter of the first die; allowing the first remapping unit to select output data channels in a second order; outputting the signal to a receiver of the second die through the selected output data channel; allowing the receiver of the second die to receive the signals output from the first die in a third order through an input data channel; as well as The second remapping unit is allowed to select output data channels in the first order and output the signals.

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