Chip packaging structure and preparation method of chip packaging structure
By designing a chip packaging structure including glass core plate, interconnection unit and packaging unit in glass core plate packaging technology, the stability and reliability problems caused by exposed glass core plates are solved, and a higher stability and reliability of chip packaging structure is achieved.
Patent Information
- Application Number
- CN202411812000.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-03-18
AI Technical Summary
In glass core plate packaging technology, exposed glass core plates lead to a decrease in stability and reliability of the chip packaging structure.
A chip package structure is designed, including a glass core plate unit, a first interconnection unit and a second interconnection unit, connected by wires, a chip unit located on the side of the first interconnection unit away from the glass core plate unit, and a packaging unit is provided around the chip and the interconnection unit to provide protection.
By packaging the glass core plate unit, the stability and reliability of the chip packaging structure are improved, and the external environment is prevented from causing damage to the internal devices.
Smart Images
Figure CN119650547A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a chip packaging structure and a method for preparing the chip packaging structure. Background Art
[0002] Glass core board packaging technology is a packaging technology that uses glass materials as substrates. It uses glass's high thermal stability, low thermal expansion coefficient, good insulation and high mechanical strength to improve the performance and reliability of semiconductor devices. At present, when packaging chip structures based on glass core boards on the market, the glass core board is generally exposed, which will lead to a decrease in the stability and reliability of the chip packaging structure. Summary of the invention
[0003] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a chip packaging structure, wherein the chip packaging structure includes:
[0004] Glass core panel unit;
[0005] a first interconnection unit and a second interconnection unit located on opposite sides of the glass core plate unit, wherein the wire in the first interconnection unit and the wire in the second interconnection unit are connected through the glass core plate unit;
[0006] A chip unit located at a side of the first interconnection unit away from the glass core board unit, the chip unit comprising at least one chip, the chip comprising a pin side and a back side opposite to each other, the pin side of the chip being arranged toward the first interconnection unit and being electrically connected to the first interconnection unit;
[0007] The packaging unit is at least located around the chip, the side wall of the glass core board unit, the side wall of the first interconnection unit and the side wall of the second interconnection unit.
[0008] In a possible implementation manner, an orthographic projection of the packaging unit on the glass core board unit is at least partially located outside an orthographic projection of the chip unit on the glass core board unit.
[0009] In a possible implementation, the encapsulation unit includes a first encapsulation unit and a second encapsulation unit;
[0010] The first packaging unit wraps around the chip, the second packaging unit covers the side wall of the glass core board unit, the side wall of the first interconnection unit and the side wall of the second interconnection unit, the first packaging unit is connected to the second packaging unit, wherein the material of the first packaging unit is different from the material of the second packaging unit;
[0011] The first packaging unit and the second packaging unit form a flat packaging plane at the side wall of the first interconnection unit, the side wall of the glass core board unit and the side wall of the second interconnection unit.
[0012] In a possible implementation, the side wall of the first interconnected unit, the side wall of the glass core plate unit, and the side wall of the second interconnected unit form a step structure;
[0013] The side wall of the first interconnected unit extends relative to the side wall of the glass core plate unit to form a first step structure, and the side wall of the glass core plate unit extends relative to the side wall of the second interconnected unit to form a second step structure.
[0014] In a possible implementation manner, the width of the first step structure is a first width, and the width of the second step structure is a second width;
[0015] The first width is greater than the second width.
[0016] In a possible implementation, the chip packaging structure further includes a conductive ball, the conductive ball is located on a side of the second interconnect unit away from the glass core board unit, and the conductive ball is connected to a wire in the second interconnect unit.
[0017] Another object of the present application is to provide a method for preparing a chip packaging structure, the method comprising:
[0018] A wafer to be cut is provided, wherein the wafer comprises a second interconnection layer, a glass core board, a first interconnection layer, a chip layer and a packaging layer which are stacked in sequence, the chip layer comprises a plurality of chip units, a gap channel is provided between adjacent chip units, each chip unit comprises at least one chip, the chip comprises a pin side and a back side opposite to each other, the pin side of the chip is arranged toward the first interconnection layer and is electrically connected to the first interconnection layer;
[0019] Performing a first cutting on the second interconnect layer along the gap channels between adjacent chip units, dividing the second interconnect layer into a plurality of second interconnect units through the formed first cutting channels;
[0020] Performing a second cutting on the glass core board along the first cutting channel, dividing the glass core board into a plurality of glass core board units through the formed second cutting channel;
[0021] Performing a third cutting on the first interconnect layer along the second cutting path, dividing the first interconnect layer into a plurality of first interconnect units through the formed third cutting path;
[0022] The encapsulation glue is filled in the channel formed by cutting, and the encapsulation glue and the encapsulation layer are cut along the gap channel between adjacent chip units to obtain a chip encapsulation structure.
[0023] In a possible implementation, before the step of providing a wafer to be cut, the method further includes:
[0024] Providing a glass core board;
[0025] A first interconnection layer and a second interconnection layer are respectively manufactured on opposite sides of the glass core board, wherein the wires in the first interconnection layer and the wires in the second interconnection layer are connected through the glass core board;
[0026] Making a chip layer on a side of the first interconnection layer away from the glass core board;
[0027] A packaging layer is manufactured on a side of the chip layer away from the glass core board.
[0028] In a possible implementation manner, after the step of forming a packaging layer on a side of the chip layer away from the glass chip, the method further includes:
[0029] The encapsulation layer on the side of the chip layer away from the glass core board is ground, and the encapsulation layer on the back side of the chip is thinned.
[0030] In a possible implementation, the width of the first cutting channel is greater than the width of the second cutting channel, and the width of the second cutting channel is greater than the width of the third cutting channel;
[0031] The widths of the first cutting channel, the second cutting channel and the third cutting channel are sequentially reduced by 10 micrometers to 100 micrometers.
[0032] Based on any one of the above aspects, the embodiments of the present application provide a chip packaging structure and a method for preparing the chip packaging structure. Thus, through the above structure, the packaging of the glass core board unit is achieved, thereby improving the stability and reliability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0034] Figure 1 One of the schematic diagrams of a chip packaging structure provided in this embodiment;
[0035] Figure 2 for Figure 1 A partial enlarged view of the dotted box in the middle;
[0036] Figure 3 A second schematic diagram of a chip packaging structure provided in this embodiment;
[0037] Figure 4 A step diagram of a method for preparing a chip packaging structure provided in this embodiment;
[0038] Figure 5 for Figure 4 The corresponding process diagram;
[0039] Figure 6 for Figure 4 FIG. 1 is a diagram of method steps before step S110.
[0040] Icons: chip packaging structure-1, second interconnection layer-10, glass core board-11, first interconnection layer-12, chip layer-13, packaging layer-14, second interconnection unit-100, side wall of second interconnection unit-1001, glass core board unit-110, side wall of glass core board unit-1101, first interconnection unit-120, side wall of first interconnection unit-1201, chip unit-130, chip-1301, pin side-1301a, back side-1301b, packaging unit-140, first packaging unit-1401, second packaging unit-1402, conductive ball-150. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0042] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0043] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0044] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0045] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0046] In order to solve the technical problems mentioned in the aforementioned background technology, the inventor innovatively designed the following technical solution, and the specific implementation solution of the present application will be described in detail below with reference to the accompanying drawings.
[0047] See also Figure 1 , Figure 1 A schematic diagram of a chip packaging structure 1 provided in this embodiment. The chip packaging structure 1 includes a second interconnection unit 100 , a glass core board unit 110 , a first interconnection unit 120 , a chip unit 130 and a packaging unit 140 .
[0048] The second interconnection unit 100 and the first interconnection unit 120 are located at opposite sides of the glass core board unit 110, wherein the wires in the first interconnection unit 120 and the wires in the second interconnection unit 100 are connected through the glass core board unit 110. The chip unit 130 is located at a side of the first interconnection unit 120 away from the glass core board unit 110, and the chip unit 130 includes at least one chip 1301, and the chip 1301 includes opposite pin sides 1301a and back sides 1301b, and the pin side 1301a of the chip 1301 is arranged toward the first interconnection unit 120 and is electrically connected to the first interconnection unit 120.
[0049] In this embodiment, the glass core board unit 110 serves as the core of the chip packaging structure 1 and includes a plurality of through-glass holes, which provide mechanical support and electrical isolation for the chip packaging structure 1. The first interconnection unit 120 is located on one side of the glass core board unit 110. The first interconnection unit 120 is responsible for connecting the chip 1301 in the chip unit 130 with an external circuit and generally includes metal wires, which are electrically connected to the pin side 1301a of the chip 1301 through the through-glass holes on the glass core board unit 110.
[0050] The second interconnection unit 100 is opposite to the first interconnection unit 120 and is located on the other side of the glass core board unit 110. The second interconnection unit 100 also includes a wire, which is connected to the wire in the first interconnection unit 120 through the glass core board unit 110 to form a complete electrical connection path, realize bidirectional communication between the chip unit 130 and the external circuit, and provide additional electrical and mechanical stability.
[0051] It is worth noting that the chip unit 130 includes at least one chip 1301. The chip 1301 can be a high bandwidth memory (HBM) or an application-specific integrated circuit (ASIC), etc. The number and type of the chip 1301 are not specifically limited here and need to be selected according to actual conditions.
[0052] The packaging unit 140 is at least located around the chip 1301 , the side wall of the glass core board unit 110 , the side wall of the first interconnect unit 120 , and the side wall of the second interconnect unit 100 .
[0053] In this embodiment, the packaging unit 140 serves as the peripheral part of the chip packaging structure 1, and is located at least around the chip 1301, the side walls of the glass core board unit 110, the side walls of the first interconnection unit 120, and the side walls of the second interconnection unit 100. Its main function is to provide physical protection to prevent the external environment from causing damage to internal devices. It is usually made of plastic, ceramic or other polymer materials and has good mechanical strength.
[0054] Further, please see again Figure 1 , the orthographic projection of the packaging unit 140 on the glass core board unit 110 is at least partially located outside the orthographic projection of the chip unit 130 on the glass core board unit 110 .
[0055] In this embodiment, the chip unit 130 includes multiple chips 1301. The chip 1301 serves as the core component of the entire chip packaging structure 1. The packaging unit 140 covers the periphery of the chip unit 130, providing necessary protection and support for the chip unit 130, effectively preventing external environmental factors such as moisture, dust and other mechanical impacts from damaging the chip unit 130, and ensuring the reliability and stability of the chip 1301.
[0056] Further, please see again Figure 1 The encapsulation unit 140 includes a first encapsulation unit 1401 and a second encapsulation unit 1402 .
[0057] The first packaging unit 1401 wraps around the chip 1301, and the second packaging unit 1402 covers the side walls of the glass core board unit 110, the side walls of the first interconnection unit 120 and the side walls of the second interconnection unit 100. The first packaging unit 1401 is connected to the second packaging unit 1402, wherein the material of the first packaging unit 1401 is different from the material of the second packaging unit 1402.
[0058] The first packaging unit 1401 and the second packaging unit 1402 form a flat packaging plane at the side wall of the first interconnection unit 120 , the side wall of the glass core board unit 110 , and the side wall of the second interconnection unit 100 .
[0059] In this embodiment, the first packaging unit 1401 covers all sides of the chip 1301, providing direct physical protection to prevent the external environment from damaging the chip 1301. The second packaging unit 1402 covers the side walls of the glass core board unit 110, the side walls of the first interconnection unit 120 and the side walls of the second interconnection unit 100, providing additional protection and support, which helps to provide stability and reliability of the entire chip packaging structure 1.
[0060] The first packaging unit 1401 and the second packaging unit 1402 are connected to form a continuous protective layer. At the same time, the first packaging unit 1401 and the second packaging unit 1402 form a flat packaging plane at the side wall of the first interconnection unit 120, the side wall of the glass core board unit 110 and the side wall of the second interconnection unit 100, which helps to improve the overall appearance of the chip packaging structure 1 and ensure the integrity and mechanical stability of the chip packaging structure 1.
[0061] In addition, the first packaging unit 1401 and the second packaging unit 1402 use different materials to achieve different packaging requirements. The material of the first packaging structure 1401 includes resin, such as epoxy resin, which has excellent mechanical properties, adhesion and chemical resistance. The material of the second packaging structure 1402 includes epoxy molding compound (EMC), which is a thermosetting chemical material specially used for semiconductor packaging, which can protect the semiconductor chip from the external environment (such as water vapor, temperature, pollution, etc.) and realize the composite functions of heat conduction, insulation, moisture resistance, pressure resistance, support, etc.
[0062] For further information, see Figure 2 , Figure 2 for Figure 1A partial enlarged view of the dotted frame in the middle. The side wall 1201 of the first interconnected unit, the side wall 1101 of the glass core plate unit and the side wall of the second interconnected unit 1001 form a step structure, the side wall 1201 of the first interconnected unit extends relative to the side wall 1101 of the glass core plate unit to form a first step structure, and the side wall 1101 of the glass core plate unit extends relative to the side wall 1001 of the second interconnected unit to form a second step structure.
[0063] In this embodiment, the step structure design can provide additional support to enhance the overall strength and stability of the chip packaging structure 1. At the same time, the step structure design can provide more contact area for the packaging unit 140, thereby improving the overall performance and reliability of the chip packaging structure 1.
[0064] Further, please see again Figure 2 The width of the first step structure is a first width d1, the width of the second step structure is a second width d2, and the first width d1 is greater than the second width d2.
[0065] In this embodiment, the width of the step structure is reduced by continuously reducing the cutting width, and the first width d1 is designed to be greater than the second width d2, so that the chip packaging structure 1 forms obvious step differences between different levels. Such differences can provide better packaging effects, such as improving the mechanical strength, electrical isolation and thermal management performance of the package.
[0066] At the same time, the width difference can also provide better adhesion and sealing of the packaging unit 140 during the packaging process, thereby improving the reliability and durability of the chip packaging structure 1.
[0067] For further information, see Figure 3 The chip packaging structure 1 further includes a conductive ball 150 , which is located at a side of the second interconnect unit 100 away from the glass core board unit 110 , and is connected to a wire in the second interconnect unit 100 .
[0068] In this embodiment, the conductive ball 150 is located on the side of the second interconnection unit 100 away from the glass core board unit 110, and is connected to the wire in the second interconnection unit 100 to realize the electrical connection between the chip 1301 and the external circuit, and this connection allows signals and power to be transmitted between the chip 1301 and the external device. The design of the conductive ball 150 not only provides electrical connection, but also helps to improve the interconnection density and reliability of the package.
[0069] Based on the same concept, the present application also provides a method for preparing a chip packaging structure, see Figure 4 , Figure 4 A step diagram of a method for preparing a chip packaging structure provided in this embodiment, Figure 5 for Figure 4 Corresponding process flow chart, the method comprises the following steps:
[0070] Step S110, providing a wafer to be cut, wherein the wafer includes a second interconnect layer 10, a glass core board 11, a first interconnect layer 12, a chip layer 13 and a packaging layer 14 stacked in sequence, the chip layer 13 includes a plurality of chip units 130, and there is a gap channel between adjacent chip units 130, each chip unit 130 includes at least one chip 1301, the chip 1301 includes opposite pin sides 1301a and a back side 1301b, and the pin side 1301a of the chip 1301 is arranged toward the first interconnect layer 12 and is electrically connected to the first interconnect layer 12.
[0071] In this embodiment, the wafer is a basic material in semiconductor manufacturing, including a second interconnection layer 10, a glass core board 11, a first interconnection layer 12, a chip layer 13 and a packaging layer 14 stacked in sequence. The chip layer 13 includes a plurality of chip units 130, which are the basic parts of the final chip packaging structure 1. There are gap channels between adjacent chip units 130, which play a key role in the cutting process.
[0072] In addition, the chip 1301 includes a pin side 1301 a and a back side 1301 b opposite to each other. The pin side 1301 a of the chip 1301 is disposed toward the first interconnection layer 12 and is electrically connected to the first interconnection layer 12 to achieve electrical functions.
[0073] Step S120 , performing a first cutting on the second interconnect layer 10 along the gap channels between adjacent chip units 130 , and dividing the second interconnect layer 10 into a plurality of second interconnect units 100 through the formed first cutting channels.
[0074] Step S130 , cutting the glass core board 11 for a second time along the first cutting channel, and dividing the glass core board 11 into a plurality of glass core board units 110 through the formed second cutting channel.
[0075] In this embodiment, the glass core board unit 110 serves as a substrate of the chip packaging structure 1 .
[0076] Step S140 , cutting the first interconnect layer 12 for a third time along the second cutting channel, and dividing the first interconnect layer 12 into a plurality of first interconnect units 120 through the formed third cutting channel.
[0077] In this step, the first interconnect layer 12 and a portion of the packaging layer 14 are cut for the third time.
[0078] Step S150 , filling the channels formed by cutting with packaging glue, and cutting the packaging glue and the packaging layer 14 along the gap channels between adjacent chip units 130 to obtain a chip packaging structure 1 .
[0079] In this embodiment, the channel formed by cutting is filled with packaging glue, the material of the glue includes resin, and after the glue is cured, the packaging glue and the packaging layer 14 are cut along the gap channel between adjacent chip units 130 to finally obtain a chip packaging structure 1.
[0080] Furthermore, please combine Figure 6 Before step S110, the method further includes:
[0081] Step S70: providing a glass core board 11.
[0082] In this embodiment, the glass core board 11 is a key component of the chip packaging structure 1 and provides mechanical support and electrical isolation.
[0083] Step S80 , respectively manufacturing a first interconnection layer 12 and a second interconnection layer 10 on opposite sides of the glass core board 11 , wherein the wires in the first interconnection layer 12 and the wires in the second interconnection layer 10 are connected through the glass core board 11 .
[0084] In this embodiment, the first interconnection layer 12 and the second interconnection layer 10 are responsible for the electrical connection between the chip 1301 in the chip layer 13 and the external circuit. The wires in the first interconnection layer 12 and the wires in the second interconnection layer 10 are connected through the glass core board 11 to form a complete electrical path. This design allows signals to be transmitted between the chip 1301 and the external circuit.
[0085] Step S90 , manufacturing a chip layer 13 on a side of the first interconnect layer 12 away from the glass core board 11 .
[0086] In this step, the chip layer 13 includes a plurality of chip units 130, each chip unit 130 includes at least one chip 1301, and the chip 1301 has a pin side 1301a and a back side 1301b opposite to each other. The pin side 1301a of the chip 1301 is arranged toward the first interconnection layer 12 and is electrically connected to the first interconnection layer 12 to achieve electrical functions.
[0087] Step S100 , manufacturing a packaging layer 14 on a side of the chip layer 13 away from the glass core board 11 .
[0088] In this embodiment, the packaging layer 14 functions to protect the chip 1301 in the chip layer 13 from the influence of the external environment, such as moisture, dust and mechanical shock.
[0089] Furthermore, after step S100, the method further includes:
[0090] The encapsulation layer 14 on the side of the chip layer 13 away from the glass core board 11 is ground, and the encapsulation layer 14 on the back side 1301b of the chip 1301 is thinned.
[0091] In this embodiment, by thinning the packaging layer 14 on the back side 1301b of the chip 1301 in the chip layer 13, the heat generated by the chip 1301 during operation can be transferred out faster and more effectively, avoiding local overheating and improving the overall performance of the chip packaging structure 1.
[0092] Further, the width of the first cutting channel is greater than the width of the second cutting channel, and the width of the second cutting channel is greater than the width of the third cutting channel. The widths of the first cutting channel, the second cutting channel, and the third cutting channel decrease by 10 micrometers to 100 micrometers in sequence.
[0093] In this embodiment, the widths of the three cuts of the wafer are reduced successively to realize the design of a step structure. Specifically, the side wall 1201 of the first interconnected unit extends relative to the side wall 1101 of the glass core board unit to form a first step structure, and the side wall 1101 of the glass core board unit extends relative to the side wall 1001 of the second interconnected unit to form a second step structure.
[0094] The step structure design can provide additional support to enhance the overall strength and stability of the chip packaging structure 1 . At the same time, the step structure design can provide more contact area for the packaging unit 140 , thereby improving the overall performance and reliability of the chip packaging structure 1 .
[0095] The width of the first cutting channel is 10 to 100 microns greater than the width of the second cutting channel. For example, the first cutting channel is 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, etc. greater than the width of the second cutting channel. The width of the second cutting channel is 10 to 100 microns greater than the width of the third cutting channel. For example, the second cutting channel is 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, etc. greater than the width of the third cutting channel.
[0096] In summary, the present application provides a chip packaging structure and a method for preparing the chip packaging structure. The chip packaging structure includes a glass core board unit, a first interconnection unit and a second interconnection unit located on opposite sides of the glass core board unit, wherein the wires in the first interconnection unit and the wires in the second interconnection unit are connected through the glass core board unit. A chip unit is located on the side of the first interconnection unit away from the glass core board unit, the chip unit includes at least one chip, the chip includes a relative pin side and a back side, the pin side of the chip is arranged toward the first interconnection unit and is electrically connected to the first interconnection unit. The packaging units are at least located around the chip, the side walls of the glass core board unit, the side walls of the first interconnection unit, and the side walls of the second interconnection unit. In this way, through the above structure, the packaging of the glass core board unit is achieved, and the stability and reliability of the chip packaging structure are improved.
[0097] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging structure, characterized in that: The chip packaging structure comprises: Glass core panel unit; a first interconnection unit and a second interconnection unit located on opposite sides of the glass core plate unit, wherein the wire in the first interconnection unit and the wire in the second interconnection unit are connected through the glass core plate unit; A chip unit located at a side of the first interconnection unit away from the glass core board unit, the chip unit comprising at least one chip, the chip comprising a pin side and a back side opposite to each other, the pin side of the chip being arranged toward the first interconnection unit and being electrically connected to the first interconnection unit; The packaging unit is at least located around the chip, the side wall of the glass core board unit, the side wall of the first interconnection unit and the side wall of the second interconnection unit.
2. The chip packaging structure according to claim 1, characterized in that: The orthographic projection of the packaging unit on the glass core board unit is at least partially located outside the orthographic projection of the chip unit on the glass core board unit.
3. The chip packaging structure according to claim 1, characterized in that: The packaging unit includes a first packaging unit and a second packaging unit; The first packaging unit wraps around the chip, the second packaging unit covers the side wall of the glass core board unit, the side wall of the first interconnection unit and the side wall of the second interconnection unit, the first packaging unit is connected to the second packaging unit, wherein the material of the first packaging unit is different from the material of the second packaging unit; The first packaging unit and the second packaging unit form a flat packaging plane at the side wall of the first interconnection unit, the side wall of the glass core board unit and the side wall of the second interconnection unit.
4. The chip packaging structure according to claim 1, characterized in that: The side wall of the first interconnected unit, the side wall of the glass core plate unit and the side wall of the second interconnected unit form a step structure; The side wall of the first interconnected unit extends relative to the side wall of the glass core plate unit to form a first step structure, and the side wall of the glass core plate unit extends relative to the side wall of the second interconnected unit to form a second step structure.
5. The chip packaging structure according to claim 4, characterized in that: The width of the first step structure is a first width, and the width of the second step structure is a second width; The first width is greater than the second width.
6. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a conductive ball, which is located on a side of the second interconnection unit away from the glass core board unit, and is connected to a wire in the second interconnection unit.
7. A method for preparing a chip packaging structure, characterized in that: The method comprises: A wafer to be cut is provided, wherein the wafer comprises a second interconnection layer, a glass core board, a first interconnection layer, a chip layer and a packaging layer which are stacked in sequence, the chip layer comprises a plurality of chip units, a gap channel is provided between adjacent chip units, each chip unit comprises at least one chip, the chip comprises a pin side and a back side opposite to each other, the pin side of the chip is arranged toward the first interconnection layer and is electrically connected to the first interconnection layer; Performing a first cutting on the second interconnect layer along the gap channels between adjacent chip units, dividing the second interconnect layer into a plurality of second interconnect units through the formed first cutting channels; Performing a second cutting on the glass core board along the first cutting channel, dividing the glass core board into a plurality of glass core board units through the formed second cutting channel; Performing a third cutting on the first interconnect layer along the second cutting path, dividing the first interconnect layer into a plurality of first interconnect units through the formed third cutting path; The encapsulation glue is filled in the channel formed by cutting, and the encapsulation glue and the encapsulation layer are cut along the gap channel between adjacent chip units to obtain a chip encapsulation structure.
8. The method for preparing a chip packaging structure according to claim 7, characterized in that: Before the step of providing a wafer to be cut, the method further comprises: Providing a glass core board; A first interconnection layer and a second interconnection layer are respectively manufactured on opposite sides of the glass core board, wherein the wires in the first interconnection layer and the wires in the second interconnection layer are connected through the glass core board; Making a chip layer on a side of the first interconnection layer away from the glass core board; A packaging layer is manufactured on a side of the chip layer away from the glass core board.
9. The method for preparing a chip packaging structure according to claim 8, characterized in that: After the step of forming a packaging layer on a side of the chip layer away from the glass chip, the method further comprises: The encapsulation layer on the side of the chip layer away from the glass core board is ground, and the encapsulation layer on the back side of the chip is thinned.
10. The method for preparing a chip packaging structure according to claim 7, characterized in that: The width of the first cutting channel is greater than the width of the second cutting channel, and the width of the second cutting channel is greater than the width of the third cutting channel; The widths of the first cutting channel, the second cutting channel and the third cutting channel are sequentially reduced by 10 micrometers to 100 micrometers.