Duty ratio adjusting circuit and memory

Abstract

The invention discloses a duty ratio adjusting circuit and a memory. The duty ratio adjusting circuit comprises a duty ratio adjusting link, a duty ratio detector and a state machine, and the duty ratio adjusting link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty ratio detector is coupled with the duty ratio adjusting link so as to generate a corresponding detection signal based on the detected duty ratio of the output clock signal; the state machine is coupled with the duty ratio detector so as to generate a corresponding control code based on the detection signal; the duty ratio adjusting link comprises a plurality of inverter units connected in series, a first adjusting link and a second adjusting link. The first adjusting link and the second adjusting link are both coupled to the same intermediate node of the duty ratio adjusting link. Through the above mode, the first adjusting link and the second adjusting link are coupled to the same intermediate node of the duty ratio adjusting link, so that the time delay of the duty ratio adjusting circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of duty cycle regulation, and in particular to a duty cycle adjustment circuit and a memory. Background Art

[0002] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream of random access memory and is a typical semiconductor memory. DDR type memory is designed to synchronously input or output data at the rising and falling edges of the clock signal. Therefore, the duty cycle of the clock signal needs to be accurately maintained at 50%. For this reason, the chip usually uses a duty cycle adjustment circuit to adjust the duty cycle of the clock signal. The chip specification specifies the delays related to memory chip reading, writing and on-die termination (ODT), so the delay of the delay-locked loop path cannot be too long. The duty cycle adjustment circuit is part of the delay-locked loop path, so it is necessary to reduce the delay of the duty cycle adjustment circuit. Summary of the invention

[0003] In order to solve the above problems, the present application provides a duty cycle adjustment circuit and a memory to save the delay of the duty cycle adjustment circuit, thereby saving the delay of the delay locked loop path.

[0004] In order to solve the above technical problems, a technical solution adopted by the present application is: providing a duty cycle adjustment circuit, which includes a duty cycle adjustment link, a duty cycle detector and a state machine, the duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; the state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; wherein the duty cycle adjustment link includes a plurality of inverter units connected in series, a first adjustment link and a second adjustment link, the first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link, and the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node is adjusted based on the control code and the detection signal, thereby adjusting the duty cycle of the output clock signal, wherein the intermediate node is the connection point between the two inverter units.

[0005] Among them, the duty cycle adjustment circuit also includes a bias voltage generating module, which is respectively coupled to the state machine, the first adjustment link and the second adjustment link, and is used to generate a corresponding bias voltage based on the control code and provide it to the first adjustment link and the second adjustment link; wherein the first adjustment link and the second adjustment link adjust the pull-down current or pull-up current of the same intermediate node in the duty cycle adjustment link based on the detection signal and the bias voltage, so as to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal.

[0006] Among them, the bias voltage includes a first bias voltage and a second bias voltage, the first regulation link includes a first transmission gate branch and a discharge branch, the first transmission gate branch receives a detection signal and a first bias voltage, and is used to control the conduction or cutoff of the discharge branch based on the detection signal and the first bias voltage; the discharge branch is coupled to the first transmission gate branch and the intermediate node, and in response to the discharge branch being turned on, the discharge branch performs a discharge operation on the intermediate node to adjust the slope of the rising edge of the intermediate clock signal.

[0007] Among them, the second regulation link includes a second transmission gate branch and a charging branch, the second transmission gate branch receives a detection signal and a second bias voltage, and is used to control the conduction or shutoff of the charging branch based on the detection signal and the second bias voltage; the charging branch is coupled to the second transmission gate branch and the intermediate node, and in response to the charging branch being turned on, the charging branch performs a charging operation on the intermediate node to adjust the slope of the falling edge of the intermediate clock signal.

[0008] The first transmission gate branch includes a first transmission gate and a first transistor, the input end of the first transmission gate receives a first bias voltage, the first control end of the first transmission gate receives a detection signal, and the second control end of the first transmission gate receives an inverted detection signal; the first channel end of the first transistor is grounded, the second channel end of the first transistor is coupled to the output end of the first transmission gate and the discharge branch; the control end of the first transistor receives the inverted detection signal; the discharge branch includes a second transistor and a third transistor, the control end of the second transistor is coupled to the output end of the first transmission gate and the second channel end of the first transistor, the first channel end of the second transistor is coupled to the input end of the inverter unit at the next stage of the intermediate node, the control end of the third transistor is coupled to the output end of the inverter unit at the next stage of the intermediate node, the first channel end of the third transistor is coupled to the second channel end of the second transistor, and the second channel end of the third transistor is grounded; when the detection signal is at a high level, the first transmission gate is turned on and the first transistor is turned off, the control end of the second transistor receives the first bias voltage, the second transistor and the third transistor are turned on, a corresponding pull-down current is generated between the second transistor and the third transistor, and a discharge operation is performed on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

[0009] The second transmission gate branch includes a second transmission gate and a fourth transistor, the input end of the second transmission gate receives a second bias voltage, the first control end of the second transmission gate receives an inverted detection signal, and the second control end of the second transmission gate receives the detection signal; the first channel end of the fourth transistor receives a preset voltage, the second channel end of the fourth transistor is coupled to the output end of the second transmission gate and the charging branch; the control end of the fourth transistor receives the inverted detection signal; the charging branch includes a fifth transistor and a sixth transistor, the control end of the fifth transistor is coupled to the output end of the second transmission gate and the second channel end of the fourth transistor, and the first channel end of the fifth transistor is coupled to the output end of the second transmission gate and the second channel end of the fourth transistor. The control terminal of the sixth transistor is coupled to the input terminal of the inverter unit of the next stage after the intermediate node, the control terminal of the sixth transistor is coupled to the output terminal of the inverter unit of the next stage after the intermediate node, the first channel terminal of the sixth transistor is coupled to the second channel terminal of the fifth transistor, and the second channel terminal of the sixth transistor receives a preset voltage; wherein, when the detection signal is at a low level, the second transmission gate is turned on and the fourth transistor is turned off, the control terminal of the fifth transistor receives a second bias voltage, the fifth transistor and the sixth transistor are turned on, a corresponding pull-up current is generated between the fifth transistor and the sixth transistor, and a charging operation is performed on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

[0010] Among them, in response to the intermediate clock signal being in phase with the initial clock signal, the first adjustment link is used to narrow the duty cycle of the output clock signal based on the first bias voltage and the detection signal; the second adjustment link is used to increase the duty cycle of the output clock signal based on the second bias voltage and the detection signal; in response to the intermediate clock signal being out of phase with the initial clock signal, the first adjustment link is used to increase the duty cycle of the output clock signal based on the first bias voltage and the detection signal; the second adjustment link is used to narrow the duty cycle of the output clock signal based on the second bias voltage and the detection signal.

[0011] Among them, the bias voltage generating module includes a bias current generating module and a current mirror module; the bias current generating module includes a plurality of bias current branches connected in parallel, and adjusts the number of bias current branches connected based on a control code to generate a corresponding bias current; the current mirror module is coupled to the bias current generating module to generate a first bias voltage and a second bias voltage based on the bias current, and the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0012] The current mirror module includes a seventh transistor, an eighth transistor, a ninth transistor and a first capacitor; a first channel end of the seventh transistor is connected to the output end of the bias current generating module and coupled to the control end of the seventh transistor, a second channel end of the seventh transistor is grounded, and the control end of the seventh transistor is also used to output a first bias voltage; the control end of the eighth transistor is connected to the control end of the seventh transistor, the first channel end of the eighth transistor is connected to the second channel end of the ninth transistor, and the second channel end of the eighth transistor is grounded; the first channel end of the ninth transistor receives the first working voltage, the control end of the ninth transistor is coupled to the second channel end of the ninth transistor, and is used to output a second bias voltage; a first end of the first capacitor is grounded, and a second end of the first capacitor is respectively coupled to the control end of the seventh transistor and the control end of the eighth transistor.

[0013] Each bias current branch in the bias current generating module includes a tenth transistor and a switch, the control end of the tenth transistor receives a reference voltage, and the first channel end of the tenth transistor receives a second working voltage; the first end of the switch is coupled to the second channel end of the tenth transistor, the second end of the switch is coupled to the bias current output module, and the control end of the switch is used to receive a control code to determine whether the corresponding bias current branch is turned on based on the control of the control code.

[0014] Among them, the bias voltage generating module includes a first bias voltage generating module and a second bias voltage generating module, wherein the first bias voltage generating module is used to generate a first bias voltage, and the second bias voltage generating module is used to generate a second bias voltage, and the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0015] In order to solve the above technical problem, another technical solution adopted in the present application is: to provide a memory, which includes any one of the duty cycle adjustment circuits mentioned above.

[0016] Different from the prior art, the duty cycle adjustment circuit of the present application includes a duty cycle adjustment link, a duty cycle detector and a state machine, the duty cycle adjustment link receives an initial clock signal, and adjusts the initial clock signal to generate an output clock signal; the duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; the state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; wherein, the duty cycle adjustment link includes a plurality of inverter units connected in series, a first adjustment link and a second adjustment link, the first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link, and the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node is adjusted based on the control code and the detection signal, thereby adjusting the duty cycle of the output clock signal, and the intermediate node is the connection point between the two inverter units. Through the above method, the first adjustment link and the second adjustment link of the present application can be coupled to the same intermediate node of the duty cycle adjustment link, and there is no need to adjust the duty cycle of the output clock signal separately at the two intermediate nodes of the duty cycle adjustment link, thereby reducing the inverter units connected in series in the duty cycle adjustment link, thereby saving the delay of the duty cycle adjustment circuit and the delay of the delay locked loop path. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 is a schematic diagram of a first embodiment of a duty cycle adjustment circuit provided by the present application;

[0019] Figure 2 This is a schematic diagram of the second embodiment of the duty cycle adjustment circuit provided by the present application.

[0020] Figure 3 is a schematic diagram of an embodiment of a duty cycle adjustment link provided by the present application;

[0021] Figure 4 It is a waveform diagram of the intermediate clock signal adjustment process;

[0022] Figure 5 is a circuit structure diagram of a first embodiment of a bias voltage generating module provided by the present application;

[0023] Figure 6 is a circuit structure diagram of a third embodiment of a duty cycle adjustment circuit provided by the present application;

[0024] Figure 7 is a structural schematic diagram of an embodiment of a first bias voltage generating module provided by the present application;

[0025] Figure 8 It is a schematic diagram of the structure of a memory device according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream of random access memory and is a typical semiconductor memory. DDR type memory is designed to synchronously input or output data at the rising and falling edges of the clock signal. Therefore, the duty cycle of the clock signal needs to be accurately maintained at 50%. For this reason, the chip usually uses a duty cycle adjustment circuit to adjust the duty cycle of the clock signal. The chip specification specifies the delays related to memory chip reading, writing and on-die termination (ODT), so the delay of the delay-locked loop path cannot be too long. The duty cycle adjustment circuit is part of the delay-locked loop path, so it is necessary to reduce the delay of the duty cycle adjustment circuit.

[0029] In order to solve the above problems, the present application first proposes a duty cycle adjustment circuit. Figure 1 , Figure 1 is a schematic diagram of the first embodiment of the duty cycle adjustment circuit provided by the present application. Figure 1 As shown, the duty cycle adjustment circuit 100 of this embodiment includes a duty cycle adjustment link 10 , a duty cycle detector 20 and a state machine 30 .

[0030] like Figure 1As shown, the duty cycle adjustment link 10 receives the initial clock signal CLKIN and adjusts the initial clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detector 20 is coupled to the duty cycle adjustment link 10 to generate a corresponding detection signal based on the detected duty cycle of the output clock signal CLKOUT; the state machine 30 is coupled to the duty cycle detector 20 to generate a corresponding control code code based on the detection signal <n:1>The duty cycle regulation link 10 includes a plurality of inverter units 11 connected in series, a first regulation link 12 and a second regulation link 13, both of which are coupled to the same intermediate node of the duty cycle regulation link 10, and based on the control code code <n:1>The detection signal adjusts the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT. In this embodiment, the intermediate node of the duty cycle adjustment link 10 is the connection point between the two inverter units 11. It is worth noting that in some embodiments, the duty cycle adjustment link 10 does not directly receive the control code code <n:1>, but based on the control code code <n:1>The detection signal generates other signals to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node.

[0031] In this embodiment, the first adjustment link 12 and the second adjustment link 13 in the duty cycle adjustment link 10 are coupled to the same intermediate node of the duty cycle adjustment link 10, that is, coupled to the same connection point between the two inverter units 11, and are used to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT, wherein the specific circuit structures of the first adjustment link 12 and the second adjustment link 13 are shown below and are not described in detail here.

[0032] The duty cycle detector 20 performs duty cycle detection on the output clock signal CLKOUT of the duty cycle adjustment link 10. The duty cycle detector 20 periodically outputs a detection signal during the detection process. In this embodiment, the detection signal is a level signal. If the detection signal is output as a logic level "1", it indicates that the duty cycle is greater than 50%, and if the detection signal is output as a logic level "0", it indicates that the duty cycle is less than 50%. In other embodiments, the detection signal may also be output as a logic level "0" to indicate that the duty cycle is greater than 50%, and if the detection signal is output as a logic level "1", it indicates that the duty cycle is less than 50%. The relationship between the logic level of the detection signal and the size of the duty cycle is not limited here.

[0033] When the state machine 30 receives the detection signal of the duty cycle detector 20, it will generate a corresponding control code code <n:1>, based on the control code code <n:1>In this embodiment, the first adjustment link 12 and the second adjustment link 13 are coupled to the same intermediate node of the duty cycle adjustment link 10, and can work respectively under the control of the corresponding bias voltage and the detection signal of the duty cycle detector 20, so as to adjust the duty cycle of the output clock signal CLKOUT of the duty cycle adjustment link 10.

[0034] In addition, in this embodiment, the first regulation link 12 and the second regulation link 13 will not work at the same time. Under the control of the detection signal, only one of the first regulation link 12 and the second regulation link 13 can work. In this embodiment, the number of inverter units 11 of the duty cycle regulation link 10 is generally set to an even number, so that the initial clock signal CLKIN and the output clock signal CLKOUT are in phase.

[0035] Different from the prior art, the duty cycle adjustment circuit 100 of the present application includes a duty cycle adjustment link 10, a duty cycle detector 20 and a state machine 30. The duty cycle adjustment link 10 receives an initial clock signal CLKIN and adjusts the initial clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detector 20 is coupled to the duty cycle adjustment link 10 to generate a corresponding detection signal based on the detected duty cycle of the output clock signal CLKOUT; the state machine 30 is coupled to the duty cycle detector 20 to generate a corresponding control code code based on the detection signal <n:1>The duty cycle regulation link 10 includes a plurality of inverter units 11 connected in series, a first regulation link 12 and a second regulation link 13, both of which are coupled to the same intermediate node of the duty cycle regulation link 10, and based on the control code code <n:1>The detection signal adjusts the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT, and the intermediate node is the connection point between the two inverter units 11. In the above manner, the first adjustment link 12 and the second adjustment link 13 of the present application can be coupled to the same intermediate node of the duty cycle adjustment link 10, and there is no need to adjust the duty cycle of the output clock signal CLKOUT at the two intermediate nodes of the duty cycle adjustment link 10 respectively, so that the inverter units 11 connected in series in the duty cycle adjustment link 10 can be reduced, thereby saving the delay of the duty cycle adjustment circuit 100 and the delay of the delay locked loop path.

[0036] Optionally, based on the above embodiment, please refer to Figure 2 , Figure 2 is a schematic diagram of a second embodiment of a duty cycle adjustment circuit provided by the present application. Figure 2 As shown, the duty cycle adjustment circuit 100 further includes a bias voltage generation module 40, which is coupled to the state machine 30, the first adjustment link 12 and the second adjustment link 13 respectively, and is used to adjust the duty cycle based on the control code code <n:1>Generate a corresponding bias voltage and provide it to the first regulation link 12 and the second regulation link 13; wherein the first regulation link 12 and the second regulation link 13 adjust the pull-down current or the pull-up current of the same intermediate node in the duty cycle regulation link 10 based on the detection signal and the bias voltage, so as to adjust the slope of the rising edge or the falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT.

[0037] Among them, in this embodiment, the bias voltage generating module 40 can be a voltage generating module, which provides the first bias voltage and the second bias voltage for the first adjustment link 12 and the second adjustment link 13 respectively; in other embodiments, the bias voltage generating module 40 can also be set as two voltage generating modules, which provide the first bias voltage and the second bias voltage for the first adjustment link 12 and the second adjustment link 13 respectively, which is not limited here.

[0038] Optionally, based on the above embodiments, in this embodiment, in response to the intermediate clock signal being in phase with the initial clock signal CLKIN, the first adjustment link 12 is used to narrow the duty cycle of the output clock signal CLKOUT based on the first bias voltage and the detection signal; the second adjustment link 13 is used to increase the duty cycle of the output clock signal CLKOUT based on the second bias voltage and the detection signal; in response to the intermediate clock signal being out of phase with the initial clock signal CLKIN, the first adjustment link 12 is used to increase the duty cycle of the output clock signal CLKOUT based on the first bias voltage and the detection signal; the second adjustment link 13 is used to narrow the duty cycle of the output clock signal CLKOUT based on the second bias voltage and the detection signal.

[0039] Optionally, based on the above embodiment, please refer to Figure 3 , Figure 3 is a schematic diagram of an embodiment of a duty cycle adjustment link provided by the present application. In this embodiment, as described above, the bias voltage includes a first bias voltage and a second bias voltage. Figure 3 As shown, the first regulation link 12 of the present embodiment includes a first transmission gate branch 121 and a discharge branch 122. The first transmission gate branch 121 receives a detection signal and a first bias voltage, and is used to control the on or off of the discharge branch 122 based on the detection signal and the first bias voltage; the discharge branch 122 couples the first transmission gate branch 121 and the intermediate node. In response to the discharge branch 122 being turned on, the discharge branch 122 performs a discharge operation on the intermediate node to adjust the slope of the rising edge of the intermediate clock signal.

[0040] Optionally, based on the above embodiment, Figure 3 As shown, the first transmission gate branch 121 of the present embodiment includes a first transmission gate TG1 and a first transistor M1, the input end of the first transmission gate TG1 receives the first bias voltage, the first control end of the first transmission gate TG1 receives the detection signal, and the second control end of the first transmission gate TG1 receives the inverted detection signal; the first pass end of the first transistor M1 is grounded, the second pass end of the first transistor M1 is coupled to the output end of the first transmission gate TG1 and the discharge branch 122; the control end of the first transistor M1 receives the inverted detection signal; the discharge branch 122 includes a second transistor M2 and a third transistor M3, the control end of the second transistor M2 is coupled to the output end of the first transmission gate TG1 and the second pass end of the first transistor M1, the first pass end of the second transistor M2 is coupled to the input end of the inverter unit 11 at the next stage of the intermediate node, the control end of the third transistor M3 is coupled to the output end of the inverter unit 11 at the next stage of the intermediate node, the first pass end of the third transistor M3 is coupled to the second pass end of the second transistor M2, and the second pass end of the third transistor M3 is grounded;

[0041] When the detection signal is at a high level, the first transmission gate TG1 is turned on and the first transistor M1 is turned off, the control end of the second transistor M2 receives the first bias voltage, the second transistor M2 and the third transistor M3 are turned on, and a corresponding pull-down current is generated between the second transistor M2 and the third transistor M3, and a discharge operation is performed on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

[0042] For example, Figure 3 As shown, the first transistor M1, the second transistor M2 and the third transistor M3 in the first regulation link 12 are all NMOS transistors, the intermediate clock signal CLK1 of the intermediate node coupled to the first regulation link 12 and the second regulation link 13 is in phase with the initial clock signal CLKIN, and the first control end of the first transmission gate TG1 is the gate of the NMOS transistor in the first transmission gate TG1; the second control end of the first transmission gate TG1 is the gate of the PMOS transistor in the first transmission gate TG1. At this time, the first regulation link 12 is used to narrow the duty cycle of the output clock signal CLKOUT based on the first bias voltage and the detection signal.

[0043] The working principle of the first regulation link 12 to narrow the duty cycle of the output clock signal CLKOUT is as follows:

[0044] The input end of the first transmission gate TG1 receives the first bias voltage, the first control end of the first transmission gate TG1 receives the detection signal VSEL, and the second control end of the first transmission gate TG1 and the control end of the first transistor M1 receive the inverted detection signal VSELB. If the detection signal output by the duty cycle detector 20 is at a high level, it means that the duty cycle of the output clock signal CLKOUT is greater than 50%. At this time, the detection signal VSEL is also at a high level, and the inverted detection signal VSELB is at a low level. At this time, the first transmission gate TG1 is turned on, the first transistor M1 in the first regulation link 12 is turned off, and the first transmission gate TG1 transmits the first bias voltage to the control end of the second transistor M2. At this time, the discharge branch 122 is working, and the second transistor M2 is in a conducting state.

[0045] In this embodiment, since the control terminal of the third transistor M3 is coupled to the output terminal of the inverter unit 11 at the subsequent stage of the intermediate node, the control terminal of the third transistor M3 receives the inverted intermediate clock signal CLK1B.

[0046] See also Figure 4 , Figure 4 Figure 1 is a waveform diagram of the intermediate clock signal adjustment process. Figure 4 As shown, when the intermediate clock signal CLK1 is at the rising edge, the inverted intermediate clock signal CLK1B still stays at a high level. At this time, the second transistor M2 and the third transistor M3 are both in the on state. As the voltage of the node corresponding to the intermediate clock signal CLK1 increases, the second transistor M2 and the third transistor M3 generate a pull-down current I1, which slows down the rising speed of the node corresponding to the intermediate clock signal CLK1; when the intermediate clock signal CLK1 rises to the flip point of the inverter unit 11 after the intermediate node, the inverted intermediate clock signal CLK1B starts from high to low; when the inverted intermediate clock signal CLK1B drops below the control terminal threshold voltage of the third transistor M3, the third transistor M3 is turned off, and I1 gradually decreases to 0; when I1=0, the intermediate clock signal CLK1 continues to be driven by the inverter unit 11 of the previous stage, and its voltage is quickly pulled up to the power supply voltage. After being shaped by the inverter unit 11 in the subsequent link, the duty cycle of the output clock signal CLKOUT is finally narrowed. It can be seen that during the adjustment process, the higher the first bias voltage is, the larger the pull-down current I1 is, the slower the rising speed of the intermediate clock signal CLK1 is, and the more the duty cycle of the output clock signal CLKOUT is narrowed.

[0047] In other embodiments, if the intermediate clock signal CLK1 of the intermediate node coupled to the first regulation chain 12 and the second regulation chain 13 is in phase opposite to the initial clock signal CLKIN, the first regulation chain 12 is used to increase the duty cycle of the output clock signal CLKOUT.

[0048] Optionally, based on the above embodiment, in this embodiment, the bias voltage includes a first bias voltage and a second bias voltage. Figure 3 As shown, the second regulation link 13 includes a second transmission gate branch 131 and a charging branch 132. The second transmission gate branch 131 receives a detection signal and a second bias voltage, and is used to control the on or off of the charging branch 132 based on the detection signal and the second bias voltage; the charging branch 132 is coupled to the second transmission gate branch 131 and the intermediate node. In response to the charging branch 132 being turned on, the charging branch 132 performs a charging operation on the intermediate node to adjust the slope of the falling edge of the intermediate clock signal.

[0049] Alternatively, if Figure 3 As shown, the second transmission gate branch 131 of the present embodiment includes a second transmission gate TG2 and a fourth transistor M4, the input end of the second transmission gate TG2 receives the second bias voltage, the first control end of the second transmission gate TG2 receives the inverted detection signal, and the second control end of the second transmission gate TG2 receives the detection signal; the first pass end of the fourth transistor M4 receives the preset voltage, the second pass end of the fourth transistor M4 is coupled to the output end of the second transmission gate TG2 and the charging branch 132; the control end of the fourth transistor M4 receives the inverted detection signal; the charging branch 132 includes a fifth transistor M5 and a sixth transistor M6, the control end of the fifth transistor M5 is coupled to the output end of the second transmission gate TG2 and the second pass end of the fourth transistor M4, the first pass end of the fifth transistor M5 is coupled to the input end of the inverter unit 11 at the next stage of the intermediate node, the control end of the sixth transistor M6 is coupled to the output end of the inverter unit 11 at the next stage of the intermediate node, the first pass end of the sixth transistor M6 is coupled to the second pass end of the fifth transistor M5, and the second pass end of the sixth transistor M6 receives the preset voltage.

[0050] Among them, when the detection signal is at a low level, the second transmission gate TG2 is turned on and the fourth transistor M4 is turned off, the control end of the fifth transistor M5 receives the second bias voltage, the fifth transistor M5 and the sixth transistor M6 are turned on, and a corresponding pull-up current is generated between the fifth transistor M5 and the sixth transistor M6, and a charging operation is performed on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

[0051] Based on the above, if Figure 3 As shown, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 in the second regulation link 13 are all PMOS tubes, the intermediate clock signal CLK1 of the intermediate node coupled to the first regulation link 12 and the second regulation link 13 is in phase with the initial clock signal CLKIN, the first control end of the second transmission gate TG2 is the gate of the NMOS tube in the second transmission gate TG2; the second control end of the second transmission gate TG2 is the gate of the PMOS tube in the second transmission gate TG2. At this time, the second regulation link 13 is used to increase the duty cycle of the output clock signal CLKOUT based on the second bias voltage and the detection signal.

[0052] The working principle of the second regulation link 13 for increasing the duty cycle of the output clock signal CLKOUT is similar to that of the first regulation link 12, and the specific working principle is as follows:

[0053] The input terminal of the second transmission gate TG2 receives the second bias voltage, the first control terminal of the second transmission gate TG2 and the control terminal of the fourth transistor M4 receive the inverted detection signal VSELB, and the second control terminal of the second transmission gate TG2 receives the detection signal VSEL. If the detection signal output by the duty cycle detector 20 is at a low level, it means that the duty cycle of the output clock signal CLKOUT is less than 50%. At this time, the detection signal VSEL is at a low level, and the inverted detection signal VSELB is at a high level. At this time, the second transmission gate TG2 is turned on, the fourth transistor M4 is turned off, and the charging branch 132 is working. At this time, the second transmission gate TG2 transmits the second bias voltage to the control terminal of the fifth transistor M5. At this time, the fifth transistor M5 is in a conducting state.

[0054] In this embodiment, since the control terminal of the sixth transistor M6 is also coupled to the output terminal of the inverter unit 11 at the subsequent stage of the intermediate node, the control terminal of the sixth transistor M6 also receives the inverted intermediate clock signal CLK1B.

[0055] Similarly, when the intermediate clock signal CLK1 is at a falling edge, the inverted intermediate clock signal CLK1B is still at a low level. At this time, the fifth transistor M5 and the sixth transistor M6 are both in a conducting state. Since the second channel end of the sixth transistor M6 receives a preset voltage, as the voltage of the node corresponding to the intermediate clock signal CLK1 decreases, the fifth transistor M5 and the sixth transistor M6 generate a pull-up current I2, so that the node corresponding to the intermediate clock signal CLK1 slows down; when the intermediate clock signal CLK1 drops to the flip point of the inverter unit 11 after the intermediate node, the inverted intermediate clock signal CLK1B starts from low to high; when the inverted intermediate clock signal CLK1B rises to above the control terminal threshold voltage of the sixth transistor M6, the sixth transistor M6 is turned off, and I2 gradually decreases to 0; when I2=0, the intermediate clock signal CLK1 continues to be driven by the inverter unit 11 of the previous stage, and its voltage is quickly pulled down to the ground. After being shaped by the inverter unit 11 in the subsequent link, the duty cycle of the output clock signal CLKOUT is increased. It can be seen that during the adjustment process, the lower the second bias voltage is, the larger the pull-up current I2 is, the slower the falling speed of the intermediate clock signal CLK1 is, and the more the duty cycle of the output clock signal CLKOUT is increased.

[0056] In other embodiments, if the intermediate clock signal CLK1 of the intermediate node coupled to the first regulation chain 12 and the second regulation chain 13 is in anti-phase with the initial clock signal CLKIN, the second regulation chain 13 is used to narrow the duty cycle of the output clock signal CLKOUT.

[0057] Optionally, see Figure 5 , Figure 5 1 is a schematic diagram of the circuit structure of the first embodiment of the bias voltage generating module provided by the present application. Figure 5 As shown, the bias voltage generating module 40 of this embodiment includes a bias current generating module 401 and a current mirror module 402; the bias current generating module 401 includes a plurality of bias current branches connected in parallel, and based on the control code code <n:1>The number of bias current branches connected to the control is adjusted to generate a corresponding bias current; the current mirror module 402 is coupled to the bias current generating module 401 to generate a first bias voltage and a second bias voltage based on the bias current, wherein the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0058] Among them, in this embodiment, the first bias voltage and the second bias voltage generated by the current mirror module 402 can ensure that the pull-down current of the discharge branch 122 in the first regulation link 12 and the pull-up current of the charging branch 132 in the second regulation link 13 are the same, thereby ensuring that the first regulation link 12 and the second regulation link 13 have the same range of increase and narrowing of the duty cycle of the output clock signal CLKOUT.

[0059] Alternatively, if Figure 5 As shown, the current mirror module 402 of this embodiment includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a first capacitor C1; a first channel end of the seventh transistor M7 is connected to the output end of the bias current generating module 401 and coupled to the control end of the seventh transistor M7, a second channel end of the seventh transistor M7 is grounded, and the control end of the seventh transistor M7 is also used to output a first bias voltage; a control end of the eighth transistor M8 is connected to the control end of the seventh transistor M7, a first channel end of the eighth transistor M8 is connected to the second channel end of the ninth transistor M9, and the second channel end of the eighth transistor M8 is grounded; a first channel end of the ninth transistor M9 receives the first working voltage VCC1, a control end of the ninth transistor M9 is coupled to the second channel end of the ninth transistor M9, and is used to output a second bias voltage; a first end of the first capacitor C1 is grounded, and a second end of the first capacitor C1 is respectively coupled to the control end of the seventh transistor M7 and the control end of the eighth transistor M8.

[0060] In this embodiment, the seventh transistor M7 can be set as an NMOS tube, the first bias voltage is the gate voltage of the seventh transistor M7, the ninth transistor M9 can be set as a PMOS tube, and the second bias voltage is the gate voltage of the ninth transistor M9. In this embodiment, the voltages of the first bias voltage and the second bias voltage generated can be inconsistent.

[0061] Alternatively, if Figure 5 As shown, each bias current branch in the bias current generating module 401 of the present embodiment includes a tenth transistor MPn (n=1, 2, 3, ..., n) and a switch Tn (n=1, 2, 3, ..., n), the control end of the tenth transistor MPN receives the reference voltage Vref, and the first channel end of the tenth transistor MPn receives the second working voltage VCC2; the first end of the switch Tn is coupled to the second channel end of the tenth transistor MPn, the second end of the switch Tn is coupled to the bias current output module, and the control end of the switch Tn is used to receive the control code code <n:1>, based on the control code code <n:1>The control determines whether the corresponding bias current branch is turned on.

[0062] In this embodiment, the ratios of the sizes of the plurality of tenth transistors MPn included in the bias current branch are 1, 2, 4, 8 . . . 2^(N-1) in sequence, where N is the number of bias current branches, so that based on the control code code <n:1>The adjusted bias current is continuous with accuracy in the range of 0 to (2^N-1)*I0, where I0 is the bias current provided by the tenth transistor MPn of the unit size. The "tenth transistor MPn of the unit size" is, for example, Figure 5 MP1 in.

[0063] For example, Figure 5 As shown, the size of the tenth transistor MP1 is unit size, and the bias current it provides is I0, the size of the tenth transistor MP2 is 2*unit size, and the bias current it provides is 2I0, the size of the tenth transistor MP3 is 4*unit size, and the bias current it provides is 4I0... and so on, the size of the tenth transistor MP4 is 8*unit size, and the bias current it provides is 8I0... and so on, the size of the tenth transistor MPn is 2^(N-1)*unit size, and the bias current it provides is 2^(N-1)*I0. If the control code code <n:1>If the control code is all 0, the tenth transistor MPn is completely turned off and the bias current provided is 0; <n:1>are all 1, the tenth transistor MPn is fully turned on, and the bias current provided is the sum of N bias currents, that is, (2^N-1)*I0. That is to say, in this embodiment, by controlling the number of bias current branches that are turned on, the bias current can be accurately continuous in the range of 0, I0, 2I0, 3I0...(2^N-1)*I0, that is, the bias voltage is accurately continuous, so that the duty cycle of the clock signal can be accurately adjusted.

[0064] In other embodiments, when the control code code <n:1>When the temperature code format changes, the size of the tenth transistor MPn of each bias current branch in the above embodiment may also be the same, which is not limited here.

[0065] Optionally, see Figure 6 , Figure 6 Schematic diagram of the circuit structure of the second embodiment of the duty cycle adjustment circuit provided by the present application. Figure 6 As shown, in this embodiment, the bias voltage generating module 40 includes a first bias voltage generating module 41 and a second bias voltage generating module 42, wherein the first bias voltage generating module 41 is used to generate a first bias voltage, and the second bias voltage generating module 42 is used to generate a second bias voltage, wherein the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0066] In this example, see Figure 7 , Figure 7 is a schematic diagram of the structure of an embodiment of a first bias voltage generating module provided by the present application. Figure 7 As shown, the first bias voltage generating module 41 of this embodiment includes a bias current generating module 401 and a voltage generating submodule 411 .

[0067] The bias current generating module 401 includes a plurality of bias current branches connected in parallel and based on the control code code <n:1>The conduction quantity of the bias current branch is adjusted to generate a corresponding bias current; the bias voltage generating module 40 is coupled to the bias current generating module 401 to generate and output a bias voltage based on the bias current.

[0068] Among them, the bias current generating module 401 and Figure 5 The bias current generating module 401 in the embodiments is consistent and will not be described again.

[0069] like Figure 7 As shown, the voltage generating submodule 411 includes an eleventh transistor M11 and a second capacitor C2, wherein the first channel end of the eleventh transistor M11 is coupled to the output end of the bias current generating module 401 and the control end of the eleventh transistor M11 respectively; the second channel end of the eleventh transistor M11 is grounded; wherein the control end of the eleventh transistor M11 serves as the output end of the first bias voltage generating module 41 to output the first bias voltage; the first end of the second capacitor C2 is grounded, the second end of the second capacitor C2 is coupled to the control end of the eleventh transistor M11, and the second capacitor C2 is used to filter out the burrs in the first bias voltage generating module 41.

[0070] exist Figure 6 and Figure 7 In the embodiment, the size ratio of the tenth transistor MPm (n=1, 2, ... N) in the bias current branch can be set to conform to the binary weight. When the control terminal of the tenth transistor MPn receives the reference voltage Vref, the tenth transistor MPn is turned on. At this time, if the control code code <n:1>When the switch Tn of a branch is closed, a branch current will be generated on the branch based on the reference voltage Vref. <n:1>The number of bias current branches in the bias current generating module 401 that are turned on is controlled, thereby controlling the bias current generating module 401 to generate a corresponding bias current.

[0071] The structure of the second bias voltage generating module 42 can be similar to Figure 5 The structure of the bias voltage generating module 40 shown is the same, and it is only necessary to use the control end of the ninth transistor M9 in the current mirror module 402 as the output end of the second bias voltage generating module 42 to output the second bias voltage. In other embodiments, the second bias voltage generating module 42 can also be other circuit structures, and it is only necessary to satisfy that the generated second bias voltage is the same as the first bias voltage and the pull-down current or pull-up current of the intermediate node is the same, and no limitation is made here.

[0072] Optionally, the present application further proposes a memory, see Figure 8 , Figure 8 Schematic diagram of the structure of a memory device according to an embodiment of the present application. Figure 8 As shown, the memory 200 of this embodiment includes the duty cycle adjustment circuit 100 of any one of the above embodiments.

[0073] In this embodiment, the memory 200 may be a random access memory DRAM, a static random access memory SRAM or a pseudo static random access memory (Pseudo SRAM, PSRAM), which is not limited here.

[0074] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the description and drawings of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A duty cycle adjustment circuit, characterized in that: include: A duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; a duty cycle detector coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; a state machine coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; Wherein, the duty cycle adjustment link includes multiple inverter units connected in series, a first adjustment link and a second adjustment link, the first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link, and based on the control code and the detection signal, the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node is adjusted, thereby adjusting the duty cycle of the output clock signal, wherein the intermediate node is the connection point between the two inverter units.

2. The duty cycle adjustment circuit according to claim 1, characterized in that: Also includes: a bias voltage generating module, coupled to the state machine, the first regulating link and the second regulating link respectively, for generating a corresponding bias voltage based on the control code and providing the bias voltage to the first regulating link and the second regulating link; Among them, the first regulation link and the second regulation link adjust the pull-down current or pull-up current of the same intermediate node in the duty cycle regulation link based on the detection signal and the bias voltage, so as to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal.

3. The duty cycle adjustment circuit according to claim 2, characterized in that: The bias voltage includes a first bias voltage and a second bias voltage, The first regulation link includes a first transmission gate branch and a discharge branch, The first transmission gate branch receives the detection signal and the first bias voltage, and is used to control the on or off of the discharge branch based on the detection signal and the first bias voltage; The discharge branch is coupled to the first transmission gate branch and the intermediate node. In response to the discharge branch being turned on, the discharge branch performs a discharge operation on the intermediate node to adjust the slope of the rising edge of the intermediate clock signal.

4. The duty cycle adjustment circuit according to claim 3, characterized in that: The second regulation link includes a second transmission gate branch and a charging branch, The second transmission gate branch receives the detection signal and the second bias voltage, and is used to control the on or off of the charging branch based on the detection signal and the second bias voltage; The charging branch is coupled to the second transmission gate branch and the intermediate node. In response to the charging branch being turned on, the charging branch performs a charging operation on the intermediate node to adjust the slope of the falling edge of the intermediate clock signal.

5. The duty cycle adjustment circuit according to claim 3, characterized in that: The first transmission gate branch comprises: a first transmission gate, wherein an input terminal of the first transmission gate receives the first bias voltage, a first control terminal of the first transmission gate receives the detection signal, and a second control terminal of the first transmission gate receives an inverted detection signal; a first transistor, wherein a first channel end of the first transistor is grounded, a second channel end of the first transistor is coupled to an output end of the first transmission gate and the discharge branch; and a control end of the first transistor receives the inverted detection signal; The discharge branch comprises: a second transistor, wherein a control terminal of the second transistor is coupled to an output terminal of the first transmission gate and a second path terminal of the first transistor, and a first path terminal of the second transistor is coupled to an input terminal of the inverter unit at a stage after the intermediate node, a third transistor, wherein a control terminal of the third transistor is coupled to an output terminal of the inverter unit at a stage after the intermediate node, a first channel terminal of the third transistor is coupled to a second channel terminal of the second transistor, and a second channel terminal of the third transistor is grounded; When the detection signal is at a high level, the first transmission gate is turned on and the first transistor is turned off, the control end of the second transistor receives the first bias voltage, the second transistor and the third transistor are turned on, a corresponding pull-down current is generated between the second transistor and the third transistor, and a discharge operation is performed on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

6. The duty cycle adjustment circuit according to claim 4, characterized in that: The second transmission gate branch comprises: a second transmission gate, wherein an input terminal of the second transmission gate receives the second bias voltage, a first control terminal of the second transmission gate receives the inverted detection signal, and a second control terminal of the second transmission gate receives the detection signal; a fourth transistor, wherein a first channel terminal of the fourth transistor receives a preset voltage, a second channel terminal of the fourth transistor is coupled to the output terminal of the second transmission gate and the charging branch; and a control terminal of the fourth transistor receives the inverted detection signal; The charging branch comprises: a fifth transistor, wherein a control terminal of the fifth transistor is coupled to the output terminal of the second transmission gate and the second channel terminal of the fourth transistor, and a first channel terminal of the fifth transistor is coupled to an input terminal of the inverter unit at a stage after the intermediate node, a sixth transistor, wherein a control terminal of the sixth transistor is coupled to an output terminal of the inverter unit at a stage after the intermediate node, a first channel terminal of the sixth transistor is coupled to a second channel terminal of the fifth transistor, and a second channel terminal of the sixth transistor receives the preset voltage; When the detection signal is at a low level, the second transmission gate is turned on and the fourth transistor is turned off, the control end of the fifth transistor receives the second bias voltage, the fifth transistor and the sixth transistor are turned on, a corresponding pull-up current is generated between the fifth transistor and the sixth transistor, and a charging operation is performed on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

7. The duty cycle adjustment circuit according to claim 3, characterized in that: In response to the intermediate clock signal being in phase with the initial clock signal, the first regulation link is used to narrow the duty cycle of the output clock signal based on the first bias voltage and the detection signal; The second regulation link is used to increase the duty cycle of the output clock signal based on the second bias voltage and the detection signal; In response to the intermediate clock signal being in phase opposition with the initial clock signal, the first regulation link is used to increase a duty cycle of the output clock signal based on the first bias voltage and the detection signal; The second regulation link is used to narrow the duty cycle of the output clock signal based on the second bias voltage and the detection signal.

8. The duty cycle adjustment circuit according to claim 2, characterized in that: The bias voltage generating module includes a bias current generating module and a current mirror module; The bias current generating module includes a plurality of bias current branches connected in parallel, and adjusts the number of the bias current branches connected based on the control code to generate a corresponding bias current; the current mirror module is coupled to the bias current generating module to generate a first bias voltage and a second bias voltage based on the bias current, and the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

9. The duty cycle adjustment circuit according to claim 8, characterized in that: The current mirror module includes a seventh transistor, an eighth transistor, a ninth transistor and a first capacitor; The first channel end of the seventh transistor is connected to the output end of the bias current generating module and coupled to the control end of the seventh transistor, the second channel end of the seventh transistor is grounded, and the control end of the seventh transistor is also used to output the first bias voltage; The control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, the first channel terminal of the eighth transistor is connected to the second channel terminal of the ninth transistor, and the second channel terminal of the eighth transistor is grounded; The first channel end of the ninth transistor receives the first working voltage, and the control end of the ninth transistor is coupled to the second channel end of the ninth transistor and is used to output the second bias voltage; A first terminal of the first capacitor is grounded, and a second terminal of the first capacitor is coupled to a control terminal of the seventh transistor and a control terminal of the eighth transistor respectively.

10. The duty cycle adjustment circuit according to claim 8, characterized in that: Each of the bias current branches in the bias current generating module comprises: a tenth transistor, wherein a control terminal of the tenth transistor receives a reference voltage, and a first channel terminal of the tenth transistor receives a second operating voltage; A switch, wherein a first end of the switch is coupled to the second path end of the tenth transistor, a second end of the switch is coupled to the bias current output module, and a control end of the switch is used to receive the control code to determine whether the corresponding bias current branch is turned on based on the control of the control code.

11. The duty cycle adjustment circuit according to claim 2, characterized in that: The bias voltage generating module includes a first bias voltage generating module and a second bias voltage generating module. The first bias voltage generating module is used to generate a first bias voltage, and the second bias voltage generating module is used to generate a second bias voltage. The first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

12. A memory, characterized in that: The invention comprises the duty cycle adjustment circuit as described in any one of claims 1 to 11.

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