Digital-to-analog converter circuitry

Abstract

The invention discloses digital-to-analog converter circuitry. In described examples, a circuit (100) includes a digital-to-analog converter (DAC) cell element switch circuit (120) including first and second symbol switch inputs, first and second select switch inputs, and first, second, and third DAC outputs. Synchronizer logic (122) includes a select input and first and second sync outputs, where the first sync output is coupled to the first select switch input and the second sync output is coupled to the second select switch input. Selection logic (106) includes a data input, a symbol control output, and a selection control output, where the symbol control output is coupled to the first and second symbol switch inputs, and the selection control output is coupled to the selection input.

Description

[0001] Related Applications

[0002] This application claims priority to Indian Provisional Patent Application Serial No. 202341048847 filed on July 20, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present description relates to digital-to-analog converters and systems including digital-to-analog converters. Background Art

[0004] A digital-to-analog converter (DAC) is a device that converts a digital signal into an analog signal. A DAC can be viewed as an enabling technology or building block that finds application in many technologies such as audio, video, and communications (to name a few). As an example, a delta-sigma modulator analog-to-digital converter may include a multi-bit DAC as part of a feedback loop. A multi-bit DAC includes several DAC unit elements that transition between states in response to a digital input signal. When there are errors or mismatches in the transitions being made, the errors may result in the nature of inter-symbol interference between the unit elements. Inter-symbol interference may produce nonlinearities, which in turn may result in harmonic distortion and ultimately deteriorate the dynamic range of the circuit system. Summary of the invention

[0005] In the described example, a circuit includes a digital-to-analog converter (DAC) unit element switch circuit, the DAC unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second, and third DAC outputs. Synchronizer logic includes a select input and first and second synchronization outputs, wherein the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. The selection logic includes a data input, a sign control output, and a select control output, wherein the sign control output is coupled to the first and second sign switch inputs, and the select control output is coupled to the select input.

[0006] In another described example, a circuit includes a plurality of digital-to-analog converter (DAC) unit elements. Each DAC unit element includes a unit element switch circuit, a synchronizer logic, and a sign logic. The unit element switch circuit of each unit element is configured to provide one of three values ​​in response to first and second sign output signals and first and second synchronization output signals. The synchronizer logic of each unit element is configured to provide first and second synchronization output signals in response to a selection signal. The sign logic of each unit element is configured to provide first and second sign output signals in response to a sign control signal. The selection logic is configured to divide a plurality of unit elements into a first section and a second section, and provide a selection signal and a sign control signal to route input data to at least one DAC unit element of a given section in the first section and the second section, thereby preventing continuous overlapping transitions.

[0007] In a further described example, a device includes a digital interface, the digital interface including a digital input and a digital output. A digital filter includes a filter input and a filter output, wherein the filter input is coupled to the digital output. The selection logic includes a data input, a selection output, and a symbol output, wherein the data input is coupled to the filter output. The synchronizer logic circuit includes a selection input, a clock input, and first and second synchronization outputs, wherein the selection input is coupled to the selection output. The symbol logic circuit includes a symbol input and first and second symbol control outputs, wherein the symbol input is coupled to the symbol output. The device also includes a digital-to-analog converter (DAC) unit element switch circuit, the DAC unit element switch circuit including first and second symbol switch inputs, first and second selection switch inputs, and a DAC output. The first selection switch input is coupled to the first synchronization output, and the second selection switch input is coupled to the second synchronization output. The first symbol switch input is coupled to the first symbol control output, and the second symbol switch input is coupled to the second symbol control output. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example DAC circuit.

[0009] Figure 2 is a block diagram of example unit cell circuitry that may be implemented in a DAC circuit.

[0010] Figure 3 is a circuit diagram showing an example DAC unit cell element.

[0011] Figure 4 is a circuit diagram illustrating another example DAC unit cell element.

[0012] Figure 5 is a flow chart illustrating an example method for controlling a DAC.

[0013] Figure 6 It shows that according to Figure 5 The method is a diagram of an example of a selection vector generated to place data in a DAC unit element.

[0014] Figure 7 is a graph illustrating the spectral output provided by an example modulator circuit.

[0015] Figure 8 is a graph showing a comparison of spectral outputs provided by different modulator circuits.

[0016] Fig. 9 is a block diagram illustrating an example DAC circuit.

[0017] Fig.10 is a block diagram illustrating an example modulator circuit including a DAC. DETAILED DESCRIPTION

[0018] The present description relates to digital-to-analog converters and systems including digital-to-analog converters.

[0019] As an example, a circuit includes one or more digital-to-analog converter (DAC) unit elements (UE). Each UE includes a UE switch circuit and a synchronizer logic. Each UE may also include a symbol logic. Each UE switch circuit may include a network of parallel switch paths, wherein each switch path provides a different output state (e.g., current and / or voltage value) at the corresponding path output terminal of the UE. For example, each UE switch circuit provides one of three (or more) different output values, such as 3 values ​​(e.g., +1, 0, and -1) representing the corresponding output state. A given switch path in the switch path thus provides an output value at its corresponding path output terminal in response to a symbol output signal and a synchronization output signal. The synchronizer logic provides a synchronization output signal in response to a selection signal, and the symbol logic provides a symbol output signal in response to a symbol control signal.

[0020] The circuit also includes a selection logic configured to divide a plurality of UEs into a first segment and a second segment of the UE, and provide a selection signal and a symbol control signal to control the routing of input data to one or more UEs in a selected segment in the first segment and the second segment of the UE. As described herein, the selection logic selects one of the segments of the UE for routing the input data to avoid continuous overlapping transitions. Overlap transitions refer to state transitions of corresponding UEs involving symbol changes, such as from +1 to -1 or from -1 to +1. Therefore, the selection logic can constrain the state transitions of the UE to include 0 to +1, 0 to -1, +1 to 0, and -1 to 0. Additionally or alternatively, the selection logic can provide a selection signal as a selection vector to control the output values ​​provided by several UEs in one or more UEs of the selected segment based on the input data (e.g., a digital input value). Advantageously, in response to the corresponding selection signal and the symbol control signal provided to each corresponding UE, only a single synchronizer can be used for each UE to synchronize the transitions of each UE. Improved synchronization between transitions may result in reduced noise (eg, inter-symbol interference) at the DAC output, which may improve dynamic range.

[0021] Figure 1 1 is a block diagram showing an example DAC circuit (also referred to as a DAC) 100 having a digital input 102 and an analog output 104. As an example, the DAC 100 may be implemented on an integrated circuit (IC) or as part of an IC. The DAC 100 includes a selection logic 106 and a unit element (UE) circuit system 112. The selection logic 106 has an input coupled to the digital input 102. The selection logic 106 also has a number N of selection control outputs 108 and N sign control outputs 110, where N is a positive integer representing the number of UEs implemented in the DAC UE circuit system 112. The UE circuit system 112 has N selection inputs 114 and N sign inputs 116, which are coupled to the corresponding selection control outputs 108 and sign control outputs 110 (e.g., through corresponding control lines). The selection logic 106 may provide a selection signal at 108 and a sign control signal at 110 based on the value of the input data received at 102 (e.g., a digital value). UE circuitry 112 may provide analog output signals at 104 representing values ​​of input data based on routing of the input data (eg, bits) to corresponding UEs 118 according to selection signals and sign control signals received at 114 and 116, respectively.

[0022] As described herein, the UE circuitry 112 includes a number N of UEs 118, one of which is Figure 1. Each UE 118 can be a one-bit DAC configured to convert a corresponding one-bit input (e.g., encoded by the selection logic 106) to the analog domain. In the example described herein, the DAC 100 is a Class B DAC, and each UE 118 can be a tri-state (or three-level) unit element configured to provide one of at least three different output values ​​having different levels, such as a positive voltage, a negative voltage, and a midpoint or common mode voltage (e.g., reference voltages P, CM, and M). The outputs of the individual DAC UEs 118 can be combined to produce one or more analog output signals at 104 that represent the original digital signal at 102.

[0023] like Figure 1 As shown, each UE 118 may include a UE switch circuit 120, a synchronizer logic (also referred to as a synchronizer) 122, and a symbol logic 124. Each symbol logic 124 may provide a pair of opposite symbol signals at the corresponding first and second symbol output terminals in response to a symbol input signal at the symbol input terminal 116 (such as a symbol representing a number provided to the corresponding UE 118). Each synchronizer logic 122 may provide a pair of synchronization selection signals at the first and second synchronization output terminals, wherein the first and second synchronization selection signals are inverted versions of each other in response to the selection signal at the selection input terminal 114 of the corresponding UE 118. Each UE switch circuit 120 may provide a corresponding UE output signal having a value (e.g., state) depending on the synchronization selection signal and the symbol signal of the corresponding UE 118. The UE switch circuit 120 may include a unit current source, a unit resistor or a unit capacitor circuit, or a combination thereof. Other types of DAC UEs may be used in other examples. The UE output signals are combined to generate an analog output signal at 104.

[0024] As described herein, the selection logic 106 can control the transitions between the states of each UE 118 to avoid continuous overlapping transitions (e.g., continuous sign changes in the UE output state). For example, the selection logic 106 divides the DAC UE 118 into two sections, such as each section having half the number of UEs. The selection logic 106 can further be configured to use a pair of independent pointers to track the positive input values ​​and negative input values ​​of each section of the UE (e.g., a total of four pointers-two pointers for each section). The selection logic 106 can further be configured to use a pair of usage variables to track the corresponding positive data values ​​and negative data values ​​of the section usage (e.g., a total of four usage variables-two usage variables for each section in the section). The selection logic 106 provides a selection signal at 108 to control the UE circuit system by providing a selection vector, which is suitable for routing a data bit to one or more UEs in the appropriate section, which avoids overlapping transitions (e.g., transitions between -1 and +1). Thus, each unit element has only 4 transitions of interest (e.g., transitions between 0 and + / -1) in response to the select signal and the sign signal, which can be synchronized using a synchronous SEL bit and an asynchronous SIGN bit as described herein. By preventing (or reducing) overlapping transitions of the UE, noise (e.g., due to inter-signal interference) can be reduced. In addition, each UE 118 can be implemented with a single synchronizer, as compared to existing approaches that tend to require more than one synchronizer. Therefore, the UE circuit system can be implemented on a given IC using a smaller area and with reduced power requirements than many existing approaches.

[0025] Figure 2 2 is a block diagram of an example UE circuit system 200 that may be implemented in a DAC circuit such as the circuit described herein. Figure 1 An example of UE circuit system 112 is described. Therefore, Figure 2 The description also refers to Figure 1 UE circuit system 200 includes multiple UEs 202, as shown by UE 1 to UE N. Each UE 202 includes a clock input terminal (CLK) 204, a selection input terminal (SEL[i]) 206, and a symbol input terminal (SIGN[i]) 208, where i is a positive integer (i=1 to N) identifying the corresponding UE. Each UE 202 also has corresponding output terminals 210, 212, and 214, wherein the UE is configured to provide a UE output signal with a different level (state) at each corresponding output terminal. Figure 2In the example of , the output terminals 210, 212, and 214 of each UE 202 are each coupled (e.g., shorted) together to provide a combined analog output, such as a positive voltage, a negative voltage, and a common mode voltage (shown as P, CM, and M) at each of the corresponding UE output terminals. As described herein, each UE 202 may include a UE switch circuit (e.g., UE switch circuit 120), a synchronizer logic (e.g., synchronizer logic 122), and a symbol logic (e.g., symbol logic 124), which is configured to provide analog UE output signals P, CM, and M at the corresponding output terminals 210, 212, and 214.

[0026] Figure 3 is a circuit diagram showing an example DAC UE 300. The UE 300 is about Figure 1 and Figure 2 The example of UE 118 and 202 described above. Figure 3 The description also refers to Figure 1 and Figure 2 Thus, the DAC circuit may include multiple instances of UE 300.

[0027] UE 300 includes UE switch circuitry 302, synchronizer logic 304, and symbol logic 306. Symbol logic 306 may be implemented as digital logic having a symbol input 308 and a pair of symbol outputs 310 and 312. Figure 3 In the example of , the sign logic 306 includes a digital buffer 314 coupled between a sign input 308 and a sign output 310, and an inverter 316 coupled between the sign input 308 and the sign output 312. The sign input 308 can be coupled to a sign control output of a selection logic (e.g., the selection logic 106). Thus, in response to a sign control signal (e.g., a one-bit logic signal) at the sign input 308 (e.g., provided by the selection logic 106), the sign logic 306 provides sign logic signals having opposite logic values ​​at the corresponding sign outputs 310 and 312.

[0028] Synchronizer logic 304 may be implemented as digital logic having a select input 318, a clock input 320, and synchronization outputs 322 and 324. Figure 3In the example of , synchronizer logic 304 includes buffer 326, buffer 334, inverters 332, 336 and 338, and transistors 328 and 330. Buffer 326 has an input coupled to clock input 320 and an output coupled to control inputs (e.g., gates) of transistors 328 and 330. Inverter 332 has an input coupled to select input 318 and an output coupled to a first current input (e.g., source) of transistor 328. The current input of a transistor may also be referred to as a terminal, and the control input of a transistor may also be referred to as a control terminal. Buffer 334 has an input coupled to select input 318 and an output coupled to a first current input (e.g., source) of transistor 330. Thus, inverter 332 and buffer 334 are configured to provide opposite logic signals to corresponding transistor inputs in response to the select logic signal at 318, and the clock signal at 320 is used to control transistors 328 and 330 (e.g., turn them on and off) in response to the clock signal. The synchronization output 322 is coupled to the second current input (e.g., drain) of transistor 328, and the synchronization output 324 is coupled to the second current input (e.g., drain) of transistor 330. The pair of inverters 336 and 338 are coupled in anti-parallel between the respective second current inputs (e.g., drains) of transistors 328 and 330. The synchronizer logic 304 can provide first and second synchronization select signals at the synchronization outputs 322 and 324 in response to the select signal at 318 and the clock signal at 320. Inverters 336 and 338 are therefore configured to ensure that the first and second synchronization select signals at 322 and 324 remain synchronized and are inverted versions of each other.

[0029] UE switch circuit 302 includes UE output switch paths, each path coupled between power supply terminal 340 and a corresponding UE output terminal 342, 344 and 346. The UE output switch path includes switches 348, 350, 352, 356 and 358. Figure 3 In the example of , the power terminal can be coupled to a power supply configured to provide a power supply voltage (shown as VDD). A current source (or other circuitry, such as a resistor) 341 can be coupled between the power terminal 340 and the input of each switch path configured to provide current to the corresponding switch path.

[0030] Each switch path may include two or more switches coupled between the power supply terminal 340 and the corresponding DAC output. The first switch path includes switches 348 and 350 coupled between the current source 341 and the UE output 342. Switch 348 has a control input coupled to the first sign switch output 310, and switch 350 has a control input coupled to the synchronization output 322. The second switch path includes switches 352 and 354 coupled between the current source 341 and the UE output 344. Switch 356 has a control input coupled to the switch output 312, and switch 358 has a control input coupled to the synchronization output 322. The third switch path includes switches 356 and 358 coupled between the current source 341 and the UE output 346. Switch 352 has a control input coupled to a fixed voltage (e.g., VDD) to keep it turned on, and another switch 354 has a control input coupled to the synchronization output 324. Switches 348 to 358 may be implemented as identical switches (eg, transistors), and a normally-on switch 352 may be provided so that each of the switch paths has the same resistance. Other circuitry may be used to provide a common resistance and appropriate switching between switch paths.

[0031] The UE switch circuit 302 may provide a UE output signal having a corresponding value of P, CM, or M at one of the respective output terminals 342, 344, 346 in response to the synchronization selection signals at 322 and 324 and the sign signals at 310 and 312. As described herein, the UE switch circuit 302 is controlled (e.g., by the selection logic 106) to avoid consecutive overlapping transitions at the output terminals 342, 344, and 346.

[0032] Figure 4 4 is a circuit diagram showing another example DAC UE 400, wherein the UE elements are configured to provide a differential analog output signal. Figure 1 and Figure 2 Examples of UE 118 and 202 are described and are Figure 3 400 includes UE switch circuit 402, synchronizer logic 404 and symbol logic 406. Figure 4 In the example of FIG. 1 , the synchronizer logic 404 and the symbol logic 406 may be implemented as follows: Figure 3 The same logic circuit shown in Figure 3 Compared with the single-ended UE switch circuit 302, the UE switch circuit 402 is a differential circuit. Therefore, Figure 4 The description also refers to Figure 1 , Figure 2 and Figure 3 .

[0033] exist Figure 4 In the example of , the sign logic 406 includes a digital buffer 414 coupled between a sign input 408 and a sign output 410, and an inverter 416 coupled between the sign input 408 and the sign output 412. The sign input 408 can be coupled to a sign control output of a selection logic (e.g., the selection logic 106). The synchronizer logic 404 can be implemented as a digital logic having a selection input 418, a clock input 420, and synchronization outputs 422 and 424. The synchronizer logic 404 includes a buffer 426, a buffer 434, inverters 432, 436, and 438, and transistors 428 and 430. The buffer 426 has an input coupled to the clock input 420 and an output coupled to the control inputs (e.g., gates) of the transistors 428 and 430. The inverter 432 has an input coupled to the selection input 418 and an output coupled to the first current input (e.g., source) of the transistor 428. Buffer 434 has an input coupled to select input 418 and an output coupled to a first current input (e.g., source) of transistor 430. Synchronous output 422 is coupled to a second current input (e.g., drain) of transistor 428, and synchronous output 424 is coupled to a second current input (e.g., drain) of transistor 430. A pair of inverters 436 and 438 are coupled in anti-parallel between respective second current inputs (e.g., drains) of transistors 428 and 430. Synchronizer logic 404 may provide first and second synchronous select signals at synchronous outputs 422 and 424 in response to a select signal at 418 and a clock signal at 420.

[0034] UE switch circuit 402 includes differential UE output switch paths. A first group (e.g., positive) switch paths are coupled between power supply terminal 440 and corresponding UE output terminals 444, 446, and 448. The first group of switch paths includes switches 454, 456, 458, 460, 462, and 464. A current source (or other circuit system, such as a resistor, a capacitor, and / or other unit element circuit system) 442 can be coupled between power supply terminal 440 (e.g., coupled to VDD) and the input of each switch path configured to provide current to the corresponding switch path. A second group (e.g., negative) switch path is coupled between ground terminal 450 and a corresponding one of UE output terminals 444, 446, and 448. A second group of switch paths includes switches 466, 468, 470, 472, 474, and 476. Another current source (or other circuit system, such as a resistor) 452 can be coupled between ground terminal 440 and the input of each switch path configured to provide current to the corresponding switch path. Each positive switch path may include two or more switches coupled between a power supply terminal 440 and a corresponding DAC output 444 , 446 , 448 , and each negative switch path may include two or more switches coupled between a ground terminal 450 and a corresponding DAC output.

[0035] The first positive switch path includes switches 454 and 456 coupled between the current source 442 and the UE output 444. Switch 454 has a control input coupled to the first sign switch output 410, and switch 456 has a control input coupled to the synchronization output 422. The second positive switch path includes switches 458 and 460 coupled between the current source 442 and the UE output 448. Switch 458 has a control input coupled to the sign output 412, and switch 460 has a control input coupled to the synchronization output 422. The third positive switch path includes switches 462 and 464 coupled between the current source 442 and the UE output 446. Switch 462 has a control input coupled to a fixed voltage (e.g., VDD), and another switch 464 has a control input coupled to the synchronization output 424.

[0036] The first negative switch path includes switches 466 and 468 coupled between the current source 452 and the UE output 444. Switch 466 has a control input coupled to the second sign switch output 412, and switch 468 has a control input coupled to the synchronization output 422. The second negative switch path includes switches 470 and 472 coupled between the current source 452 and the UE output 448. Switch 470 has a control input coupled to the sign output 412, and switch 472 has a control input coupled to the synchronization output 422. The third negative switch path includes switches 474 and 476 coupled between the current source 442 and the UE output 446. Switch 474 has a control input coupled to a fixed voltage (e.g., VDD), and another switch 476 has a control input coupled to the synchronization output 424.

[0037] The UE switch circuit 402 may provide differential analog UE output signals (e.g., P, CM, and M) at 444, 446, and 448, wherein the P signal and the M signal across 444 and 448 provide a differential positive or negative signal, and the CM signal at 446 provides a midpoint (common mode) signal. As described herein, the UE switch circuit 402 is controlled (e.g., by the selection logic 106) to avoid consecutive overlapping transitions in the UE output signals provided at the outputs 442, 444, and 446.

[0038] Figure 5 5 is a flow chart illustrating an example method 500 for controlling a DAC. The method 500 is an example of functions that the selection logic 106 may be configured to perform for controlling the UE circuitry 112 and 200 and its UE, such as with respect to Figure 1 , Figure 2 , Figure 3 and Figure 4 Therefore, Figure 5 The description also refers to Figure 1 , Figure 2 , Figure 3 and Figure 4 . Although for ease of explanation, method 500 is shown and described as being performed serially, such method is not limited by the order shown. Some actions may occur in an order different from that shown and / or occur simultaneously. In addition, not all of the blocks shown are required to implement method 500. The method may be implemented by hardware (e.g., logic circuitry and memory in an IC, a field programmable gate array (FPGA), and / or discrete components within an IC), firmware and / or software (e.g., machine-readable instructions stored in a non-temporary medium and executed by a processor or controller), or a combination of hardware and software.

[0039] The method begins at 502, such as when an IC or other type of device including a DAC configured to perform is powered on. As described herein, the DAC includes a number N of unit elements. The DAC also has an input terminal at which input data (e.g., a digital value V) is received. At 504, the UE is divided into corresponding segments of the UE. The segments of the UE may be referred to as segments X and Y. In one example, each of segments X and Y includes N / 2 UEs. In addition, at 504, the input data V is divided into two parts A and B. In some examples, where the input data V has a number of bits |V|=<N / 2, A=V and B=0, all input data is kept together. In other examples, segment A=sign(V)*N / 2, and segment B=VA.

[0040] As a further example, as part of method 500, selection logic (e.g., selection logic 106) may use several pointers to track positive and negative numbers for each segment X and Y (e.g., four pointers total). Thus, the selection logic uses pointers to track positive and negative numbers used by such pointers. For example, PTRPX is a positive pointer for segment X, PTRMX is a negative pointer for segment X, PTRPY is a positive pointer for segment Y, and PTRMY is a negative pointer for segment Y. The selection logic may also implement usage variables that each track positive and negative input data values ​​used by such variables. UXP is the sum of positive values ​​used by segment X, UXM is the sum of negative values ​​through segment X, UYP is the sum of positive values ​​used by segment Y, and UYM is the sum of negative values ​​through segment Y. Similar for UYP and UYM. The pointers and variables may be stored in a memory (e.g., a register, such as a flip-flop) and updated by the selection logic when the value of the input data is converted from the analog domain to the digital domain by the selected UE.

[0041] At 506, a selection vector is constructed. For example, two selection vectors (SV1 and SV2) are constructed to provide respective options that can be used (e.g., by selection logic) to control in which UE segment (X or Y) the input data is provided. A first selection vector SV1 may be provided, in which a portion A of the input signal is assigned to segment X, and a portion B is assigned to segment Y (e.g., A->X and B->Y). A second selection vector SV2 may be provided, in which a portion A of the input signal is assigned to segment Y, and a portion B is assigned to segment X (e.g., A->Y and B->X). Thus, when a given selection vector is selected, bits of the input data V are provided to UEs in one or more segments according to the selected given selection vector.

[0042] At 508, it is determined whether there is a sign change between the current input data V(n) and the previous instance V(n-1) of the input data, where n represents the current instance and n-1. In one example, the sign change is calculated by determining that V(n)*V(n-1)<0. If the determination at 508 is negative, indicating that there is no sign change (e.g., no overlapping transitions), the method proceeds to 510. At 510, the usage score values ​​(e.g., USAGE_X and USAGE_Y) for each of the segments X and Y are evaluated. For example, the usage variables USAGE_X and USAGE_Y store values ​​to track the usage of each segment X and Y based on the number of bits of input data received over time in each corresponding segment. The usage variables USAGE_X and USAGE_Y can track positive and negative values ​​(e.g., USAGE_X=UXP+UXM and USAGE_Y=UYP+UYM). Each usage variable may be updated in each iteration of method 500 and may vary depending on which selection vector option is selected, as described herein (at 512 and 514). At 510, if USAGE_X <= USAGE_Y, the method proceeds to 512. At 512, the method selects selection vector option SV1 and updates the relevant usage variables for the selected segment (e.g., usage of segments X and / or Y) based on the input value V(n). For example, at 512, the usage variables for segments X and Y may be updated as follows:

[0043] USAGE_X(n)=USAGE_X(n-1)+|A|

[0044] USAGE_Y(n)=USAGE_Y(n-1)+|B|

[0045] Where: n represents the current cycle;

[0046] n-1 represents the previous cycle;

[0047] |A| represents the number of bits of the current input data V(n) in part A; and

[0048] |B| represents the number of bits of the current input data V(n) in part B.

[0049] At 510, if USAGE_X>USAGE_Y, the method proceeds to 514. At 514, the method selects selection vector SV2 and updates the relevant usage variables of the selected segment (e.g., usage of segments X and Y) based on the input value V(n). For example, at 514, the usage of the variables of segments X and Y may be updated as follows:

[0050] USAGE_X(n)=USAGE_X(n-1)+|B|; and

[0051] USAGE_Y(n)=USAGE_Y(n-1)+|A|.

[0052] In response to the determination at 508 being positive, indicating the occurrence of a sign change (e.g., an overlap transition), the method proceeds from 508 to 516. At 516, an overlap score is calculated for each of the selection vectors (e.g., SV1 and SV2) constructed at 506. For example, if there is a data sign change, the overlap is calculated (at 506) by performing a bitwise AND operation on SV(n-1) with each of the selection vectors SV1 and SV2 determined for the current input value to provide corresponding overlap values ​​(e.g., OVERLAP1 and OVERLAP2) for the corresponding selection vector options SV1 and SV2. At 518, it is determined whether the overlaps are equal (e.g., OVERLAP1=OVERLAP2). If the determination at 518 is positive, indicating that the overlaps are equal, the method proceeds to 510 to select the selection vector option based on the segment usage, such as described herein. If the determination at 518 is negative, indicating that the overlaps are not equal, the method proceeds to 520. At 520, a determination is made as to whether the overlap of SV1 is less than the overlap of SV2 (e.g., OVERLAP1 < OVERLAP2). If the determination at 520 is negative, indicating that OVERLAP1 is not less than OVERLAP2, the method proceeds to 514 to select SV2 and update the usage variable accordingly. If the determination at 520 is positive, indicating that OVERLAP1 is less than OVERLAP2, the method proceeds to 512 to select SV1 and update the usage variable accordingly. The method 500 may be implemented for each digital input value.

[0053] As a further example, Figure 6 It shows that according to Figure 5 600 is a diagram of an example of a selection vector generated by the method for placement of a series of input data received over time. Figure 6 The description also refers to Figure 5 .exist Figure 6 In the example of 600, the DAC includes 16 UEs (e.g., numbered 0 to 15 in the leftmost column of the diagram 600). The UEs are shown divided into segments X and Y, where segment X includes UEs 0 to 7 and segment Y includes UEs 8 to 15. The diagram 600 also includes input values ​​(e.g., 2, 3, -4, -5, 3, -2, 4, 5, -3, 0, and 1) shown at 606, which are received by the DAC over time. Therefore, the method 500 is implemented to place bits / positions of -1, 0, and 1 in a selected UE in one of the segments X or Y according to the corresponding input values ​​for each clock cycle.

[0054] like Figure 6 As shown, UE coverage is improved compared to existing methods, at least in part because there are separate pointers for positive and negative values ​​for each segment as described herein. In addition, method 500 causes no overlap between consecutive vectors of opposite signs. For example, as shown at 610, method 500 selects segment Y instead of segment X's selection vector for the transition from 3 to -2. It can be shown that as long as the data during the sign transition is less than half the number of unit elements (which is true in the case of a multi-bit modulator), method 500 can ensure a non-overlapping solution. In addition, as described herein, because of the dual pointers for positive and negative values, improved usage averaging can be achieved by the UE.

[0055] Figure 7 7 is a graph 700 illustrating a spectral output 702 over a frequency range (eg, bins) provided by an example modulator circuit implementing a DAC as described herein. Figure 7 The spectrum output 702 for a -60 dBFS input is shown in FIG. As shown, the modulator exhibits low noise, such as evidenced by the absence of a tone in frequency.

[0056] Figure 8 8 is a graph 800 showing a comparison of spectral outputs 802, 804, 806, and 808 provided by different modulator circuits. Graph 802 is provided by a modulator implementing a DAC as described herein, and graph 804 represents a simulated spectral output of an ideal modulator. Figure 8 As shown, graph 802 exhibits performance comparable to an ideal modulator. In contrast, graphs 806 and 808, which are spectral outputs of modulators implementing two different prior art DACs, exhibit significantly lower performance. The improved performance associated with graph 802 is due to reduced inter-mark interference that occurs because the DAC can transition between 0 and + / -1 while avoiding overlapping transitions with sign changes (e.g., between -1 and +1).

[0057] Fig. 9 is a block diagram illustrating an example DAC circuit 900. The DAC circuit 900 may be implemented on an IC or as part of an IC. The DAC circuit 900 includes a digital input 902 and one or more analog outputs 904 and 906 (e.g., differential outputs). The circuit 900 includes a DAC 908, a digital interface 910, one or more digital filters 912, and analog support circuitry 922, which are coupled between the input 902 and the outputs 904 and 906. As described herein, the DAC 908 includes selection logic 914 and UE circuitry 920, which includes a number of UEs. For example, the selection logic 914 may be implemented by the selection logic 106, which may be configured to perform Figure 5 UE circuitry 920 may be implemented by UE circuitry 112 and 200 and thus include several UEs, such as any of UEs 118, 202, 300, and / or 400. Thus, each instance of a UE of UE circuitry 920 thus includes UE switch circuitry 924, synchronizer logic 926, and symbol logic 928.

[0058] For example, the digital interface 910 has one or more input terminals coupled to the digital input terminal 902, and thus receives a digital input signal. The digital filter 912 can perform corresponding filtering on the digital input signal received from the interface 910, and provide a digital filter signal. The digital filter can be configured as a low-pass filter to remove the image of the input signal generated due to interpolation, and / or configured as a high-pass filter to remove the DC signal component. The digital filter 912 can also include one or more configurable filters that can be configured according to the use environment. The selection logic 914 can provide a selection signal and a symbol control signal for each UE based on the filtered digital input signal. The circuit 900 also includes an analog support circuit system 922, which includes an oscillator (e.g., a clock generator circuit) that is configured to provide a clock signal at a desired frequency for propagating digital data through the DAC 908.

[0059] Each instance of symbol logic 926 may provide a pair of symbol signals at a corresponding symbol output in response to a symbol input signal provided by selection logic 914. Each instance of synchronizer logic 928 may provide a synchronization selection signal in response to a selection signal provided by selection logic in response to the filtered digital input signal. As described herein, UE circuitry 920 may provide an analog output signal at 104 representing the value of input data based on the routing of the input data (e.g., bits / bits) to its corresponding UE in accordance with the selection signal and the symbol control signal received at 114 and 116, respectively.

[0060] Fig.10 1 is a block diagram illustrating an example modulator circuit 1000 including a DAC circuit 1014 (e.g., circuit 100 or 900) implemented in accordance with the present specification. Circuit 1000 may be implemented on or as part of an IC, or may be implemented on other types of circuits (e.g., a system on a chip or a printed circuit board). Circuit 1000 has one or more inputs 1002 and 1004 and a digital output 1006. Circuit 100 includes a noise shaping block 1008, a quantizer 1010, a digital filter 1012, and a DAC 1014. Fig.10In an example of , the noise shaping block 1008 can provide a noise shaped output based on the digital inputs at 1002 and 1004 (such as by shifting the noise to a high frequency bin away from the data signal). The quantizer can process the noise shaped signal and provide a quantized digital output signal (e.g., a multi-bit digital signal) at 1006. The feedback path includes a digital filter 1012 and a DAC 1014. The digital filter 1012 can provide a filtered digital signal based on the digital output signal provided at 1006. The DAC 1014 can convert the filtered digital signal into an analog signal (e.g., an analog differential signal), such as described herein. The analog signal can then be fed back into the input terminals 1002 and 1004. The modulator circuit 1000 can therefore be configured to provide a corresponding digital output at 1006 based on the analog input signals (e.g., differential analog input signals) received at 1004 and 1006. The modulator circuit 1000 can be implemented as a delta-sigma modulator analog-to-digital converter. The DAC circuit makes the modulator circuit very suitable for high performance applications (e.g., for audio or video applications, such as audio codecs), such as used in various environments, such as test and measurement applications, industrial, automotive, etc.

[0061] As described herein, a DAC (e.g., DAC 100, 900, 1014) can be configured to divide the UE of the DAC into segments and use a pair of independent pointers to track the positive input and negative input of each segment. In addition, as described herein, each segment can use a pair of usage variables to track the segment usage of positive data and negative data respectively. As described herein, a DAC implemented according to this specification can route data to the UE of the appropriate segment in a manner that reduces or avoids continuous overlapping transitions. The DAC can also effectively and efficiently synchronize the transitions between input data values. As a result, the noise (e.g., inter-marker interference) generated by this DAC can be significantly reduced compared to existing DAC designs.

[0062] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first example, device A is coupled to device B through a direct connection; or (b) in the second example, if the intervening component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intervening component C, so that device B is controlled by device A via the control signal generated by device A.

[0063] In this specification, a device that is "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer, and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. Configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof. In addition, a circuit or device described herein as including certain components can be configured to be coupled to those components to form the described circuit system or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors) and / or one or more sources (such as voltage sources and / or current sources) can be changed to include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be configured to be coupled to at least some of the passive elements and / or sources at the time of manufacture or after manufacture (such as by an end user and / or a third party) to form the described structure.

[0064] The expression “based on” means “based at least in part on.” Thus, if X is based on Y, X may be a function of Y and any number of other factors.

[0065] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are possible.

Claims

1. A circuit comprising: A digital-to-analog converter unit element switch circuit, i.e., a DAC unit element switch circuit, comprising a first sign switch input terminal and a second sign switch input terminal, a first selection switch input terminal and a second selection switch input terminal, and a first DAC output terminal, a second DAC output terminal and a third DAC output terminal; synchronizer logic comprising a select input and a first synchronization output and a second synchronization output, wherein the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input; as well as A selection logic includes a data input, a sign control output, and a selection control output, wherein the sign control output is coupled to the first sign switch input and the second sign switch input, and the selection control output is coupled to the selection input.

2. The circuit of claim 1 , further comprising a sign logic comprising a sign input terminal and a first sign output terminal and a second sign output terminal, wherein the first sign output terminal is coupled to the first sign switch input terminal, the second sign output terminal is coupled to the second sign switch input terminal, and the sign control output terminal is coupled to the sign input terminal.

3. The circuit of claim 2, wherein the sign logic is configured to provide opposite sign signals at the first sign output and the second sign output in response to a sign input signal at the sign input.

4. The circuit of claim 1 , wherein the DAC unit element switch circuit comprises a first switch path, a second switch path, and a third switch path, wherein each switch path comprises a set of at least two switches coupled between a power supply terminal and a corresponding DAC output.

5. The circuit of claim 4, wherein: the first switch path comprising a first pair of switches coupled between the power supply terminals and respective DAC outputs, wherein one switch of the first pair of switches has a first control input coupled to the first sign switch input and the other switch of the first pair of switches has a second control input coupled to the first select switch input, the second switch path comprises a second pair of switches coupled between the power supply terminal and the second DAC output, wherein one switch of the second pair of switches has a third control input coupled to a fixed voltage and the other switch of the first pair of switches has a fourth control input coupled to the second select switch input, and The third switch path comprises a third pair of switches coupled between the power supply terminal and the third DAC output, wherein one switch of the third pair of switches has a fifth control input coupled to the second sign switch input and the other switch of the third pair of switches has a sixth control input coupled to the first select switch input.

6. A circuit according to claim 1, wherein the synchronizer logic is configured to provide a first synchronization selection signal and a second synchronization selection signal at the first synchronization output terminal and the second synchronization output terminal, wherein the first synchronization selection signal and the second synchronization selection signal are inverted versions of each other in response to the selection signal at the selection input terminal, and the DAC unit element switching circuit is configured to transition between states in response to the first synchronization selection signal and the second synchronization selection signal.

7. The circuit of claim 6 , wherein the DAC unit element switching circuit and the synchronizer logic define an instance of a unit element, the circuit comprises N unit elements, wherein N is a positive integer greater than 2, and the selection logic is configured to divide the N unit elements into corresponding first and second segments of unit elements, and provide the selection signal as a selection vector to control the number of unit elements of a selected segment in the first segment and the second segment based on input data.

8. The circuit of claim 7 , wherein the selection logic is configured to provide the selection signal to control the cell elements of the selected one of the first segment and the second segment based on an overlap score, wherein the selection logic is configured to determine the overlap score in response to detecting a sign change between a previous value and a current value of the input data.

9. The circuit of claim 8, wherein the selection logic is configured to determine the overlap fraction for each of the first segment and the second segment based on a previous value of the selection vector and each current instance of the selection vector according to the current value of the input data.

10. The circuit of claim 8 , wherein the selection logic is configured to provide the selection signal based on a usage score, wherein the selection logic is configured to determine the usage score for each of the first segment and the second segment in response to not detecting a sign change between the previous value and the current value of the input data, and to determine the usage score for each of the first segment and the second segment based on a relative usage of the cell elements in each of the corresponding first segment and the second segment.

11. The circuit of claim 7 , wherein the selection logic is configured to select one of the first segment and the second segment and provide the selection signal as the selection vector to place one or more bits representing the input data such that there is no overlap between consecutive values ​​of the input data having opposite signs.

12. The circuit of claim 11 , wherein the selection logic is configured to implement a first pointer and a second pointer, wherein the first pointer is used to track the vector placement of positive values ​​of the input data in each of the first segment and the second segment, and the second pointer is used to track the vector placement of negative values ​​of the input data in each of the first segment and the second segment.

13. A circuit comprising: A plurality of digital-to-analog converter unit elements, namely DAC unit elements, wherein each DAC unit element comprises: a unit cell switch circuit configured to provide one of three values ​​in response to the first sign output signal and the second sign output signal and the first synchronization select signal and the second synchronization select signal; synchronizer logic configured to provide the first synchronization select signal and the second synchronization select signal in response to a select signal; symbol logic configured to provide the first symbol output signal and the second symbol output signal in response to a symbol control signal; and A selection logic is configured to divide the plurality of unit elements into a first segment and a second segment and provide the selection signal and the sign control signal to route input data to at least one DAC unit element of a given segment of the first segment and the second segment, thereby preventing consecutive overlapping transitions. 14 . The circuit of claim 13 , wherein the synchronizer logic is configured to provide the first synchronization select signal and the second synchronization select signal as inverted versions of each other that are synchronized in time in response to the select signal.

15. The circuit of claim 13 , wherein the selection logic is configured to provide the selection signal to the unit elements in the given one of the first segment and the second segment based on an overlap score, wherein the selection logic is configured to determine the overlap score in response to detecting a sign change between a previous value and a current value of the input data.

16. The circuit of claim 15, wherein the selection logic is configured to determine a respective overlap score for each of the first segment and the second segment based on a previous instance of a selection vector and each current instance of the selection vector according to the current value of the input data.

17. The circuit of claim 15 , wherein the selection logic is configured to provide the selection signal based on a usage score, wherein the selection logic is configured to determine the usage score in response to an absence of a sign change between the previous value and the current value of the input data, and to determine the usage score for each of the first segment and the second segment based on a relative usage of the cell element in each of the corresponding first segment and the second segment.

18. The circuit of claim 13, wherein the selection logic is configured to implement a first pointer and a second pointer, wherein the first pointer is used to track the vector placement of positive values ​​of the input data in each of the first segment and the second segment, and the second pointer is used to track the vector placement of negative values ​​of the input data in each of the first segment and the second segment.

19. A device comprising: A digital interface including a digital input terminal and a digital output terminal; a digital filter comprising a filter input and a filter output, wherein the filter input is coupled to the digital output; a selection logic comprising a data input, a selection output, and a sign output, wherein the data input is coupled to the filter output; a synchronizer logic circuit comprising a select input, a clock input, and a first synchronization output and a second synchronization output, wherein the select input is coupled to the select output; a sign logic circuit comprising a sign input and a first sign control output and a second sign control output, wherein the sign input is coupled to the sign output; as well as The digital-to-analog converter unit element circuit, i.e., a DAC unit element circuit, comprises a first sign switch input terminal and a second sign switch input terminal, a first selection switch input terminal and a second selection switch input terminal, and a DAC output terminal, wherein the first selection switch input terminal is coupled to the first synchronization output terminal, the second selection switch input terminal is coupled to the second synchronization output terminal, the first sign switch input terminal is coupled to the first sign control output terminal, and the second sign switch input terminal is coupled to the second sign control output terminal.

20. The device according to claim 19, wherein the DAC unit element circuit comprises a plurality of N unit elements, wherein N is a positive integer greater than 2, and the selection logic comprises N selection output terminals and N sign output terminals and is configured to divide the N unit elements into corresponding first segments and second segments of corresponding unit elements.

21. The apparatus of claim 20, wherein: The synchronizer logic circuit includes N synchronizer logic circuits, each synchronizer logic circuit is configured to provide a pair of synchronized output signals in response to a corresponding selection signal; The symbolic logic circuit includes N symbolic logic circuits, each symbolic logic circuit being configured to provide a pair of symbolic output signals in response to a corresponding symbolic control signal; as well as The selection logic is configured to provide N selection signals and N sign control signals to route input data to at least one DAC cell element of a given one of the first segment and the second segment to prevent overlapping transitions.

22. The apparatus of claim 21, wherein each of the N unit cells is configured to provide one of three output values ​​in response to a corresponding pair of the sign output signals and a corresponding set of the synchronization output signals.

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