Micro-nano GaN-based VCSEL (Vertical Cavity Surface Emitting Laser) without electron barrier layer and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor optoelectronic devices, and particularly relates to a low-loss micro-nano GaN-based VCSEL (Vertical Cavity Surface Emitting Laser) without an electron barrier layer and a preparation method thereof. Comprising a substrate, an N-type GaN layer is arranged on the substrate, a plurality of VCSEL micro-nano columns are arranged on the surface of the N-type GaN layer, and a lower electrode layer, an insulating layer and an upper electrode layer which are used for wrapping the VCSEL micro-nano columns are sequentially arranged on the surface of the N-type GaN layer from bottom to top; the VCSEL micro-nano column is of a VCSEL epitaxial structure and comprises an N-GaN buffer layer, an N-DBR layer, a lower space layer, an active region, an upper space layer, a P-DBR layer and a P + GaN contact layer which are sequentially arranged from bottom to top. The bottom of the VCSEL micro-nano column is arranged on the upper surface of the N-type GaN layer, and the top of the upper P + GaN contact layer is arranged in the upper electrode layer; the lower electrode layer and the N-type GaN layer form ohmic contact, and the upper electrode layer and the P + GaN contact layer of the VCSEL micro-nano column form ohmic contact. The loss of the device is reduced, and the wavelength adjusting range of the device is widened.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor optoelectronic devices, and in particular relates to a low-loss micro-nano GaN-based VCSEL without an electron blocking layer and a preparation method thereof. Background Art

[0002] Vertical Cavity Surface Emitting Laser (VCSEL) is a semiconductor laser whose light emission direction is perpendicular to the device surface. Compared with edge-emitting lasers, it has the advantages of easy coupling of output beams with optical fibers, low threshold, single longitudinal mode emission, easy arraying, and low manufacturing cost. Infrared VCSELs based on the AlGaAs / GaAs material system have long been mature and commercialized. They are also used in optical interconnection, optical communication, optical storage, quantum precision measurement and other fields. However, visible light VCSELs based on the GaN material system are still difficult to manufacture and are currently in the laboratory research stage. The main reason is the poor material compatibility and the lack of distributed Bragg reflector (DBR) materials that match the GaN lattice. The lattice mismatch between AlN and GaN is as high as 2.4%. As the number of AlGaN / GaN DBR logarithms increases, a large number of defects will be generated due to strain relaxation. In addition, P-type doping of the AlGaN / GaN material system is relatively difficult, which also hinders the industrialization process of GaN-based visible light VCSELs.

[0003] In order to solve the problems existing in GaN-based VCSELs, researchers proposed a solution to replace III-nitride DBRs with dielectric film DBRs. Based on this idea, researchers first proposed a VCSEL with a composite DBR structure, that is, using nitride DBR as the lower reflector and dielectric DBR as the upper reflector, respectively. The dielectric materials include Ta2O5 / SiO2, Nb2O5 / SiO2, SiO2 / Si3N4, etc. This solution avoids the difficulty of p-type doping, but the nitride DBR as the lower reflector still has extremely high strain accumulation and produces a large number of defects. These defects will affect the subsequent epitaxial growth process, resulting in an increase in the defect density in the active area, reducing the radiation recombination efficiency and internal quantum efficiency of the VCSEL, and increasing the internal loss. In addition, the use of dielectric film DBR as the upper reflector increases the process difficulty of chip preparation and is not conducive to the industrialization process. Driven by the emergence and promotion of laser lift-off technology, researchers further proposed a VCSEL structure with dual dielectric film DBRs, that is, dielectric film DBRs are used on both the upper and lower reflectors. This structure completely avoids the problem of DBR material incompatibility and the problem of difficulty in achieving P-type doping, but it further increases the difficulty of chip processing and is not conducive to industrial implementation.

[0004] However, both the VCSEL with a composite DBR structure and the VCSEL with a dual dielectric film DBR structure have a high concentration of P-type doped electron blocking layer. This electron blocking layer is in the VCSEL resonant cavity. When photons propagate back and forth in the resonant cavity, they will be absorbed by the idle electrons in the electron blocking layer, increasing the loss of the device. In recent years, the growth technology of GaN micro-nano column arrays has gradually matured, and axial heterostructure nano columns can form a complete VCSEL epitaxial structure, providing a new possible way for the preparation of GaN-based VCSELs, namely, micro-nano VCSELs based on GaN-based axial heterojunction micro-nano columns. Therefore, it is necessary to further improve the structure of VCSELs to simplify the preparation process, reduce device losses, and expand the wavelength range of the device. Summary of the invention

[0005] The technical problems to be solved by the present invention are as follows: 1) The existing GaN-based VCSELs all contain an electron blocking layer, which contains a high concentration of P-type doping (generally 2 to 3×1018cm-3), and this electron blocking layer is located in the resonant cavity, which has a strong absorption effect on photons and increases the loss of the device; 2) There is a lattice mismatch of 2.4% between AlN and GaN. With the increase of the number of AlGaN / GaNDBR cycles, the strain also accumulates accordingly, resulting in severe strain relaxation and a large number of defects. The defects generated in the lower DBR will affect the growth of the subsequent space layer and active area, resulting in high-density defects in the space layer and active area; 3) The preparation of the dielectric film DBR not only increases the process difficulty, but also the dielectric film is not conductive, which is not conducive to the injection of holes.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a micro-nano GaN-based VCSEL without an electron blocking layer, comprising a substrate, an N-type GaN layer is arranged on the substrate, a plurality of VCSEL micro-nano columns are arranged on the surface of the N-type GaN layer, and a lower electrode layer, an insulating layer and an upper electrode layer for wrapping the VCSEL micro-nano columns are arranged on the surface of the N-type GaN layer in sequence from bottom to top;

[0007] The VCSEL micro-nano column is a VCSEL epitaxial structure, including an N-GaN buffer layer, an N-DBR layer, a lower space layer, an active region, an upper space layer, a P-DBR layer, and a P+GaN contact layer arranged in sequence from bottom to top; the bottom of the VCSEL micro-nano column is arranged on the upper surface of the N-type GaN layer, and the top of the upper P+GaN contact layer is arranged in the upper electrode layer;

[0008] The lower electrode layer forms an ohmic contact with the N-type GaN layer, and the upper electrode layer forms an ohmic contact with the P+GaN contact layer of the VCSEL micro-nano column.

[0009] The diameter of the VCSEL micro-nano column is 100nm-2000nm.

[0010] The substrate is an N-type GaN substrate, sapphire or silicon carbide; the lower space layer and the upper space layer are GaN layers, and the insulating layer material is SiO2 or Si3N4.

[0011] The upper electrode layer includes a transparent electrode layer and a P electrode layer. The transparent electrode layer is used to cover the top of the VCSEL micro-nano column. The P electrode layer is provided with light holes for light output at positions corresponding to the VCSEL micro-nano columns.

[0012] In the VCSEL micro-nano column, the active region is a single-layer quantum well structure or a multi-quantum well structure formed by periodic overlap of two materials; the N-DBR layer is a GaN layer and an Al x Ga 1-x N layers are periodically overlapped, with the number of periods ranging from 35 to 60; the P-DBR layer is composed of Al x Ga 1-x The N layer and the GaN layer are periodically overlapped, and the number of periods is 10 to 30; the GaN layer and the Al x Ga 1-x The thickness of the N layer is λ / 4n, where λ is the emission wavelength of the VCSEL, n is the refractive index of the material, and x is the Al component of AlGaN.

[0013] The edge region of the lower electrode layer is not covered by the insulating layer and the upper electrode layer, and the width of the edge region is greater than 20 μm.

[0014] The VCSEL micro-nano columns are arranged in a two-dimensional periodic manner.

[0015] In addition, the present invention also provides a method for preparing the micro-nano GaN-based VCSEL without an electron blocking layer, comprising the following steps:

[0016] Step 1: Select a substrate and grow an N-type GaN layer on the substrate;

[0017] Step 2: Deposit a mask layer on the N-GaN surface by plasma enhanced chemical vapor deposition or magnetron sputtering technology;

[0018] Step 3: exposing the mask layer opening pattern on the mask layer, and then using dry etching technology to open holes on the mask layer to the surface of the N-type GaN layer as a template for the growth of the VCSEL micro-nano column array;

[0019] Step 4: After cleaning, place the film in the reaction chamber of the MOCVD device, and grow a VCSEL micro-nano column array in the opening of the mask layer by autocatalysis; after the growth of the VCSEL micro-nano column is completed, remove the mask layer;

[0020] Step 5: Expose the VCSEL micro-nano pillars to form a patterned photoresist, where the area of ​​the photoresist is larger than the VCSEL micro-nano pillars; then deposit metal on the device surface. After the deposition is completed, remove the photoresist and the metal on the surface through a stripping process to expose the VCSEL micro-nano pillars and obtain a lower electrode layer;

[0021] Step 6: Annealing the lower electrode layer by an alloy annealing process to form an ohmic contact with the N-type GaN layer;

[0022] Step 7: Deposit an insulating layer on the device surface using PECVD or magnetron sputtering technology to completely bury the VCSEL micro-nano column, and then use a wet etching process to remove a portion of the insulating layer to expose a portion of the P+GaN contact layer of the VCSEL micro-nano column;

[0023] Step 8: depositing an upper electrode layer on the insulating layer so that it completely covers the VCSEL micro-nano pillars, and then setting a photoresist on the device surface by an exposure method to protect the area where the VCSEL micro-nano pillar array is located, and exposing the edge area of ​​the device; using dry etching and wet etching processes to remove the insulating layer in the edge area until the lower electrode layer is exposed.

[0024] The step 8 specifically comprises the following steps:

[0025] Step 8.1: depositing a transparent electrode layer on the insulating layer so that the transparent electrode completely covers the P+GaN contact layer and forms an ohmic contact therewith;

[0026] Step 8.2: Then, a photoresist is placed on the device surface by an exposure method to protect the area where the VCSEL micro-nano column array is located, and the edge area of ​​the device is exposed; the insulating layer of the edge area is removed by dry etching and wet etching processes until the lower electrode layer of the edge area is exposed, and then the photoresist is removed;

[0027] Step 8.3: Using an exposure method, a photoresist is placed on the device surface to protect the area where the VCSEL micro-nano pillars are located and the edge area of ​​the device, and a P electrode layer is deposited on the micro-nano pillar array by magnetron sputtering or electron beam evaporation;

[0028] Step 8.4: Use the adhesive stripping process to remove the P electrode layer on the top and edge areas of the VCSEL micro-nano column to expose the laser emission opening and the edge area of ​​the lower electrode layer.

[0029] In the step 8.3, the diameter of the photoresist set in the area where the VCSEL micro-nano column is located is larger than the diameter of the VCSEL micro-nano column.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] First, the VCSEL structure provided by the present invention does not contain an electron blocking layer, thereby avoiding the absorption of photons by the electron blocking layer and reducing the loss of the device.

[0032] Second, the micro-nano pillars can release stress in both the X and Y directions through elastic deformation. Therefore, the stress in both N-DBR and P-DBR can be released through elastic deformation without generating a large number of defects, which is beneficial to the growth of nitride DBR. At the same time, the active region can achieve very high strain without strain relaxation, so the material composition of the active region can vary in a wider range. Accordingly, the emission wavelength of the VCSEL can be adjusted in a wider range.

[0033] Third, the diameter of the micro-nano pillar is less than 2 μm, which can naturally achieve single transverse mode emission, making the wavelength more precise, and eliminating the preparation process of the oxidation restriction structure, simplifying the preparation process;

[0034] Fourth, nanowires are natural waveguide structures. The refractive index of nanowires is much greater than that of the dielectric film of the insulating layer. Photons will be confined in the nanowires and propagate along the axial direction. Nanowires are single crystals grown epitaxially, and there is no problem of etching damage on the sidewalls, which can better confine photons. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic structural diagram of a low-loss micro-nano GaN-based VCSEL without an electron blocking layer provided by an embodiment of the present invention;

[0036] Figure 2 Schematic diagram of the epitaxial structure of VCSEL in an embodiment of the present invention;

[0037] Figure 3 Schematic diagram of the arrangement of the N-side electrode on the outside of the micro-nano column array in an embodiment of the present invention;

[0038] Figure 4 Schematic diagram of the epitaxial structure of a green light VCSEL in an embodiment of the present invention;

[0039] Figure 5 Schematic diagram of mask layer opening and P-side electrode opening in an embodiment of the present invention;

[0040] Figure 6 is the DBR reflection spectrum of the VCSEL in the embodiment of the present invention;

[0041] Figure 7 Schematic diagram of the arrangement of the N-side electrode in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0043] The present invention aims at the problems of high absorption loss of electron blocking layer in GaN-based VCSEL, serious strain accumulation and high defect density of nitride DBR, and high difficulty in the preparation process of dielectric film DBR, and provides a micro-nano GaN-based VCSEL without electron blocking layer. Taking advantage of the high Al component of P-DBR, the electron blocking layer in the resonant cavity is removed, and the absorption loss is reduced; taking advantage of the small diameter of micro-nano column, the stress is released through elastic deformation, and the defect density is reduced; since the diameter of micro-nano column is less than 2μm, it naturally has the advantage of single transverse mode emission; micro-nano column can release stress in two dimensions perpendicular to the growth direction, has a higher tolerance to strain, and can achieve a wider range of material composition and wavelength control; micro-nano column is a single crystal structure grown epitaxially, and there is no problem of side wall damage.

[0044] Embodiment 1

[0045] like Figure 1 As shown, the first embodiment of the present invention provides a micro-nano GaN-based VCSEL without an electron blocking layer, including a substrate, an N-type GaN layer disposed on the substrate, a plurality of VCSEL micro-nano columns disposed on the surface of the N-type GaN layer, and a lower electrode layer, an insulating layer and an upper electrode layer for wrapping the VCSEL micro-nano columns disposed on the surface of the N-type GaN layer from bottom to top. Each VCSEL micro-nano column can be regarded as an independent micro-nano VCSEL structure.

[0046] like Figure 2 As shown, in this embodiment, the VCSEL micro-nano column is a VCSEL epitaxial structure, including an N-GaN buffer layer, an N-DBR layer, a lower space layer, an active region, an upper space layer, a P-DBR layer, and a P+GaN contact layer arranged in sequence from bottom to top; the bottom of the VCSEL micro-nano column is arranged on the upper surface of the N-type GaN layer, and the top of the upper P+GaN contact layer is arranged in the upper electrode layer; the lower electrode layer forms an ohmic contact with the N-type GaN layer, and the upper electrode layer forms an ohmic contact with the P+GaN contact layer of the VCSEL micro-nano column. In particular, the VCSEL micro-nano column structure of this embodiment does not contain an electron blocking layer.

[0047] Specifically, in this embodiment, the diameter of the VCSEL micro-nano column is 100nm to 2000nm. The diameter is determined by the size of the opening of the mask layer, and the diameter value range is set to 100nm to 2000nm. Because the surface effect is too strong when the diameter is too small, the device light output power is too low, and the large diameter will cause the stress to be unable to be better released, resulting in a large number of defects. Preferably, the diameter of the VCSEL micro-nano column is 500nm.

[0048] Specifically, in this embodiment, the substrate is an N-type GaN substrate, sapphire or silicon carbide. The insulating layer material is SiO2 or Si3N4.

[0049] Specifically, in this embodiment, in the VCSEL micro-nano column, the lower space layer and the upper space layer are GaN layers, and the equivalent optical thickness of the upper space layer + active region + lower space layer is the cavity length of this VCSEL, which is equal to an integer multiple of the wavelength λ. In this embodiment, the cavity length is set to 2λ, that is, ∑ i L i ×n i =2λ,L i is the thickness of each layer that makes up the VCSEL resonant cavity, n i is the refractive index of each layer. In addition, considering the matching of the standing wave in the resonant cavity and the quantum well active region, the thicknesses of the upper space layer and the lower space layer are set to 178 nm and 180 nm respectively.

[0050] Specifically, in the VCSEL micro-nano column of this embodiment, the P+GaN contact layer needs to be heavily doped to form an ohmic contact, and the doping concentration should reach 2E19cm -3 Above, the thickness is set to 300 nm.

[0051] Specifically, the insulating layer wraps the N-GaN buffer layer, N-DBR, lower space layer, active area, upper space layer, P-DBR of the VCSEL micro-nano column, and buries part of the P+GaN contact layer. Optionally, the thickness of the P+GaN contact layer buried by the insulating layer is 100nm, and 200nm is exposed outside the insulating layer. The insulating layer can be selected from a variety of dielectric materials. Optionally, the insulating layer is set to SiO2 in this embodiment.

[0052] Furthermore, in this embodiment, the upper electrode layer includes a transparent electrode layer and a P electrode layer, the transparent electrode layer is used to cover the top of the VCSEL micro-nano column to ensure complete coverage of the P+GaN contact layer and form an ohmic contact with the P+GaN contact layer; a light-through hole for light output is provided on the P electrode layer at a position corresponding to the VCSEL micro-nano column.

[0053] In this embodiment, a transparent electrode layer is arranged on the insulating layer. The material of the transparent electrode layer is ITO. The thickness of the transparent electrode is greater than 200nm. Optionally, the thickness of the transparent electrode layer is set to 300nm, completely covering the exposed P-GaN contact layer and forming an ohmic contact therewith. A metal P-side electrode is arranged on the transparent electrode. The metal P-side electrode is opaque. Therefore, an opening is arranged on the P-side electrode layer above each VCSEL micro-nano column. The diameter of the opening is greater than the diameter of the VCSEL micro-nano column. Optionally, the diameter of the opening of the P-side electrode is set to 600nm. Figure 5 shown.

[0054] Furthermore, in this embodiment, in the VCSEL micro-nano column, the active region is a single-layer quantum well structure. Figure 2 As shown, the active region can also be a multi-quantum well structure formed by periodic overlap of quantum well layers and quantum barrier layers, and the value of the alternating period k is 3 to 10. Specifically, in the present embodiment, in the VCSEL micro-nano column, the N-DBR layer is a GaN layer and an Al x Ga 1-x N layers are periodically overlapped, and the number of cycles is n n 35~60; P-DBR layer is made of Al x Ga 1-x The N layer and the GaN layer are periodically overlapped, and the period number n p 10~30; GaN layer and Al x Ga 1-x The thickness of the N layer is λ / 4n, where λ is the emission wavelength of the VCSEL, n is the refractive index of the material, and x is the Al component of AlGaN.

[0055] Specifically, in this embodiment, the N-DBR layer is composed of N-type Al 0.9 GaN (low refractive index layer) and GaN (high refractive index layer) are periodically overlapped. The optical thickness of these two layers is 1 / 4 of the VCSEL laser wavelength, that is, the disk thickness is λ / 4n, where n is the refractive index of each of the two layers. The refractive index of the material will change with the change of the wavelength of the incident light. 0.9 The refractive index of GaN and GaN can be calculated by the Sellmeier model:

[0056]

[0057] Among them, s i and λ j are fitting parameters.

[0058] According to the above refractive index dispersion model, Al 0.9The thicknesses of the GaN layer and the GaN layer are 58nm and 51nm respectively. Combining the refractive index dispersion model and the transmission matrix method, the Al 0.9 The reflection spectrum of GaN / GaN DBR, such as Figure 6 As shown. Considering that the laser is emitted from the P-DBR, the reflectivity of the P-DBR is required to be less than that of the N-DBR. Therefore, the N-DBR period is set to 40 and the P-DBR period is set to 25. The doping concentration of the N-DBR and P-DBR is set to 2×10 18 cm -3 .

[0059] Specifically, in this embodiment, the active region is set to In 0.29 Ga 0.71 N / In 0.11 Ga 0.89 N multiple quantum well structure. 0.29 Ga 0.71 The thickness of the N quantum well is set to 3 nm, In 0.11 Ga 0.89 The thickness of the N quantum barrier is 6nm, such as Figure 4 As shown, the number of periods is set to 5, so there are 5 layers of quantum wells, 6 layers of quantum barriers, and the total thickness is 51nm.

[0060] Furthermore, in this embodiment, the period number k of the active region is 5, and the period number n of the N-DBR layer is n The value of is 40, the period number n of the P-DBR layer p The value of is 25.

[0061] Furthermore, in this embodiment, the VCSEL micro-nano columns are arranged in a two-dimensional periodic manner, such as Figure 3 As shown, in this embodiment, the VCSEL micro-nano columns are arranged in a square array. Specifically, in this embodiment, the center distance between two adjacent VCSEL micro-nano columns is 5 to 15 μm, preferably 10 μm. Specifically, in this embodiment, the edge area of ​​the lower electrode layer is not covered with the insulating layer and the upper electrode layer, and is in a bare state. The width of the edge area is greater than 20 μm, which is used for later packaging leads.

[0062] Specifically, in this embodiment, the doping concentration of the N-type GaN layer is set to 1E18 cm -3 ~2E18cm -3 In order to form a good ohmic contact with the lower electrode. In the VCSEL micro-nano column, the N-GaN buffer layer is used to cover the etching damage caused by the mask layer opening, so its thickness needs to be greater than or equal to 200nm. Optionally, the thickness of the N-GaN buffer layer is set to 200nm.

[0063] In this embodiment, since the diameter of the VCSEL micro-nano column is very small, it can effectively release stress through elastic deformation without generating defects. Therefore, the active region can be set to different nitride materials, and a wide range of wavelength adjustment can be achieved by changing the material composition. Therefore, the luminous wavelength of the present invention can be any wavelength within the range of 380nm to 550nm, covering ultraviolet, purple, blue, and green bands.

[0064] Embodiment 2

[0065] Embodiment 2 of the present invention provides a method for preparing a micro-nano GaN-based VCSEL without an electron blocking layer, wherein a GaN-based green light VCSEL is prepared. The preparation method comprises the following steps:

[0066] Step 1: Select a substrate and grow an N-type GaN layer on the substrate.

[0067] Specifically, in this embodiment, a c-plane sapphire substrate is selected as a substrate for N-GaN growth; specifically, this embodiment adopts metal organic chemical vapor deposition (MOCVD) technology, and adopts a two-step method to first grow 2μm U-GaN, and then grow 1μm N-GaN on U-GaN.

[0068] Step 2: Deposit a mask layer on the N-GaN surface by plasma enhanced chemical vapor deposition or magnetron sputtering technology. The mask layer is made of SiO2 with a thickness of 20nm.

[0069] Step 3: Expose the mask layer opening pattern on the mask layer, and then use dry etching technology to open holes on the mask layer to the surface of the N-type GaN layer as a template for the growth of the VCSEL micro-nano column array.

[0070] In this embodiment, a high-precision exposure technique (such as a stepper or electron beam exposure technique) is used to expose the mask layer opening pattern on the mask layer, and then a dry etching technique is used to open holes on the mask layer to the N-GaN surface as a template for the growth of the micro-nano column array.

[0071] Step 4: The above micro-nano column template is thoroughly cleaned to ensure that there is no residual chemical substances such as photoresist; after cleaning, it is placed in the reaction chamber of the MOCVD equipment, and a VCSEL micro-nano column array is grown in the opening of the mask layer by autocatalysis; after the growth of the VCSEL micro-nano column is completed, the mask layer is removed.

[0072] Specifically, in this embodiment, the cleaned template is placed in the reaction chamber of the MOCVD equipment, and the VCSEL micro-nano column array is grown in an autocatalytic manner under low temperature and low V / III ratio growth conditions. The growth rate is controlled by changing the flow rate of the group III source, and the V / III ratio is controlled by changing the flow rate of the group V source. After the growth of the VCSEL micro-nano column array is completed, the SiO2 mask layer is removed using a HF+H2O2 mixed solution.

[0073] Step 5: Expose the VCSEL micro-nano pillar to form a patterned photoresist, where the area of ​​the photoresist is larger than the VCSEL micro-nano pillar; then deposit metal on the device surface. After the deposition is completed, remove the photoresist and the metal on the surface through a stripping process to expose the VCSEL micro-nano pillar and obtain the lower electrode layer.

[0074] In this embodiment, a high-precision exposure technique is used to form a pattern on the device surface, such as Figure 7 As shown in the figure, the shaded part is the photoresist covering the VCSEL micro-nano column array, while there is no photoresist in the blank area. The circular diameter of the shaded part is 2μm, which is much larger than the diameter of the VCSEL micro-nano column and can well cover the VCSEL micro-nano column. Then magnetron sputtering or electron beam evaporation technology is used to deposit metal on the device surface.

[0075] In this embodiment, after the growth is completed, the mask layer needs to be removed to expose the N-GaN layer, and then the lower electrode (N-side electrode) is evaporated in the gap of the VCSEL micro-nano column by combining photolithography and coating technology. The N-side electrode basically covers the gap of the VCSEL micro-nano column and the outer edge of the VCSEL micro-nano column array. The outer edge width exceeds 20μm and is used for the later packaging lead. In particular, the thickness of the N-side electrode cannot be greater than the thickness of the N-GaN buffer layer in the micro-nano column to avoid leakage.

[0076] The VCSEL micro-nano column is protected by photoresist. The metal is deposited on the photoresist instead of directly on the top of the VCSEL micro-nano column. Only the blank area without photoresist and the edge area outside the micro-nano column array will be deposited with the N-side electrode. Figure 7 The blank area and Figure 3 A lower electrode layer serving as an N-side electrode will be deposited in the edge region of the transistor.

[0077] Then, the metal and photoresist within a radius of 2 μm centered on the VCSEL micro-nano column are removed by a tape stripping process to expose the VCSEL micro-nano column array.

[0078] Step 6: Annealing alloy process Anneal the lower electrode layer to form an ohmic contact with the N-type GaN layer.

[0079] Step 7: Use PECVD or magnetron sputtering process to deposit an insulating layer on the device surface to completely bury the VCSEL micro-nano column, and then use wet etching process to remove a portion of the insulating layer to expose a portion of the P+GaN contact layer of the VCSEL micro-nano column.

[0080] In this embodiment, the material of the insulating layer is SiO2, and the thickness of the portion of the P+GaN contact layer of the VCSEL micro-nano column exposed from the insulating layer is 200 nm.

[0081] Step 8: depositing an upper electrode layer on the insulating layer so that it completely covers the VCSEL micro-nano pillars, and then setting a photoresist on the device surface by an exposure method to protect the area where the VCSEL micro-nano pillar array is located, and exposing the edge area of ​​the device; using dry etching and wet etching processes to remove the insulating layer in the edge area until the lower electrode layer is exposed.

[0082] Specifically, in this embodiment, step 8 specifically includes the following steps:

[0083] Step 8.1: Deposit a transparent electrode layer on the insulating layer so that the transparent electrode completely covers the P+GaN contact layer and forms an ohmic contact therewith.

[0084] In this embodiment, a 300 nm thick ITO transparent electrode is deposited on the insulating layer. The transparent electrode completely covers the P+GaN contact layer and forms an ohmic contact therewith.

[0085] Step 8.2: Then, a photoresist is set on the device surface by exposure method to protect the area where the VCSEL micro-nano column array is located, and the edge area of ​​the device is exposed; the insulating layer of the edge area is removed by dry etching and wet etching process until the lower electrode layer of the edge area is exposed, and then the photoresist is removed.

[0086] In this embodiment, an exposure method is used to form a rectangular pattern above the micro-nano column array, protecting the ITO transparent electrode and the insulating layer in the micro-nano column array area and exposing the edge area outside the micro-nano column array.

[0087] Step 8.3: Photoresist is placed on the device surface by exposure to protect the area where the VCSEL micro-nano pillars are located and the edge area of ​​the device, and a P electrode layer is deposited above the micro-nano pillar array by magnetron sputtering or electron beam evaporation.

[0088] In the step 8.3, the diameter of the photoresist set in the area where the VCSEL micro-nano column is located is larger than the diameter of the VCSEL micro-nano column.

[0089] In this embodiment, a high-precision exposure technique is used to form a pattern on the ITO transparent electrode. Figure 5As shown, the P-side electrode opening area is protected by photoresist, and the diameter is 600nm, which is larger than the diameter of the VCSEL micro-nano column to ensure that the laser can be emitted through the opening. Similarly, the lower electrode surface in the edge area is also provided with photoresist protection.

[0090] Step 8.4: Use the adhesive stripping process to remove the P electrode layer on the top and edge areas of the VCSEL micro-nano column to expose the laser emission opening and the edge area of ​​the lower electrode layer.

[0091] After the above steps are completed, slicing and splitting can be performed as needed to form a VCSEL array chip, and the GaN-based VCSEL of the embodiment of the present invention is completed.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A micro-nano GaN-based VCSEL without an electron blocking layer, characterized in that: The invention comprises a substrate, an N-type GaN layer is arranged on the substrate, a plurality of VCSEL micro-nano columns are arranged on the surface of the N-type GaN layer, and a lower electrode layer, an insulating layer and an upper electrode layer for wrapping the VCSEL micro-nano columns are arranged on the surface of the N-type GaN layer in sequence from bottom to top; The VCSEL micro-nano column is a VCSEL epitaxial structure, including an N-GaN buffer layer, an N-DBR layer, a lower space layer, an active region, an upper space layer, a P-DBR layer, and a P+GaN contact layer arranged in sequence from bottom to top; the bottom of the VCSEL micro-nano column is arranged on the upper surface of the N-type GaN layer, and the top of the upper P+GaN contact layer is arranged in the upper electrode layer; The lower electrode layer forms an ohmic contact with the N-type GaN layer, and the upper electrode layer forms an ohmic contact with the P+GaN contact layer of the VCSEL micro-nano column.

2. The micro-nano GaN-based VCSEL without an electron blocking layer according to claim 1, characterized in that: The diameter of the VCSEL micro-nano column is 100nm-2000nm.

3. The micro-nano GaN-based VCSEL without an electron blocking layer according to claim 1, characterized in that: The substrate is an N-type GaN substrate, sapphire or silicon carbide; the lower space layer and the upper space layer are GaN layers, and the insulating layer material is SiO2 or Si3N4.

4. The micro-nano GaN-based VCSEL without an electron blocking layer according to claim 1, characterized in that: The upper electrode layer includes a transparent electrode layer and a P electrode layer. The transparent electrode layer is used to cover the top of the VCSEL micro-nano column. The P electrode layer is provided with light holes for light output at positions corresponding to the VCSEL micro-nano columns.

5. The micro-nano GaN-based VCSEL without an electron blocking layer according to claim 1, characterized in that: In the VCSEL micro-nano column, the active region is a single-layer quantum well structure or a multi-quantum well structure formed by periodic overlap of two materials; the N-DBR layer is a GaN layer and an Al x Ga 1-x N layers are periodically overlapped, with the number of periods ranging from 35 to 60; the P-DBR layer is composed of Al x Ga 1-x The N layer and the GaN layer are periodically overlapped, and the number of periods is 10 to 30; the GaN layer and the Al x Ga 1-x The thickness of the N layer is λ / 4n, where λ is the emission wavelength of the VCSEL, n is the refractive index of the material, and x is the Al component of AlGaN.

6. The micro-nano GaN-based VCSEL without an electron blocking layer according to claim 1, characterized in that: The edge region of the lower electrode layer is not covered with the insulating layer and the upper electrode layer, and the width of the edge region is greater than 20 μm.

7. The micro-nano GaN-based VCSEL without an electron blocking layer according to claim 1, characterized in that: The VCSEL micro-nano columns are arranged in a two-dimensional periodic manner.

8. The method for preparing a micro-nano GaN-based VCSEL without an electron blocking layer according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1: Select a substrate and grow an N-type GaN layer on the substrate; Step 2: Deposit a mask layer on the N-GaN surface by plasma enhanced chemical vapor deposition or magnetron sputtering technology; Step 3: exposing the mask layer opening pattern on the mask layer, and then using dry etching technology to open holes on the mask layer to the surface of the N-type GaN layer as a template for the growth of the VCSEL micro-nano column array; Step 4: After cleaning, place the film in the reaction chamber of the MOCVD device, and grow a VCSEL micro-nano column array in the opening of the mask layer by autocatalysis; after the growth of the VCSEL micro-nano column is completed, remove the mask layer; Step 5: Expose the VCSEL micro-nano pillars to form a patterned photoresist, where the area of ​​the photoresist is larger than the VCSEL micro-nano pillars; then deposit metal on the device surface. After the deposition is completed, remove the photoresist and the metal on the surface through a stripping process to expose the VCSEL micro-nano pillars and obtain a lower electrode layer; Step 6: Annealing the lower electrode layer by an alloy annealing process to form an ohmic contact with the N-type GaN layer; Step 7: Deposit an insulating layer on the device surface using PECVD or magnetron sputtering technology to completely bury the VCSEL micro-nano column, and then use a wet etching process to remove a portion of the insulating layer to expose a portion of the P+GaN contact layer of the VCSEL micro-nano column; Step 8: depositing an upper electrode layer on the insulating layer so that it completely covers the VCSEL micro-nano pillars, and then setting a photoresist on the device surface by an exposure method to protect the area where the VCSEL micro-nano pillar array is located, and exposing the edge area of ​​the device; using dry etching and wet etching processes to remove the insulating layer in the edge area until the lower electrode layer is exposed.

9. The method for preparing a micro-nano GaN-based VCSEL without an electron blocking layer according to claim 8, characterized in that: The step 8 specifically includes the following steps: Step 8.1: depositing a transparent electrode layer on the insulating layer so that the transparent electrode completely covers the P+GaN contact layer and forms an ohmic contact therewith; Step 8.2: Then, a photoresist is placed on the device surface by an exposure method to protect the area where the VCSEL micro-nano column array is located, and the edge area of ​​the device is exposed; the insulating layer of the edge area is removed by dry etching and wet etching processes until the lower electrode layer of the edge area is exposed, and then the photoresist is removed; Step 8.3: Using an exposure method, a photoresist is placed on the device surface to protect the area where the VCSEL micro-nano pillars are located and the edge area of ​​the device, and a P electrode layer is deposited on the micro-nano pillar array by magnetron sputtering or electron beam evaporation; Step 8.4: Use the adhesive stripping process to remove the P electrode layer on the top and edge areas of the VCSEL micro-nano column to expose the laser emission opening and the edge area of ​​the lower electrode layer.

10. The method for preparing a micro-nano GaN-based VCSEL without an electron blocking layer according to claim 8, characterized in that: In the step 8.3, the diameter of the photoresist set in the area where the VCSEL micro-nano column is located is larger than the diameter of the VCSEL micro-nano column.

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