Efficient data exchange system and method for digital ink-jet printer

Abstract

The invention discloses an efficient data exchange system and method for a digital ink-jet printer, and relates to the technical field of printers. Comprising an MCU (Microprogrammed Control Unit) and an FPGA (Field Programmable Gate Array), the FPGA is responsible for reading the content in the buffer area and performing related processing; the DRAM is used for storing printing data; the DRAM is positioned between the MCU and the FPGA; according to the invention, a high-speed dynamic random access memory chip is introduced as a data exchange medium between the microcontroller unit and the field-programmable gate array, so that the problems of bandwidth bottleneck, unmatched data transmission rate and low system response speed of the traditional data bus architecture are solved.

Description

Technical Field

[0001] The invention relates to the technical field of printers, and in particular to a high-efficiency data exchange system and method for digital inkjet printers. Background Art

[0002] In modern digital inkjet printer systems, data exchange between microcontroller units (MCUs) and field programmable gate arrays (FPGAs) is essential for efficient printing. However, with the increase in printing functionality and speed, traditional data bus architectures face bandwidth bottlenecks, data transfer rate mismatches, and low system response speeds, which limit the performance and application scope of printers. To meet these challenges, a new data exchange architecture is urgently needed to increase data transfer rates, alleviate bandwidth limitations, and reduce system latency, thereby improving the overall performance and printing efficiency of digital inkjet printers. Summary of the invention

[0003] The object of the present invention is to provide an efficient data exchange system and method for a digital inkjet printer.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides an efficient data exchange system for a digital inkjet printer, comprising an MCU and an FPGA, wherein the MCU, as a device controller, provides commands and buffer addresses and triggers automatic address increment; the FPGA is responsible for reading the buffer content and performing related processing; and further comprises a DRAM for storing print data; the DRAM is located between the MCU and the FPGA;

[0006] The MCU and FPGA are connected to the DRAM via a parallel 16-bit bus.

[0007] Furthermore, it also includes a control line multiplexing module, through which the MCU and FPGA can bidirectionally access the DRAM.

[0008] Furthermore, when the MCU and FPGA bidirectionally access the DRAM through the control line multiplexing module, the access requests of the MCU and FPGA to the DRAM are monitored through the timing control algorithm, and the control signal is dynamically switched between the two. The specific contents include:

[0009] S11, using the logic inside the FPGA to construct a request arbitration logic, and dynamically granting access rights to the MCU or FPGA according to a preset priority rule;

[0010] S12, through the DMA controller, directly transfer the data from the internal buffer of the MCU or FPGA to the address of the DRAM, or read the data from the DRAM to the specified buffer;

[0011] S13, using the programmable logic of the FPGA to generate precise timing control signals, determine the time to turn on and off the corresponding signals to perform DRAM read and write operations; after determining the access sequence and preparing the address and data, the control signal will be dynamically switched to allow the current device to perform read and write operations on the DRAM;

[0012] S14. After the control signal is correctly set, data will be transferred from MCU to DRAM for write operation, or from DRAM to FPGA for read operation.

[0013] Furthermore, it also includes a data exchange and synchronization module. The MCU writes data blocks into the DRAM in batches and sends a write completion signal to the FPGA through the control line. After receiving the signal, the FPGA reads the data from the DRAM for processing and feeds back a signal to the MCU after the processing is completed.

[0014] Furthermore, according to the data exchange and synchronization module, the dynamic data exchange and synchronization optimization algorithm optimizes the bidirectional data exchange process between the MCU and FPGA and the DRAM. The specific contents include:

[0015] S21. Use data flow analysis techniques to monitor data access patterns and obtain relevant information about how data flows along the program execution path by building control flow graphs and data flow graphs;

[0016] S22. Based on the results of data flow analysis, dynamically adjust the access priority to DRAM according to the real-time data processing requirements of MCU and FPGA through a dynamic scheduler; wherein the scheduler uses advanced data flow analysis technology to predict data access patterns and optimize access order;

[0017] S23. After optimizing the access order, the size and management strategy of the data block will be dynamically adjusted by implementing version control and conflict detection mechanisms according to the characteristics of the data and the current load situation.

[0018] Furthermore, the data transmission path is adjusted through the minimum cost maximum flow algorithm to optimize the data flow; specifically, by constructing a directed weighted graph, the data transmission solution with the lowest output cost while meeting the maximum flow is found, including:

[0019] Let G = (V, E) be a network, where V is the set of vertices, E is the set of edges, and each edge (u, υ) ∈ E has two properties: capacity c(u, υ) and cost per unit flow a(u, υ); flow f(u, υ) represents the amount of data passing through the edge (u, υ);

[0020] The goal of minimum cost maximum flow is to find a traffic allocation scheme f that maximizes the total flow from the source point s to the sink point t while minimizing the total cost. The minimum total cost B(f) is expressed as:

[0021]

[0022] Among them, f(u,υ) is the flow on edge (u,υ), and a(u,υ) is the unit flow cost of edge (u,υ).

[0023] Furthermore, the constraint of minimum cost maximum flow is expressed as:

[0024] Capacity restriction: for each edge (u,υ)∈E, 0≤f(u,υ)≤c(u,υ);

[0025] Flow conservation: For each vertex υ∈V\{s,t},

[0026] Σ (u，υ)∈E f(u,υ)=Σ (u，w)∈E f(u,υ);

[0027] Flow range: for all edges (u,υ)∈E, f(u,υ)≥0.

[0028] Furthermore, it also includes a network service support module, which transmits data through the network and stores it in DRAM. The FPGA accesses the DRAM in a time-sharing manner according to demand to obtain the required ink output data.

[0029] Furthermore, data is transmitted through the network and stored in DRAM. FPGA accesses DRAM in time-sharing according to demand. After obtaining the required ink output data, it also includes: FPGA uses edge computing technology to process the data received through the network in real time, stores the processing results in DRAM, and reads the data in time-sharing according to the specific needs of the printing task. Through the closed-loop control mechanism, FPGA monitors the processing results in real time after processing the data, and sends the processing status back to MCU through the feedback path to make adjustments.

[0030] A method for efficient data exchange for a digital inkjet printer, using the above-mentioned efficient data exchange system for a digital inkjet printer, comprises the following steps:

[0031] S1, Initialization: MCU and FPGA each initialize hardware resources, including registers, buffers and clocks;

[0032] S2, load configuration code: MCU and FPGA load their own configuration codes respectively;

[0033] S3, MCU sends data: For each data block transmitted, the MCU first calculates the address and activates the address auto-increment mode, then starts the write transfer operation and writes the data to the address; then, the MCU enables the FPGA to read the data in the address area;

[0034] S4, FPGA sends data: FPGA reads the data block at the specified address according to the instructions of MCU, and writes the data result back to the original address or a new address after completing the specified processing task; when new data is written, the old data will be overwritten.

[0035] The beneficial effects of the present invention are:

[0036] The present invention effectively solves the bandwidth bottleneck and data transmission rate mismatch problems in the traditional architecture by introducing high-speed DRAM as the data cache area between the microcontroller unit (MCU) and the field programmable gate array (FPGA); by using the control line multiplexing module and the timing control algorithm, the MCU and the FPGA can efficiently and synchronously access the DRAM in both directions, optimizing the continuity of the data flow and the smoothness of the printing process; the data exchange and synchronization module further ensures the batch rapid writing and reading of data blocks, and the dynamic data exchange and synchronization optimization algorithm dynamically adjusts the access priority according to the real-time data processing requirements and optimizes the access order; in addition, the use of the minimum cost maximum flow algorithm provides the lowest cost flow allocation solution for the data transmission path, The overall transmission cost is reduced and the utilization efficiency of network resources is improved; the network service support module enables the MCU to run the standard protocol stack, transmit data through the network and store it in DRAM, and the FPGA accesses the DRAM in a time-sharing manner according to demand to obtain the required ink output data, thereby enhancing the scalability and flexibility of the system; the FPGA uses edge computing technology to process the received data in real time, and monitors the processing results in real time through a closed-loop control mechanism, ensuring the accuracy of data processing and the continuity of printing tasks; the combination of these technologies not only improves printing quality and production efficiency, but also reduces the cost and complexity of hardware modifications, enabling the system to adapt to more complex application scenarios and meet the needs of modern digital inkjet printers for high-speed and large-data printing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0038] Figure 1 A schematic diagram of the structure of an efficient data exchange system for a digital inkjet printer provided in Example 1 of the present application;

[0039] Figure 2A flowchart of the steps of an efficient data exchange system for a digital inkjet printer provided in Example 1 of the present application to monitor access requests of MCU and FPGA to DRAM through a timing control algorithm;

[0040] Figure 3 A flowchart of the steps of an efficient data exchange method for a digital inkjet printer provided in Example 1 of the present application. DETAILED DESCRIPTION

[0041] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0042] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0043] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0044] Example 1

[0045] See also Figure 1-Figure 3 This embodiment provides an efficient data exchange system and method for a digital inkjet printer, introducing a high-speed dynamic random access memory (DRAM) chip as a data exchange medium between a microcontroller unit (MCU) and a field programmable gate array (FPGA), solving the problems of bandwidth bottleneck, data transmission rate mismatch and low system response speed existing in the traditional data bus architecture.

[0046] The invention provides an efficient data exchange system for a digital inkjet printer, comprising a microprocessor (MCU) and a field programmable gate array (FPGA), wherein the MCU, as a device controller, provides commands and buffer addresses and triggers automatic address increment; the FPGA is responsible for reading the buffer content and performing related processing; the FPGA includes a dynamic random access memory (DRAM) for storing print data. The DRAM is located between the MCU and the FPGA, and its reading and writing are controlled by the two, respectively.

[0047] Specifically, high-speed DRAM is introduced as the data cache between MCU and FPGA. Due to the difference in data processing speed between MCU and FPGA, direct data exchange will lead to rate mismatch, thus causing data congestion or delay. Through the high bandwidth characteristics of DRAM, MCU can quickly write the data to be processed into DRAM, while FPGA can read and process the data from DRAM, solving the rate mismatch problem. This step provides the basis for subsequent control line multiplexing and data exchange and synchronization.

[0048] Furthermore, the MCU and FPGA are connected to the DRAM via a parallel 16-bit bus.

[0049] Furthermore, it also includes a control line multiplexing module, which enables bidirectional access of MCU and FPGA to DRAM based on high-speed DRAM. This multiplexing mechanism allows MCU and FPGA to access DRAM in turn under different control signals, realizing efficient synchronous exchange of data. The multiplexing of control lines not only improves the utilization rate of DRAM, but also ensures the synchronous exchange of data between MCU and FPGA, providing precise timing control for the operation of data exchange and synchronization modules.

[0050] Furthermore, when the MCU and FPGA access the DRAM bidirectionally through the control line multiplexing module, the access requests of the MCU and FPGA to the DRAM are monitored through the timing control algorithm, and the control signal is dynamically switched between the two to achieve efficient alternating access to the DRAM; the specific contents include:

[0051] S11. Use the logic inside the FPGA to build a request arbitration logic, and dynamically grant access rights to the MCU or FPGA according to the preset priority rules. Specifically, the arbitrator is used to determine which request has a higher priority, thereby determining the access order. This arbitrator is implemented based on priority coding, and the one with the higher priority obtains the access right.

[0052] S12, through the DMA (direct memory access) controller, directly transfer the data from the internal buffer of the MCU or FPGA to the address of the DRAM, or read from the DRAM to the specified buffer; specifically, when the arbitrator determines which device (MCU or FPGA) obtains the access right, the device will prepare the address and data of the DRAM to be accessed, if it is a write operation, it will prepare the data; if it is a read operation, it will prepare the address of the data to be read;

[0053] S13. Use the programmable logic of the FPGA to generate control signals with precise timing, ensuring that the corresponding signals are turned on and off at the correct time to perform DRAM read and write operations; specifically, after the access order is determined and the address and data are prepared, the control signal will be dynamically switched to allow the current device to perform read and write operations on the DRAM. Use the programmable logic of the FPGA to generate control signals with precise timing, ensuring that the corresponding signals are turned on and off at the correct time to perform DRAM read and write operations;

[0054] S14, after the control signal is correctly set, the data will be transferred from the MCU to the DRAM (write operation), or from the DRAM to the FPGA (read operation). This step requires precise timing control to ensure data integrity.

[0055] Specifically, through the timing control algorithm, MCU and FPGA achieve efficient bidirectional data access to DRAM. Through precise timing management and dynamic control signal switching, it ensures that when transmitting large amounts of data at high speed, MCU and FPGA can not only coordinately share DRAM resources, but also ensure the continuity and accuracy of data transmission, thereby significantly improving the overall performance and data processing capabilities of the system. In addition, the algorithm also reduces system energy consumption and improves energy efficiency by optimizing data flow and reducing system resource waste, meeting the needs of modern digital inkjet printers for high-speed, large-volume printing tasks.

[0056] Furthermore, it also includes a data exchange and synchronization module, which further optimizes the data exchange process based on the control line multiplexing module. The MCU writes the data blocks into the DRAM in batches and sends a write completion signal to the FPGA through the control line. After receiving the signal, the FPGA immediately reads the data from the DRAM for processing and feeds back the signal to the MCU after the processing is completed. This mode of asynchronous transmission and synchronous exchange ensures the continuity of the data flow and the smoothness of the printing process through the intermediary role of DRAM, greatly improving the parallel processing capability of the system.

[0057] Furthermore, according to the data exchange and synchronization module, the dynamic data exchange and synchronization optimization algorithm further optimizes the bidirectional data exchange process between MCU and FPGA and DRAM, including:

[0058] S21. Use data flow analysis techniques to monitor data access patterns. This is achieved by building control flow graphs (CFGs) and data flow graphs to obtain information about how data flows along the program execution path. The purpose of data flow analysis is to infer information about the dynamic execution of the program through static code, thereby providing the algorithm with a global view of data access.

[0059] S22. Based on the result of data flow analysis, dynamically adjust the access priority to DRAM according to the real-time data processing requirements of MCU and FPGA through a dynamic scheduler; wherein the scheduler uses advanced data flow analysis technology to predict data access patterns and optimize the access order accordingly;

[0060] S23. After optimizing the access order, the size and management strategy of the data block will be dynamically adjusted by implementing version control and conflict detection mechanisms based on the characteristics of the data (such as size, frequency, type) and the current load of the system; while ensuring data consistency, the data access order will be optimized.

[0061] Specifically, through the Dynamic Data Exchange and Synchronization Optimization Algorithm, the bidirectional data exchange process between MCU and FPGA and DRAM has been significantly optimized. This algorithm first uses data flow analysis technology (such as S21 technology) to monitor data access patterns, and builds control flow graphs (CFGs) and data flow graphs to provide the algorithm with a global view of data access. Then, based on the analysis results, the dynamic scheduler dynamically adjusts the access priority to DRAM and optimizes the access order according to the real-time data processing requirements of MCU and FPGA. After that, according to the characteristics of the data and the current load, through version control and conflict detection mechanisms, the size and management strategy of the data block are dynamically adjusted to ensure data consistency while optimizing the data access order. The system not only improves the efficiency and accuracy of data transmission, but also enhances scalability and flexibility, supports more complex network services and data processing functions, and reduces the cost and complexity of hardware changes.

[0062] Furthermore, the data transmission path is adjusted through the minimum cost maximum flow algorithm to further optimize the data flow; specifically, by constructing a directed weighted graph, the data transmission solution with the lowest cost while meeting the maximum flow is found. This method can reduce the overall cost of data transmission and improve the utilization efficiency of network resources, including:

[0063] Let G = (V, E) be a network, where V is the set of vertices, E is the set of edges, and each edge (u, υ) ∈ E has two properties: capacity c(u, υ) and cost per unit flow a(u, υ); flow f(u, υ) represents the amount of data passing through the edge (u, υ);

[0064] The goal of minimum cost maximum flow is to find a traffic allocation scheme f that maximizes the total flow from the source point s to the sink point t while minimizing the total cost. The minimum total cost B(f) is expressed as:

[0065]

[0066] Among them, f(u,υ) is the flow on edge (u,υ), and a(u,υ) is the unit flow cost of edge (u,υ).

[0067] Specifically, by applying the minimum cost maximum flow algorithm, the data transmission path can be effectively adjusted to minimize the overall transmission cost while maximizing the data flow. Specifically, by constructing a directed weighted graph, each edge represents a potential data transmission channel with two attributes: capacity and unit flow cost. By iteratively searching for the augmenting path with the minimum cost, the algorithm gradually optimizes the data flow until the maximum flow is reached. This method not only reduces the overall cost of data transmission, but also improves the utilization efficiency of network resources. The purpose of optimizing data flow through the minimum cost maximum flow algorithm is to adapt to more complex network services and data processing requirements, and to ensure that data can flow efficiently and at low cost in high-speed printing tasks, thereby improving printing quality and production efficiency.

[0068] Furthermore, the constraint of minimum cost maximum flow is expressed as:

[0069] Capacity restriction: for each edge (u,υ)∈E, 0≤f(u,υ)≤c(u,υ);

[0070] Flow conservation: For each vertex υ∈V\{s,t},

[0071] ∑ (u，υ)∈E f(u,υ)=∑ (υ，w)∈E f(υ,w);

[0072] Flow range: for all edges (u,υ)∈E, f(u,υ)≥0.

[0073] Specifically, u is the starting vertex of the edge, v is the ending vertex of the edge, and each edge (u, v) represents a directed connection from one vertex to another, and this connection has associated capacity and cost attributes. In this network, data can flow from u to v, but not in the reverse direction.

[0074] By solving this optimization problem, we can find a path from the source point s to the sink point t, which maximizes the flow on this path and minimizes the total cost. We can find the path with the minimum cost growth through an iterative algorithm and gradually increase the flow until we can no longer increase the flow.

[0075] Furthermore, it also includes a network service support module, which uses the increased bandwidth to enable the MCU to run a standard protocol stack, transmit data over the network and store it in DRAM. The FPGA accesses the DRAM in a time-sharing manner according to demand to obtain the required ink output data. This module not only enhances the scalability and flexibility of the system, but also supports more complex network services and data processing functions, such as receiving print tasks over the network and storing them directly in DRAM for FPGA processing. This design enables the system to adapt to more complex application scenarios while reducing the cost and complexity of hardware changes.

[0076] Furthermore, after transmitting data through the network and storing it in DRAM, FPGA accesses DRAM in time-sharing according to demand, and obtains the required ink output data, it also includes: FPGA uses edge computing technology to process the data received through the network in real time, stores the processing results in DRAM, and reads the data in time-sharing according to the specific needs of the printing task. Through the closed-loop control mechanism, FPGA can monitor the processing results in real time after processing the data, and send the processing status back to MCU through the feedback path to make necessary adjustments to ensure the accuracy of data processing and the continuity of printing tasks. MCU makes decisions based on the feedback from FPGA, dynamically adjusts subsequent data transmission and processing strategies, and forms an efficient closed-loop control system, thereby optimizing the entire printing process and improving response speed and processing efficiency.

[0077] Specifically, the efficient data exchange system of the present invention is aimed at the MCU and FPGA in the digital inkjet printer, and solves the rate matching problem between them by introducing high-speed DRAM as the data cache area, realizes bidirectional data access by using control line multiplexing technology, and dynamically manages the access requests of MCU and FPGA to DRAM through the timing control algorithm, thereby optimizing the continuity of data flow and the parallel processing capability of the system. In addition, the system uses data flow analysis technology to monitor and predict data access patterns, dynamically adjusts the data block size and access priority, optimizes the data transmission path through the minimum cost maximum flow algorithm, reduces costs and improves network resource utilization. Finally, combined with edge computing technology, FPGA can process data received through the network in real time, and work with MCU through a closed-loop control mechanism to dynamically adjust data transmission and processing strategies to adapt to complex network services and data processing requirements, improve printing quality and efficiency, and reduce the cost and complexity of hardware changes.

[0078] A method for efficient data exchange for a digital inkjet printer, using the above-mentioned efficient data exchange system for a digital inkjet printer, comprises the following steps:

[0079] S1, Initialization: MCU and FPGA each initialize hardware resources, including registers, buffers and clocks;

[0080] S2, load configuration code: MCU and FPGA load their own configuration codes respectively;

[0081] S3, MCU sends data: For each data block transmitted, the MCU first calculates the address and activates the address auto-increment mode, then starts the write transfer operation and writes the data to the address; then, the MCU enables the FPGA to read the data in the address area;

[0082] S4, FPGA sends data: FPGA reads the data block at the specified address according to the instructions of MCU, and writes the data result back to the original address or a new address after completing the specified processing task; when new data is written, the old data will be overwritten.

[0083] In the present invention, by introducing high-speed DRAM as a data cache area and optimizing the data transmission architecture between MCU and FPGA, the bandwidth bottleneck problem of the traditional data bus is effectively solved, so that the overall system response speed and printing efficiency of the digital inkjet printer are greatly improved; the control line multiplexing technology is adopted to ensure that the data exchange between MCU and FPGA can be carried out efficiently and synchronously, significantly reducing the delay of data transmission, improving the continuity of data flow and the smoothness of the printing process, and the new architecture allows the high bandwidth characteristics of DRAM to support higher data transmission rates and more complex application scenarios without changing the hardware, while reducing the cost and complexity of hardware changes. This provides convenience for future system upgrades and function expansions; optimized data flow management reduces the waste of system resources, reduces energy consumption, and achieves higher energy efficiency. It is in line with the development direction of green environmental protection technology and provides technical support for the sustainable development of modern digital inkjet printers; through the efficient data exchange mechanism and the improvement of real-time processing capabilities, the printer can better control the ink output and printing accuracy, thereby improving the quality of print output and meeting high-end printing needs.

[0084] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. An efficient data exchange system for a digital inkjet printer, characterized in that: It includes an MCU and an FPGA, wherein the MCU, as a device controller, provides commands and buffer addresses and triggers the address to automatically increase; the FPGA is responsible for reading the buffer content and performing related processing; and it also includes a DRAM for storing print data; The DRAM is located between the MCU and the FPGA.

2. The efficient data exchange system for a digital inkjet printer according to claim 1, characterized in that: It also includes a control line multiplexing module, through which the MCU and FPGA can bidirectionally access the DRAM.

3. The efficient data exchange system for a digital inkjet printer according to claim 2, characterized in that: When the MCU and FPGA access the DRAM bidirectionally through the control line multiplexing module, the access request of the MCU and FPGA to the DRAM is monitored through the timing control algorithm, and the control signal is dynamically switched between the two. The specific contents include: S11, using the logic inside the FPGA to construct a request arbitration logic, and dynamically granting access rights to the MCU or FPGA according to a preset priority rule; S12, through the DMA controller, directly transfer the data from the internal buffer of the MCU or FPGA to the address of the DRAM, or read the data from the DRAM to the specified buffer; S13, using the programmable logic of the FPGA to generate precise timing control signals, determine the time to turn on and off the corresponding signals to perform DRAM read and write operations; after determining the access sequence and preparing the address and data, the control signal will be dynamically switched to allow the current device to perform read and write operations on the DRAM; S14. After the control signal is correctly set, data will be transferred from MCU to DRAM for write operation, or from DRAM to FPGA for read operation.

4. The efficient data exchange system for a digital inkjet printer according to claim 1, characterized in that: It also includes a data exchange and synchronization module. The MCU writes data blocks into the DRAM in batches and sends a write completion signal to the FPGA through a control line. After receiving the signal, the FPGA reads the data from the DRAM for processing and feeds back a signal to the MCU after the processing is completed.

5. The efficient data exchange system for a digital inkjet printer according to claim 4, characterized in that: According to the data exchange and synchronization module, the dynamic data exchange and synchronization optimization algorithm optimizes the bidirectional data exchange process between MCU and FPGA and DRAM. The specific contents include: S21. Use data flow analysis techniques to monitor data access patterns and obtain relevant information about how data flows along the program execution path by building control flow graphs and data flow graphs; S22. Based on the results of data flow analysis, dynamically adjust the access priority to DRAM according to the real-time data processing requirements of MCU and FPGA through a dynamic scheduler; wherein the scheduler uses advanced data flow analysis technology to predict data access patterns and optimize access order; S23. After optimizing the access order, the size and management strategy of the data block will be dynamically adjusted by implementing version control and conflict detection mechanisms according to the characteristics of the data and the current load situation.

6. The efficient data exchange system for a digital inkjet printer according to claim 5, characterized in that: The data transmission path is adjusted through the minimum cost maximum flow algorithm to optimize the data flow; Specifically, by constructing a directed weighted graph, we can find the data transmission solution with the lowest output cost while meeting the maximum flow. Specifically, it includes: Let G = (V, E) be a network, where V is the set of vertices, E is the set of edges, and each edge (u, v) ∈ E has two properties: capacity c(u, v) and cost per unit flow a(u, v); flow f(u, v) represents the amount of data passing through edge (u,). The goal of minimum cost maximum flow is to find a traffic allocation scheme f that maximizes the total flow from the source point s to the sink point t while minimizing the total cost. The minimum total cost B(f) is expressed as: Among them, f(u, v) is the flow on edge (u, v), and a(u, v) is the unit flow cost of edge (u, v).

7. The efficient data exchange system for a digital inkjet printer according to claim 6, characterized in that: The constraints of minimum cost maximum flow are expressed as: Capacity restriction: for each edge (u, v)∈E, 0≤f(u, v)≤c(u, v); Flow conservation: For each vertex v∈V\{s,t}, ∑ (u，v)∈E f(u,v)=∑ (v，w)∈E f(v,w); Flow range: for all edges (u, ν)∈E, f(u, v) ≥ 0.

8. The efficient data exchange system for a digital inkjet printer according to claim 1, characterized in that: It also includes a network service support module, which transmits data through the network and stores it in DRAM. The FPGA accesses the DRAM in a time-sharing manner according to demand to obtain the required ink output data.

9. The efficient data exchange system for a digital inkjet printer according to claim 8, characterized in that: Data is transmitted over the network and stored in DRAM. FPGA accesses DRAM in time-sharing according to demand. After obtaining the required ink output data, it also includes: FPGA uses edge computing technology to process the data received through the network in real time, stores the processing results in DRAM, and reads the data in time-sharing according to the specific needs of the printing task. Through the closed-loop control mechanism, FPGA monitors the processing results in real time after processing the data, and sends the processing status back to MCU through the feedback path for adjustment.

10. An efficient data exchange method for a digital inkjet printer, applied to an efficient data exchange system for a digital inkjet printer as claimed in any one of claims 1 to 9, characterized in that: The following steps are involved: S1, Initialization: MCU and FPGA each initialize hardware resources, including registers, buffers and clocks; S2, load configuration code: MCU and FPGA load their own configuration codes respectively; S3, MCU sends data: For each data block transmitted, the MCU first calculates the address and activates the address auto-increment mode, then starts the write transfer operation and writes the data to the address; then, the MCU enables the FPGA to read the data in the address area; S4, FPGA sends data: FPGA reads the data block at the specified address according to the instructions of MCU, and writes the data result back to the original address or a new address after completing the specified processing task; when new data is written, the old data will be overwritten.

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