Flight control computer telemetering analog quantity collecting and editing circuit

Abstract

The invention belongs to the technical field of analog signal collection, and discloses a flight control computer telemetering analog quantity collecting and editing circuit which comprises an input signal conditioning circuit, an analog switch circuit, a voltage following circuit, an ADC sampling circuit, an FPGA master control module circuit and a PCM sending circuit. And after passing through the two voltage following circuits, the signal is output to the two analog-to-digital converters for time-sharing ping-pong alternate sampling, and then the signal is output to the FPGA main control module circuit by adopting a serial interface, and is output in an RS485 signal form after being isolated by a digital isolator. The invention has the advantages of bipolar and wide input range, avoids the measurement error caused by signal amplitude scaling, reduces the measurement error caused by the output impedance of a pre-stage circuit to the ADC sampling hold circuit, improves the sampling precision and the sampling speed, and also reduces the I / O resource occupancy rate of an FPGA (Field Programmable Gate Array).

Description

Technical Field

[0001] The invention belongs to the technical field of analog signal acquisition, and specifically discloses a flight control computer telemetry analog quantity acquisition and editing circuit. Background Art

[0002] With the continuous improvement of modern system functional requirements, the flight control computer, as the control core, not only needs to collect more and more telemetry information, but also puts forward more stringent requirements on the input range, collection accuracy, collection speed, real-time processing and encoded transmission capabilities of the telemetry information.

[0003] The commonly used flight control computer telemetry analog quantity acquisition and editing circuits currently include the following three types:

[0004] The first is to use an operational amplifier (op amp for short) as a conditioning circuit, and the output of the op amp is connected to an analog switch combination for channel selection. After the analog switch, the analog signal is directly converted into a digital signal using an analog-to-digital converter (ADC for short), and sent to the main control chip FPGA for framing processing, and then output through the RS422 interface. This type of telemetry analog quantity acquisition circuit was used in the article "Design of Missile-borne Telemetry Anti-Destruction Collection and Storage System" published by Bao Aida et al. in "Computer Measurement and Control" Volume 29, Issue 11, Pages 122-126 in 2021. Because it uses op amps to adjust the analog input signal range, it supports a larger input range, but it also leads to an increase in the number and cost of op amps during multi-channel acquisition. At the same time, the design uses imported devices. Limited by the current foreign technical blockade of high-performance op amps and ADC products, it is impossible to ensure the normal procurement needs and technical iteration updates of subsequent product production, and the maximum transmission rate after framing of 56-channel analog sampling is 5.28Mbps.

[0005] The second is to use a resistor array voltage divider to proportionally reduce the amplitude of the input analog signal, and then collect it through analog switches, op amps, and ADCs in sequence. The utility model patent "A Space Equipment Analog Telemetry Circuit System" applied for by Li Hanqing and others in 2019 introduced this type of telemetry analog acquisition circuit. The design uses two 20kΩ resistors for voltage division. The advantage is that the circuit is simple, but considering the inherent resistance deviation of the resistor, a larger error will be introduced after voltage division, and the consistency between multiple channels is low. Therefore, it is suitable for occasions requiring lower sampling accuracy. At the same time, the core components used in this circuit are all imported components.

[0006] The third is to use an SOC chip with an internal integrated XADC conversion module instead of ADC for collection. The invention patent "A micro telemetry collector and method based on SoC technology" applied for by Gao Junlu and others in 2021 introduced this type of telemetry analog quantity acquisition circuit. The use of an SOC chip with an integrated XADC conversion module can reduce the board layout area, but the SOC is currently mainly used in the imported Xilinx company's Zynq7000 series. The input range of the XADC inside the SOC is generally 0~1V. For the analog quantity acquisition with an input range of only 0~5V in the present invention, the input range needs to be adjusted in the switching submodule, and the maximum transmission rate after framing of 64-channel analog quantity sampling only supports 2.5Mbps.

[0007] The existing flight control computer telemetry analog quantity acquisition and editing circuit has limited applicability and can no longer meet the rapid development needs of flight control computers under the current situation. Summary of the invention

[0008] 1. Technical issues to be resolved

[0009] The purpose of the present invention is to propose a flight control computer telemetry analog quantity acquisition and editing circuit that is not subject to foreign technology blockade and can support subsequent mass production. It can not only support multi-channel, bipolar, wide range, and high-precision input analog quantity acquisition, but also can perform real-time processing and frame encoding of the converted analog quantity for rapid output.

[0010] (II) Technical solution

[0011] A flight control computer telemetry analog quantity collection and editing circuit comprises an input signal conditioning circuit, an analog switch circuit, a voltage follower circuit, an ADC sampling circuit, an FPGA main control module circuit and a PCM sending circuit, wherein the telemetry analog quantity is input into the input signal conditioning circuit, and the input signal conditioning circuit comprises a grounded resistor R1 and a low-pass filter composed of a resistor R2 and a capacitor C1; the telemetry analog quantity is sent to the primary analog switch after passing through the input signal conditioning circuit, and then sent to the secondary analog switch, and then sent to two voltage follower circuits after passing through the secondary analog switch, and after passing through the two voltage follower circuits, the signal is output to two analog-to-digital converters for time-sharing ping-pong alternating sampling, and then output to the FPGA main control module circuit using a serial interface, and the FPGA main control module circuit comprises an ADC collection control module, a PCM framing module and a PCM sending control module; after the telemetry analog quantity is framed and encoded inside the FPGA main control module circuit, it is isolated by a digital isolator and then input into an RS485 transmitter and output in the form of RS485 signals.

[0012] Furthermore, the first-level analog switch is composed of 6 16-channel-to-1 analog multiplexers, the 1st to 15th channels of the first 5 multiplexers are respectively connected to 1 conditioned analog signal, the 16th channel of the first 5 multiplexers is kept pulled down to ground, the 1st to 3rd channels of the 6th multiplexer are connected to the 76th to 78th conditioned analog signals in sequence, and the 16th channel of the 6th multiplexer is pulled down to ground; the output ends of the 6 first-level analog switches are connected to the 1st to 6th channel inputs of a second-level analog switch in sequence, and 1 output of the second-level analog switch is used as the output; the independent enable signal of the two-level analog switch, the common 4-bit address selection signal of the first-level analog switch, and the 4-bit address selection signal of the second-level analog switch are controlled by the FPGA main control module circuit.

[0013] Furthermore, the voltage follower circuit includes a current feedback operational amplifier, the output of the secondary analog switch is connected to the non-inverting input terminal of the current feedback operational amplifier after being connected to a series resistor, the inverting input terminal of the current feedback operational amplifier is connected to the output terminal of the operational amplifier in series with a feedback resistor, and a series resistor is connected between the output terminal of the operational amplifier and the subsequent ADC acquisition control module.

[0014] Furthermore, the FPGA main control module circuit includes an FPGA chip JFM7K325T, the current feedback operational amplifier model is SX811MF, the analog-to-digital converter model is HWD7891, the digital isolator model is GLc1200p, and the RS485 transmitter model is SW96F174MC.

[0015] (III) Beneficial effects

[0016] Compared with the prior art, the technical solution proposed in the present invention uses fully domestically produced devices, thereby improving the autonomous controllability of the product; a multi-channel analog switch, operational amplifier, and ADC are used to directly sample telemetry analog signals within a voltage input range of ±10V, thereby having the advantages of bipolarity and a wide input range while avoiding measurement errors introduced during signal amplitude scaling; in order to achieve rapid output of analog acquisition and editing signals, a current feedback high-speed operational amplifier with a high conversion rate is used as a voltage follower, thereby reducing the measurement error introduced by the output impedance of the front-stage circuit to the ADC sampling and holding circuit, thereby improving the sampling accuracy; the time-sharing ping-pong alternating sampling of the two ADCs improves the sampling speed, and the serial output of the ADC reduces the I / O resource occupancy rate of the FPGA, while verifying that the acquisition error of 78 analog channels is less than 2%, and the maximum output rate after acquisition and editing is 6.5536Mbps. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the circuit principle for collecting and editing the remote sensing analog quantity of the flight control computer of the present invention;

[0018] Figure 2A flow chart for collecting and editing telemetry analog quantities for each channel of the present invention;

[0019] Figure 3 This is a flow chart of the time-sharing ping-pong alternating collection and editing of two ADCs of the present invention;

[0020] Figure 4 This is a statistical diagram of the error in the telemetry analog quantity collection of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0022] Figure 1 This is a principle block diagram of the flight control computer telemetry analog quantity collection and editing circuit of the technical solution of the present invention, which includes an input signal conditioning circuit, an analog switch circuit, a voltage follower circuit, an ADC sampling circuit, an FPGA main control module circuit, a PCM sending circuit, etc. Combined with its application scenario in the flight control computer, each circuit module is specifically as follows:

[0023] The telemetry analog input is usually the voltage output of various equipment information and sensors that characterize the status of the aircraft. After being processed by the front-end module, it is sent to the flight control computer as a voltage signal with an input range of ±10V. For each telemetry analog input signal, it is first pulled down to the reference ground through a resistor R1 with a large resistance value. R1 provides a current discharge path. Then the high-frequency interference signal is filtered out through a low-pass filter composed of R2 and C1. The value of R2 here needs to avoid a large input current of the subsequent analog switch, and at the same time reduce the impact of the charge recoil of the analog switch on the input signal when switching. The value of C1 should not be too small, and the role of timely power supply when the subsequent analog switch switches quickly should be considered. R1, R2, and C1 together form the input signal conditioning circuit, and the 78-channel telemetry analog input signal conditioning circuit remains consistent.

[0024] The telemetry analog quantity is directly sent to the first-level analog switch after the input signal conditioning circuit. The first-level analog switch consists of 6 16-channel 1-select analog multiplexers HCE506S, with an input range of ±15V. The 1st to 15th channels of the first 5 multiplexers are each connected to 1 conditioned analog signal, and the 16th channel is kept pulled down to the ground. The 1st to 3rd channels of the 6th multiplexer are connected to the 76th to 78th conditioned analog signals in turn, and the 16th channel is also pulled down to the ground. The output ends of the 6 first-level analog switches are connected to the 1st to 6th channel inputs of a second-level analog switch in turn, and the 1st output of the second-level analog switch is used as the final output to ensure that the 78 analog quantities have the same transmission path impedance and channel delay. The FPGA chip controls the independent enable signal of the two-level analog switch, the 4-bit address selection signal of the first-level analog switch, and the 4-bit address selection signal of the second-level analog switch to achieve time-sharing selection of any one of the 78 conditioned analog signals, while reducing the number of components required for the subsequent circuits.

[0025] In order to reduce the influence of the source resistance of the telemetry analog quantity on the sampling error of the subsequent ADC, a voltage follower is used to achieve low-resistance output to reduce the ADC measurement error. At the same time, considering the purpose of achieving the maximum transmission rate of 6.5536Mbps for pulse code modulation (PCM) after framing, the time to transmit one byte is 1.22us. Figure 1 Circuit principle block diagram, this time includes: analog switch switching and transmission delay, op amp transmission delay, ADC read / write delay and data conversion delay, PCM framing delay. Considering that the time from switching the analog switch to sending the start conversion command is 635ns, the output stabilization delay of the analog switch is about 200ns, considering that the ADC tracking / holding is about 400ns when the maximum voltage changes to 20V, the op amp follow-up output is completed within 35ns, and the required op amp conversion rate is 572V / us. In order to meet the op amp transmission delay, the current feedback high-speed op amp SX811MF is used as a voltage follower, making full use of its advantages of ±12V wide output swing and 2500V / us high conversion rate. The output of the secondary analog switch is connected to the non-inverting input of the two op amps after the series resistor R3, and the inverting input of the two op amps is connected to the feedback resistors R4 and R5 in series and then connected to the op amp output to achieve a voltage follower with a gain of 1. Resistors R6 and R7 are connected in series between each voltage follower and the subsequent ADC. R6 and R7 are used to compensate for the output signal peak overshoot caused by large load capacitance.

[0026] After the voltage follower circuit, the signal is output to two analog-to-digital converters HWD7891. HWD7891 supports ±10V input and uses a serial interface to output to the FPGA chip JFM7K325T, reducing the I / O resource occupancy of the FPGA.

[0027] In order to reduce the ADC read / write delay and data conversion delay, two analog-to-digital converters HWD7891 are used to perform time-sharing ping-pong alternating sampling.

[0028] Figure 2 Describes the process of collecting and editing telemetry analog quantities for each channel. Figure 3 The process of alternating the time-sharing ping-pong between two ADCs is further described. The detailed working principle is as follows:

[0029] Step 1: According to the frame format used, the FPGA first controls the analog switch to switch to the specified channel n. This process takes 50ns. After a delay of 135ns, the FPGA sends the read instruction to ADC1 when it was previously switched to channel n-2. After a delay of 500ns, the FPGA sends the start conversion instruction of ADC1 when it is switched to channel n this time. After the analog switch is switched, the 635ns delay can ensure that the voltage tracked / held by ADC1 at this time is stable. It takes 300ns to send the start conversion instruction, after which ADC1 starts to convert. The conversion is completed after 1.64us. Then, the read instruction of ADC1 for channel n is sent. After 800ns, the telemetry analog sampling data of the currently switched channel n can be obtained. After the above-mentioned sending of the read instruction when switching to channel n-2, it takes 800ns to obtain the telemetry analog sampling data of the currently switched channel n-2, and then it takes about 235ns to complete the PCM framing.

[0030] Step 2: Repeat the above steps, it takes 50ns to complete the frame format reading, switch to the analog switch channel n+1, send the ADC2 read instruction of channel n-1, send the ADC2 start conversion instruction of channel n+1, obtain the ADC2 telemetry analog quantity sampling data of channel n-1, and it takes 235ns to complete the PCM framing.

[0031] Step 3: Repeat the process of step 1 and step 2. When the analog switch is switched to channel n, ADC1 reads the sampled data of channel n-2. When it is switched to channel n+1, ADC2 reads the sampled data of channel n-1. When it is switched to channel n+2, ADC1 reads the sampled data of channel n. When it is switched to channel n+3, ADC2 reads the sampled data of channel n+1, and so on. The analog switch switching and ADC acquisition are realized within a 1.22us period. Figure 4 Select any 21 consecutive channels and input telemetry analog quantities of -10V to 10V with an interval of 1V in sequence. The horizontal axis is the input voltage amplitude and the vertical axis is the relative error percentage of the measured voltage. According to statistics, the minimum relative error percentage of the measured voltage is 0.02% and the maximum is 1.33%.

[0032] The ADC acquisition results pass through the PCM framing module and PCM sending control module in the FPGA main control module circuit, and are isolated and output after being transmitted by the digital isolator GLc1200p and RS485 transmitter SW96F174MC in the PCM sending circuit, achieving a maximum PCM transmission rate of 6.5536Mbps after framing.

[0033] During specific implementation, the flight control computer telemetry analog quantity acquisition and editing circuit can be further optimized, including but not limited to: using an ADC with a higher sampling rate to further reduce the time required for ADC acquisition, thereby increasing the output rate after PCM framing; using an ADC with a higher resolution to reduce sampling errors and other measures.

[0034] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A flight control computer telemetry analog quantity acquisition and editing circuit, characterized in that: The invention comprises an input signal conditioning circuit, an analog switch circuit, a voltage follower circuit, an ADC sampling circuit, an FPGA main control module circuit and a PCM sending circuit, wherein the telemetry analog quantity is input into the input signal conditioning circuit, and the input signal conditioning circuit comprises a grounded resistor R1 and a low-pass filter composed of a resistor R2 and a capacitor C1; the telemetry analog quantity is sent to the primary analog switch after passing through the input signal conditioning circuit, and then sent to the secondary analog switch, and then sent to the two-way voltage follower circuit after passing through the secondary analog switch, and after passing through the two-way voltage follower circuit, the signal is output to two analog-to-digital converters for time-sharing ping-pong alternating sampling, and then output to the FPGA main control module circuit through a serial interface, and the FPGA main control module circuit comprises an ADC acquisition control module, a PCM framing module and a PCM sending control module; after the telemetry analog quantity is framed and encoded inside the FPGA main control module circuit, it is isolated by a digital isolator and then input into an RS485 transmitter and output in the form of an RS485 signal.

2. A flight control computer telemetry analog quantity acquisition and editing circuit as claimed in claim 1, characterized in that: The primary analog switch is composed of 6 16-channel 1-select analog multiplexers, the 1st to 15th channels of the first 5 multiplexers are respectively connected to 1 conditioned analog signal, the 16th channel of the first 5 multiplexers is kept pulled down to ground, the 1st to 3rd channels of the 6th multiplexer are connected to the 76th to 78th conditioned analog signals in sequence, and the 16th channel of the 6th multiplexer is pulled down to ground; the output ends of the 6 primary analog switches are connected to the 1st to 6th channel inputs of 1 secondary analog switch in sequence, and 1 output of the secondary analog switch is used as the output; The FPGA main control module circuit controls the independent enable signals of the two-stage analog switches, the 4-bit address selection signal common to the first-stage analog switch, and the 4-bit address selection signal of the second-stage analog switch.

3. A flight control computer telemetry analog quantity acquisition and editing circuit as claimed in claim 2, characterized in that: The voltage follower circuit includes a current feedback operational amplifier, the output of the secondary analog switch is connected to the non-inverting input terminal of the current feedback operational amplifier after passing through a series resistor, the inverting input terminal of the current feedback operational amplifier is connected in series with a feedback resistor and then connected to the output terminal of the operational amplifier, and a resistor is connected in series between the output terminal of the operational amplifier and the subsequent ADC acquisition control module.

4. A flight control computer telemetry analog quantity acquisition and editing circuit as claimed in claim 3, characterized in that: The FPGA main control module circuit includes an FPGA chip JFM7K325T, the current feedback operational amplifier model is SX811MF, the analog-to-digital converter model is HWD7891, the digital isolator model is GLc1200p, and the RS485 transmitter model is SW96F174MC.

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