Preparation method of epitaxial wafer and semiconductor device comprising epitaxial wafer

Abstract

The invention discloses a preparation method of an epitaxial wafer and a semiconductor device comprising the epitaxial wafer. The method comprises the following steps: providing a substrate; sequentially epitaxially growing a laminated structure comprising an N-type layer, a light-emitting layer and a middle layer on the substrate; the stacked structure is pretreated, the pretreatment at least comprises a first step, and the first step comprises the steps that after an Mg source is introduced into the reaction chamber, thermal annealing treatment is carried out under a first condition; the first condition at least comprises a first annealing temperature; after pretreatment, epitaxially growing a P-type layer on the intermediate layer of the laminated structure; the first annealing temperature is higher than the growth temperature of the P-type layer, and the middle layer has the function of preventing Mg from diffusing into the light-emitting layer in the pretreatment process. According to the preparation method, the problem that P-type structure doping is difficult to reach the doping concentration set by the process due to the Mg doping memory effect is solved, the brightness and the antistatic release performance of the epitaxial wafer are improved, and the luminous efficiency of the epitaxial wafer is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing an epitaxial wafer and a semiconductor device comprising the epitaxial wafer. Background Art

[0002] As an excellent wide bandgap semiconductor material, GaN has great potential in the manufacture of optoelectronic and microelectronic devices. It can be applied to high-power, high-temperature and high-frequency electronic devices and high-brightness LEDs (Light-Emitting Diodes), and is known as the third-generation semiconductor material.

[0003] Although GaN materials have been systematically and deeply studied, they still face many problems. The important bottleneck facing research and development is the control of p-type GaN doping. Obtaining p-type GaN materials with good performance is a key factor in realizing the above-mentioned devices. Mg dopants have high ionization energy, so in order to obtain a high carrier concentration, the doping concentration of Mg atoms will be increased. However, Mg itself has a memory effect, which causes Mg atoms to deposit on the side walls and top of the reaction chamber. It is difficult to obtain an epitaxial layer with a high doping concentration in the early stage of growth, which makes it difficult to achieve the requirements of the epitaxial growth process, which seriously affects the optoelectronic performance of the epitaxial wafer.

[0004] The present invention solves at least one of the above problems. Summary of the invention

[0005] The purpose of the present invention is to provide a method for preparing an epitaxial wafer, which is used to solve the problem that the P-type structure doping caused by the Mg doping memory effect is difficult to reach the doping concentration set by the process. The brightness and anti-static release performance of the epitaxial wafer are improved, and the luminous efficiency of the epitaxial wafer is guaranteed.

[0006] The purpose of the present invention is achieved by the following technical solutions:

[0007] A first aspect of the present invention provides a method for preparing an epitaxial wafer, comprising:

[0008] providing a substrate;

[0009] epitaxially growing a stacked structure including an N-type layer, a light-emitting layer and an intermediate layer in sequence on the substrate;

[0010] Pre-treating the stacked structure, the pre-treating comprising at least a first step, the first step comprising: after introducing a Mg source into a reaction chamber, performing a thermal annealing treatment under a first condition; the first condition comprising at least a first annealing temperature;

[0011] After pretreatment, epitaxially growing a P-type layer on the middle layer of the stacked structure;

[0012] The intermediate layer has the function of preventing Mg and / or the doping material in the P-type layer from diffusing into the light-emitting layer during the pretreatment process; and the first annealing temperature is higher than the growth temperature of the P-type layer.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: under high temperature conditions, during the heat treatment process, it is beneficial for the Mg source to react and deposit on the side walls and top of the reaction chamber cavity and reach a stable state. While reducing the occurrence of the Mg atom memory effect, it can well avoid the occurrence of Mg atom decomposition during the growth of the P-type layer, thereby maintaining the stability of the growth process. At the same time, the intermediate layer is used to prevent Mg from diffusing into the light-emitting layer during the heat treatment process, thereby jointly solving the problem that the P-type structure doping caused by the Mg doping memory effect is difficult to reach the doping concentration set by the process, thereby improving the brightness and anti-static release performance of the epitaxial wafer and ensuring the luminous efficiency of the epitaxial wafer.

[0014] In some possible implementations, the pretreatment further includes a second step that is repeated and cyclically alternating with the first step, the second step including: after interrupting the introduction of the Mg source into the reaction chamber, performing a thermal annealing treatment under a second condition, the second condition including at least a second annealing temperature;

[0015] The second annealing temperature is higher than the growth temperature of the P-type layer;

[0016] The first condition includes: annealing pressure of 300-600 torr, Mg source introduction time of 5-10 seconds, first annealing temperature of 900-1100° C.; and / or

[0017] The second conditions include: annealing pressure of 300-600 torr, interruption time of Mg source of 5-10 seconds, and second annealing temperature of 900-1100°C.

[0018] In some possible implementations, the light-emitting layer includes at least a first light-emitting layer and a second light-emitting layer that are grown in sequence. Growing the light-emitting layer includes:

[0019] At least one first light-emitting structure is grown on the N-type layer to obtain a first light-emitting layer; the first light-emitting structure includes a first quantum well layer and a first quantum barrier layer that are grown in sequence, and growing the first light-emitting structure includes:

[0020] Under the first growth condition, growing the first quantum well layer with a thickness of 1 to 5 nm on the N-type layer; the first growth condition includes: a growth temperature of 650 to 850° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 1000 to 10000;

[0021] Under the second growth condition, the first quantum barrier layer with a thickness of 6 to 25 nm is grown on the first quantum well layer; the second growth condition includes: a growth temperature of 700 to 950° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 1000 to 10000;

[0022] At least one second light-emitting structure is grown on the first light-emitting layer to obtain a second light-emitting layer; the second light-emitting structure includes a second quantum well layer and a second quantum barrier layer grown in sequence, and growing the second light-emitting structure includes:

[0023] Under the third growth condition, the second quantum well layer with a thickness of 2-6 nm is grown on the first quantum barrier layer; the growth temperature is 650-850° C., the growth pressure is 200-500 torr, and the V / III ratio is 2000-20000.

[0024] Under the fourth growth condition, the second quantum barrier layer with a thickness of 3-10 nm is grown on the second quantum well layer; the growth temperature is 700-950° C., the growth pressure is 200-500 torr, and the V / III ratio is 2000-20000.

[0025] The V / III ratios of growing the second quantum well layer and the second quantum barrier layer are both greater than the V / III ratios of growing the first quantum well layer and the first quantum barrier layer.

[0026] In some possible implementations, the growth thickness of the second quantum well layer is greater than the growth thickness of the first quantum well layer; and the growth thickness of the second quantum barrier layer is less than the growth thickness of the first quantum barrier layer.

[0027] In some possible implementations, the intermediate layer at least includes a first barrier layer, a second barrier layer, and a diffusion layer that are grown in sequence; and growing the intermediate layer includes:

[0028] Under the fifth growth condition, the first barrier layer with a thickness of 1 to 3 nm is grown on the light-emitting layer, wherein the fifth growth condition includes: a growth temperature of 750 to 1000° C., a growth pressure of 50 to 150 torr, and a V / III ratio of 3000 to 10000;

[0029] Under the sixth growth condition, growing the second barrier layer with a thickness of 1 to 3 nm on the first barrier layer, the sixth growth condition comprising: a growth temperature of 750 to 1000° C., a growth pressure of 50 to 150 torr, and a V / III ratio of 2000 to 8000;

[0030] Under the seventh growth condition, the diffusion layer with a thickness of 2-5 nm is grown on the second barrier layer, wherein the seventh growth condition includes: a growth temperature of 700-950° C., a growth pressure of 200-500 torr, and a V / III ratio of 5000-20000;

[0031] The V / III ratio of growing the diffusion layer is greater than the V / III ratio of growing the first barrier layer and greater than the V / III ratio of growing the second barrier layer.

[0032] In some possible implementations, the intermediate layer at least includes a diffusion layer, a second barrier layer, and a first barrier layer that are grown in sequence; and growing the intermediate layer includes:

[0033] Under the seventh growth condition, the diffusion layer with a thickness of 2 to 5 nm is grown on the light-emitting layer; the seventh growth condition includes: a growth temperature of 700 to 950° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 5000 to 20000;

[0034] Under the sixth growth condition, growing the second barrier layer with a thickness of 1-3 nm on the diffusion layer; the sixth growth condition includes: a growth temperature of 750-1000° C., a growth pressure of 50-150 torr, and a V / III ratio of 2000-8000;

[0035] Under the fifth growth condition, the first barrier layer with a thickness of 1 to 3 nm is grown on the second barrier layer; the fifth growth condition includes: a growth temperature of 750 to 1000° C., a growth pressure of 50 to 150 torr, and a V / III ratio of 3000 to 10000;

[0036] The V / III ratio of growing the diffusion layer is greater than the V / III ratio of growing the first barrier layer and greater than the V / III ratio of growing the second barrier layer.

[0037] In some possible implementations, the P-type layer includes at least a first P-type layer and a second P-type layer that are grown sequentially in stacked order, and growing the P-type layer includes:

[0038] Under the eighth growth condition, a first P-type layer with a thickness of 10-100 nm is grown on the intermediate layer, wherein the eighth growth condition includes: a growth temperature of 650-850° C., a growth pressure of 200-400 torr, and a V / III ratio of 300-5000;

[0039] Under the ninth growth condition, a second P type layer with a thickness of 20 to 200 nm is grown on the first P type layer. The ninth growth condition includes: a growth temperature of 850 to 1050° C., a growth pressure of 200 torr to 600 torr, and a V / III ratio of 300 to 5000.

[0040] In some possible embodiments, the second annealing temperature is higher than the growth temperature of the second P-type layer in the temperature range of 40°C to 100°C; and / or the second annealing temperature is not higher than the growth temperature of the first quantum well layer and the second quantum well layer, which is 300°C respectively.

[0041] In some possible implementations, during the repeated cyclic alternation process, the growth temperature from the first step to the second step decreases linearly; and / or during the repeated cyclic alternation process, the growth temperature from the second step to the first step increases linearly.

[0042] A second aspect of the present invention provides a semiconductor device, wherein the semiconductor device comprises an epitaxial wafer, and the epitaxial wafer is prepared by the above-mentioned method for preparing an epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic structural diagram of an epitaxial wafer in one embodiment of the present invention;

[0044] Figure 2 It is a schematic diagram of the structure of an epitaxial wafer in another embodiment of the present invention.

[0045] In the figure; 1, substrate; 2, N-type layer; 3, light-emitting layer; 31, first light-emitting structure; 32, second light-emitting structure; 311, first quantum well layer; 312, first quantum barrier layer; 321, second quantum well layer; 322, second quantum barrier layer; 4, intermediate layer; 41, first barrier layer; 42, second barrier layer; 43, diffusion layer; 5, P-type layer; 51, first P-type layer; 52, second P-type layer. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete and to fully convey the concepts of example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated description will be omitted.

[0047] The words expressing positions and directions described in the present invention are all explained with reference to the accompanying drawings as examples, but they can be changed as needed, and all such changes are included in the protection scope of the present invention.

[0048] Please refer to Figure 1 and Figure 2 The present invention provides an embodiment, which provides a method for preparing an epitaxial wafer, and the method includes the following steps S1 to S4.

[0049] Step S1: Provide a substrate 1. The substrate 1 may be a Si substrate, a silicon germanium substrate, a III-V group element compound substrate (such as a gallium nitride substrate or an aluminum nitride substrate), a silicon carbide substrate or a laminated structure thereof, a diamond, a sapphire substrate, or other semiconductor material substrates known to those skilled in the art.

[0050] Step S2: epitaxially growing a stacked structure including an N-type layer 2 , a light-emitting layer 3 and an intermediate layer 4 in sequence on a substrate 1 .

[0051] In some specific implementations, step S2 includes steps S21 to S23.

[0052] Step S21 : epitaxially growing an N-type layer 2 on the substrate 1 .

[0053] Furthermore, in this embodiment, the Si-doped N-type layer 2 is epitaxially grown on the substrate 1 by using a MOCVD (Metal-organic Chemical Vapor Deposition) process.

[0054] It should be additionally explained that the N-type layer 2 may also be epitaxially grown on the substrate 1 by using MBE (Molecular beam epitaxy) or HVPE (Hydride Vapor Phase Epitaxy).

[0055] The material of the N-type layer 2 is nitride, which can be n-type GaN or n-type AlGaN. The growth thickness of the N-type layer 2 is 1 to 10 μm. The N-type layer 2 is doped with Si to provide electron injection. The doping concentration of Si in the N-type layer 2 is 1×10 18 cm -3 ~8×10 18 cm -3 The growth conditions of the N-type layer 2 include: a growth temperature of 1000-1200° C., a growth pressure of 100-600 torr, and a V / III ratio of 500-5000.

[0056] It is worth noting that the V / III ratio in the present invention refers to the molar flow ratio of the group V element to the group III element.

[0057] Step S22 : epitaxially growing a light emitting layer 3 on the N-type layer 2 .

[0058] Furthermore, in this embodiment, the light emitting layer 3 is epitaxially grown on the N-type layer 2 by MOCVD process.

[0059] It should be supplemented that the light emitting layer 3 may also be epitaxially grown on the N-type layer 2 by using MBE or HVPE.

[0060] In a specific embodiment, the light emitting layer 3 includes a first light emitting layer and a second light emitting layer that are grown in sequence. Growing the light emitting layer 3 includes step S221 and step S222.

[0061] Step S221: growing at least one first light emitting structure 31 on the N-type layer 2 to obtain a first light emitting layer, wherein the number of the first light emitting structures 31 is preferably 1-15.

[0062] The first light emitting structure 31 includes a first quantum well layer 311 and a first quantum barrier layer 312 that are sequentially stacked. Growing the first light emitting structure 31 includes:

[0063] A) Under the first growth condition, a first quantum well layer 311 with a thickness of 1-5 nm is grown on the N-type layer 2; the first growth condition includes: a growth temperature of 650-850° C., a growth pressure of 200-500 torr, and a V / III ratio of 1000-10000.

[0064] B) Under a second growth condition, growing a first quantum barrier layer with a thickness of 6 to 25 nm on the first quantum well layer; the second growth condition includes: a growth temperature of 700 to 950° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 1000 to 10000.

[0065] Step S222: growing at least one second light-emitting structure 32 on the first light-emitting layer to obtain a second light-emitting layer, wherein the number of the second light-emitting structures 32 is preferably 1-15.

[0066] The second light emitting structure 32 includes a second quantum well layer 321 and a second quantum barrier layer 322 that are sequentially stacked. Growing the second light emitting structure 32 includes:

[0067] C) Under the third growth condition, a second quantum well layer 321 with a thickness of 2-6 nm is grown on the first quantum barrier layer 312; the third growth condition includes: a growth temperature of 650-850° C., a growth pressure of 200-500 torr, and a V / III ratio of 2000-20000.

[0068] D) Under the fourth growth condition, a second quantum barrier layer 322 with a thickness of 3-10 nm is grown on the second quantum well layer 321; the fourth growth condition includes: a growth temperature of 700-950° C., a growth pressure of 200-500 torr, and a V / III ratio of 2000-20000.

[0069] Specifically, the materials of the first quantum well layer 311, the second quantum well layer 321, the first quantum barrier layer 312, and the second quantum barrier layer 322 are all nitrides, wherein the material of the first quantum well layer 311 and the second quantum well layer 321 can be InGaN, and the material of the first quantum barrier layer 312 and the second quantum barrier layer 322 can be GaN.

[0070] In some specific embodiments, the growth thickness of the second quantum well layer 321 is greater than the growth thickness of the first quantum well layer 311. For example, the growth thickness of the second quantum well layer 321 is 6 nm, and the growth thickness of the first quantum well layer 311 is 5 nm; the growth thickness of the second quantum well layer 321 is 2 nm, and the growth thickness of the first quantum well layer 311 is 1 nm; the growth thickness of the second quantum well layer 321 is 4 nm, and the growth thickness of the first quantum well layer 311 is 3 nm.

[0071] The growth thickness of the second quantum barrier layer 322 is less than the growth thickness of the first quantum barrier layer 312. For example, the growth thickness of the second quantum barrier layer 322 is 10 nm, and the growth thickness of the first quantum barrier layer 312 is 25 nm; the growth thickness of the second quantum barrier layer 322 is 3 nm, and the growth thickness of the first quantum barrier layer 312 is 6 nm; the growth thickness of the second quantum barrier layer 322 is 6 nm, and the growth thickness of the first quantum barrier layer 312 is 15 nm.

[0072] The light-emitting layer 3 serves as the active region of the epitaxial wafer. The electrons provided by the N-type layer 2 and the holes provided by the P-type layer 5 are respectively injected into the light-emitting layer 3 under electrical injection conditions. The electrons and holes radiate and recombine to emit light in the light-emitting layer 3. The thickness difference between the first quantum well layer 311 and the first quantum barrier layer 312 and between the second quantum well layer 321 and the second quantum barrier layer 322 can improve the brightness of the epitaxial wafer. When the growth thickness of the second quantum well layer 321 is greater than the growth thickness of the first quantum well layer 311, it is beneficial for the electrons provided by the N-type layer 2 to gather in the second quantum well layer 321, thereby reducing the probability of electrons overflowing the light-emitting layer 3. When the growth thickness of the second quantum barrier layer 322 is less than the growth thickness of the first quantum barrier layer 312, it is beneficial for the holes provided by the P-type layer 5 to be transmitted in the light-emitting layer 3, thereby improving the hole injection capability.

[0073] It should be noted that the V / III ratios of the second quantum well layer 321 and the second quantum barrier layer 322 are greater than the V / III ratios of the first quantum well layer 311 and the first quantum barrier layer 312. For example, the V / III ratio of the second quantum well layer 321 is 18000, the V / III ratio of the second quantum barrier layer 322 is 16000, the V / III ratio of the first quantum well layer 311 is 15000, and the V / III ratio of the first quantum barrier layer 312 is 14000.

[0074] Setting the V / III ratio of the second quantum well layer 321 and the second quantum barrier layer 322 to be greater than the V / III ratio of the first quantum well layer 311 and the first quantum barrier layer 312 has two effects. On the one hand, because holes have lower transport capabilities than electrons, holes are often distributed in the second light-emitting structure 32 close to the P-type layer 5. The relatively large V / III ratio in the second quantum well layer 321 and the second quantum barrier layer 322 can reduce vacancy defects in the entire light-emitting layer 3, thereby reducing the capture of holes by vacancy defects, enhancing the longitudinal transport capability of holes, and improving the uniformity of hole distribution in the nitride light-emitting layer 3. On the other hand, because there are surface defects in the epitaxial growth process, which have a high adsorption and deposition performance for Mg atoms, this can reduce the phenomenon of increased surface defect distribution in the intermediate layer 4 due to the increase in vacancy defects, thereby reducing the adsorption of Mg atoms by defects in the intermediate layer 4 during the Mg heat treatment process due to the increase in defects.

[0075] The relatively low V / III ratio in the first quantum well layer 311 and the first quantum barrier layer 312 can reduce the surface roughness of the first light-emitting structure 31, improve the interface quality of the first quantum well layer 311 and the first quantum barrier layer 312, reduce the dislocation extension in the light-emitting layer 3, and improve the radiation recombination in the light-emitting layer 3, thereby providing a high-quality growth template for the growth of the second quantum well layer 321 and the second quantum barrier layer 322.

[0076] Step S23 : epitaxially growing an intermediate layer 4 on the light-emitting layer 3 .

[0077] It should be noted that the intermediate layer 4 has the function of preventing Mg from diffusing into the light-emitting layer 3 during the pretreatment process, that is, the intermediate layer 4 is mainly used to play a role in regulating the functional layer during the Mg thermal annealing process, and also has the function of preventing Mg-doped materials from diffusing into the light-emitting layer 3.

[0078] Furthermore, the intermediate layer 4 can also prevent the doping material from diffusing into the light-emitting layer 3 during the growth of the P-type layer 5. In this embodiment, the doping material in the P-type layer 5 is Mg.

[0079] In this embodiment, the doping material in the P-type layer 5 may be Mg.

[0080] Furthermore, in this embodiment, the intermediate layer 4 is epitaxially grown on the light-emitting layer 3 by MOCVD process.

[0081] It should be additionally explained that the intermediate layer 4 may also be epitaxially grown on the light-emitting layer 3 by using MBE or HVPE.

[0082] In a specific embodiment, see the attached Figure 1 As shown, the intermediate layer 4 includes a first barrier layer 41, a second barrier layer 42 and a diffusion layer 43 which are grown in sequence. The growth of the intermediate layer 4 includes steps S23a to S25a.

[0083] Step S23a: Under the fifth growth condition of a growth temperature of 750-1000°C, a growth pressure of 50-150torr, and a V / III ratio of 3000-10000, a first barrier layer 41 with a thickness of 1-3 nm is grown on the light-emitting layer (specifically, the second quantum barrier layer of the light-emitting layer). The material of the first barrier layer 41 is AlN, and the first barrier layer 41 utilizes the low solubility of Mg atoms in the first barrier layer 41 to prevent Mg atoms from diffusing from the second quantum barrier layer 322 into the first quantum well layer 311 during the thermal annealing process of introducing the Mg source in step S3.

[0084] Step S24a: Under the sixth growth condition of a growth temperature of 750-1000° C., a growth pressure of 50-150 torr, and a V / III ratio of 2000-8000, a second barrier layer 42 with a thickness of 1-3 nm is grown on the first barrier layer 41. The material of the second barrier layer 42 is AlGaN, and the second barrier layer 42 utilizes the lower solubility of Mg atoms in the second barrier layer 42, and further blocks Mg atoms from diffusing from the second quantum barrier layer 322 into the first quantum well layer 311 during the thermal annealing process in which the Mg source is introduced in step S3.

[0085] Step S25a: Under the seventh growth condition of a growth temperature of 700-950° C., a growth pressure of 200-500 torr, and a V / III ratio of 5000-20000, a diffusion layer 43 with a thickness of 2-5 nm is grown on the second barrier layer 42. The material of the diffusion layer 43 is InGaN, and the diffusion layer 43 can absorb Mg atoms to form restrictions by utilizing the high solubility of Mg atoms in the diffusion layer 43, and the restricted Mg atoms can utilize the low activation characteristics of Mg atoms in the diffusion layer 43 to effectively provide holes for the doping of Mg atoms.

[0086] In this embodiment, through step S24a and step S25a, step S24a makes the difference in band gap barrier height between the second barrier layer 42 and the P-type layer 5 in step S3 (specifically, the first P-type layer 51 in the P-type layer 5 in contact with the diffusion layer 43) relatively low, which is conducive to the injection of holes from the P-type layer 5 to the light-emitting layer 3, improves the distribution uniformity of electrons and holes in the light-emitting layer 3, and significantly improves the luminous brightness of the epitaxial wafer, and improves the luminous efficiency of the epitaxial wafer under low current working conditions; although when the epitaxial wafer is under high current working conditions, there is a risk of leakage of electrons in the light-emitting layer 3, which to a certain extent makes the luminous efficiency of the epitaxial wafer slightly lower than that of the epitaxial wafer under low current working conditions. However, while ensuring that the luminous brightness of the epitaxial wafer is significantly improved, its luminous efficiency can still meet the use requirements.

[0087] In another specific embodiment, see the attached Figure 2 As shown, the intermediate layer 4 includes a diffusion layer 43, a second barrier layer 42 and a first barrier layer 41 which are grown in sequence, and the growth of the intermediate layer 4 includes steps S23b to S25b.

[0088] Step S23b: Under the seventh growth condition of a growth temperature of 700-950°C, a growth pressure of 200-500torr, and a V / III ratio of 5000-20000, a diffusion layer 43 with a thickness of 2-5nm is grown on the light-emitting layer 3 (specifically, the second quantum barrier 322 layer of the light-emitting layer 3). The material of the diffusion layer 43 is InGaN, and the diffusion layer 43 can absorb Mg atoms to form restrictions by utilizing the high solubility of Mg atoms in the diffusion layer 43, and the restricted Mg atoms can utilize the low activation characteristics of Mg atoms in the diffusion layer 43 to effectively provide holes for the doping of Mg atoms.

[0089] Step S24b: Under the sixth growth condition of a growth temperature of 750-1000° C., a growth pressure of 50-150 torr, and a V / III ratio of 2000-8000, a second barrier layer 42 with a thickness of 1-3 nm is grown on the diffusion layer 43. The material of the second barrier layer 42 is AlGaN, and the second barrier layer 42 utilizes the lower solubility of Mg atoms in the second barrier layer 42, and further blocks Mg atoms from diffusing from the second quantum barrier layer 322 into the first quantum well layer 311 during the thermal annealing process in which the Mg source is introduced in step S3.

[0090] Step S25b: Under the fifth growth condition of a growth temperature of 750-1000°C, a growth pressure of 50-150torr, and a V / III ratio of 3000-10000, a first barrier layer 41 with a thickness of 1-3nm is grown on the second barrier layer 42. The material of the first barrier layer 41 is AlN, and the first barrier layer 41 utilizes the low solubility of Mg atoms in the first barrier layer 41 to prevent Mg atoms from diffusing from the second quantum barrier layer 322 into the first quantum well layer 311 during the thermal annealing process of introducing the Mg source in step S3.

[0091] It should be further explained that the materials in the first barrier layer 41 , the second barrier layer 42 and the diffusion layer 43 can be selected according to the difference in solubility gradients, but what must be ensured is that the solubility of Mg atoms in the diffusion layer 43 > the solubility of Mg atoms in the second barrier layer 42 > the solubility of Mg atoms in the first barrier layer 41 .

[0092] In this embodiment, through step S23b and step S24b, step S24b makes the difference in band gap barrier height between the second barrier layer 42 and the P-type layer 5 in step S3 (specifically, the first P-type layer 51 in the P-type layer 5 that contacts the first barrier layer 41) higher. Although it affects the injection of holes from the P-type layer 5 to the light-emitting layer 3, it can more effectively block the leakage of electrons injected from the N-type layer 2 into the light-emitting layer 3 into the P-type layer 5, which is beneficial to improving the luminous efficiency of the epitaxial wafer under high current working conditions and improving the luminous brightness of the epitaxial wafer.

[0093] In summary, in the above two embodiments, by utilizing the solubility gradient difference of Mg atoms in the first barrier layer 41, the second barrier layer 42 and the diffusion layer 43 in the intermediate layer 4, the restriction on the diffusion of Mg atoms in the diffusion layer 43 is increased, the dissolution rate and doping efficiency of Mg atoms in the diffusion layer 43 are increased, and the diffusion capacity of Mg atoms in the solubility layer, that is, the intermediate layer 4, is reduced, thereby preventing Mg atoms from diffusing into the light-emitting layer 3, thereby increasing the radiation recombination efficiency of the light-emitting layer and improving the photoelectric performance of the epitaxial wafer.

[0094] It should be further explained that, the V / III ratio of the growing diffusion layer 43>the V / III ratio of the growing second barrier layer 42>the V / III ratio of the growing first barrier layer 41. For example, the V / III ratio of the diffusion layer 43 is 20000, the V / III ratio of the second barrier layer 42 is 10000, and the V / III ratio of the first barrier layer 41 is 8000; the V / III ratio of the diffusion layer 43 is 5000, the V / III ratio of the second barrier layer 42 is 3000, and the V / III ratio of the first barrier layer 41 is 2000; the V / III ratio of the diffusion layer 43 is 12000, the V / III ratio of the second barrier layer 42 is 7000, and the V / III ratio of the first barrier layer 41 is 5000.

[0095] The first barrier layer 41, the second barrier layer 42 and the diffusion layer 43 all adopt a relatively high V / III ratio growth process to reduce vacancy defects in the intermediate layer 4. The high V / III ratio can reduce vacancy defects under relatively low growth temperature conditions and reduce the absorption of holes by vacancy defects during the transmission process.

[0096] Compared with the first barrier layer 41 and the second barrier layer 42 , the high V / III ratio of the diffusion layer 43 can further reduce the vacancy defects formed under relatively low growth temperature conditions and reduce the absorption of holes by the vacancy defects during the transport process.

[0097] The first barrier layer 41 and the second barrier layer 42 use a relatively low V / III ratio relative to the diffusion layer 43 to reduce the pre-reaction under the fifth growth condition and the sixth growth condition, and reduce the impurity distribution in the first barrier layer 41 (because the pre-reaction will introduce impurity atoms such as C, H and O into the epitaxial wafer).

[0098] The first barrier layer 41 adopts a relatively lower V / III ratio than the second barrier layer 42 , which can avoid the second barrier layer 42 increasing the metal polarity surface at a high V / III ratio, improve the surface flatness of the second barrier layer 42 , and further improve the uniformity of hole injection into the P-type layer 5 .

[0099] Based on the above steps, a stacked structure is obtained, which includes an N-type layer 2, a light-emitting layer 3 and an intermediate layer 4 which are sequentially stacked on a substrate 1.

[0100] Step S3: pre-processing the stacked structure.

[0101] Specifically, the pretreatment includes at least a first step, and the first step includes: after introducing a Mg source into the reaction chamber, performing a thermal annealing treatment under a first condition; the first condition includes at least a first annealing temperature.

[0102] The first condition also includes: annealing pressure of 300-600 torr, Mg source introduction time of 5-10 seconds, and first annealing temperature of 900-1100°C.

[0103] Step S4: After pretreatment, epitaxially grow a P-type layer 5 on the middle layer 4 of the stacked structure.

[0104] Furthermore, in this embodiment, the P-type layer 5 is epitaxially grown on the pre-treated stacked structure (specifically, the first barrier layer 41 or the diffusion layer 43 of the intermediate layer 4 ) by the MOCVD process.

[0105] It should be additionally explained that the P-type layer 5 may also be epitaxially grown on the intermediate layer 4 by using MBE or HVPE.

[0106] In some specific embodiments, the P-type layer 5 includes a first P-type layer 51 and a second P-type layer 52 that are grown in sequence, and growing the P-type layer 5 includes step S41 and step S42.

[0107] Step S41 : growing a first P-type layer 51 doped with Mg on the intermediate layer 4 under the eighth growth condition of a growth temperature of 650-850° C., a growth pressure of 200-400 torr, and a V / III ratio of 300-5000.

[0108] The material of the first P-type layer 51 is p-type GaN, the growth thickness of the first P-type layer 51 is 10-100 nm, and the doping concentration of Mg in the first P-type layer 51 is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0109] Step S42 : growing a second P-type layer 52 doped with Mg on the first P-type layer 51 under the ninth growth condition of a growth temperature of 850-1050° C., a growth pressure of 200-600 torr, and a V / III ratio of 300-5000.

[0110] The material of the second P-type layer 52 is p-type GaN, the growth thickness of the second P-type layer 52 is 20-200 nm, and the doping concentration of Mg in the second P-type layer 52 is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0111] At a relatively low growth temperature, the first P-type layer 51 plays a role in further protecting the light-emitting layer 3 , and improves the doping efficiency of Mg in the first P-type layer 51 , thereby improving the injection capability of holes into the light-emitting layer 3 .

[0112] At a relatively high growth temperature, the vacancy defects and impurity atom distribution in the second P-type layer 52 can be effectively reduced. On the one hand, the self-compensation effect of Mg doping is reduced, the hole concentration in the second P-type layer 52 is increased, and the lateral expansion distribution of holes is greatly improved, the leakage channel of the epitaxial wafer is reduced, and the anti-static release performance of the epitaxial wafer is improved.

[0113] It should be noted that the first annealing temperature is higher than the growth temperature of the P-type layer 5. For example, when the first annealing temperature is 900°C, the growth temperature of the first P-type layer 51 is 650°C, and the growth temperature of the second P-type layer 52 is 850°C; when the first annealing temperature is 1100°C, the growth temperature of the first P-type layer 51 is 850°C, and the growth temperature of the second P-type layer 52 is 1050°C; when the first annealing temperature is 1000°C, the growth temperature of the first P-type layer 51 is 750°C, and the growth temperature of the second P-type layer 52 is 950°C.

[0114] During the heat treatment process under high temperature conditions, it is beneficial for the Mg source to react and deposit on the side walls and top of the reaction chamber cavity and reach a stable state. While reducing the occurrence of Mg atom memory effect, it can well avoid Mg atom decomposition during the growth of the first P-type layer 51 and the second P-type layer 52, thereby maintaining a stable growth process.

[0115] In some specific embodiments, the pretreatment further includes a second step that is repeated and cyclically alternating with the first step, the second step comprising: after interrupting the introduction of the Mg source into the reaction chamber, performing thermal annealing under second conditions, the second conditions including at least a second annealing temperature.

[0116] The second condition also includes: annealing pressure of 300-600 torr, interruption time of Mg source of 5-10 seconds, and second annealing temperature of 900-1100°C.

[0117] It should be noted that the second annealing temperature is higher than the growth temperature of the P-type layer 5. For example, when the second annealing temperature is 900°C, the growth temperature of the first P-type layer 51 is 650°C, and the growth temperature of the second P-type layer 52 is 850°C; when the second annealing temperature is 1100°C, the growth temperature of the first P-type layer 51 is 850°C, and the growth temperature of the second P-type layer 52 is 1050°C; when the second annealing temperature is 1000°C, the growth temperature of the first P-type layer 51 is 750°C, and the growth temperature of the second P-type layer 52 is 950°C.

[0118] During the thermal annealing process of interrupting the introduction of the Mg source in the second step, the introduced Mg source is fully decomposed to avoid the undecomposed Mg source from being used as a new dopant to provide doping atoms again, affecting the actual doping concentration of Mg in step S3, and preventing the leakage and anti-static release (ESD) performance of the epitaxial wafer from being reduced.

[0119] In a specific embodiment, the second annealing temperature is higher than the growth temperature of the second P-type layer 52 in the temperature range of 40°C to 100°C, and the second annealing temperature is not higher than the growth temperature of the first quantum well layer 311 and the second quantum well layer 321, which is 300°C.

[0120] When the second annealing temperature is higher than the growth temperature of the second P-type layer 52 and is less than 40°C, the memory effect of Mg cannot be completely and effectively suppressed when the second P-type layer 52 is grown, and the Mg heat treatment time needs to be increased by more than 2-3 times. Only when the second annealing temperature is higher than the growth temperature of the second P-type layer 52 and is greater than or equal to 40°C, the memory effect of Mg can be effectively suppressed when the second P-type layer 52 is grown, and there is no need to increase the Mg heat treatment time.

[0121] When 100°C≧the second annealing temperature is higher than the growth temperature of the second P-type layer 52≧40°C, the memory effect of Mg can be completely and effectively suppressed when the second P-type layer 52 is grown, and there is no need to increase the Mg heat treatment time. However, since the memory effect of Mg has been suppressed to match the production performance requirements of the epitaxial wafer, the performance of the epitaxial wafer does not change significantly when the second annealing temperature is increased to 100°C, so there is no need to increase the temperature, which reduces energy waste, the difficulty of high temperature control, and the loss of the life of the heating components.

[0122] It should be noted that the applicant further discovered that the second annealing temperature cannot be higher than 300°C relative to the growth temperature of the first quantum well layer 311 and the second quantum well layer 321, because when it exceeds 300°C, the annealing temperature is too high, which will cause thermal damage to the light-emitting layer 3 and reduce the photoelectric performance of the epitaxial wafer.

[0123] In some specific embodiments, during the above-mentioned repeated cyclic alternation process, the temperature during the first step is linearly reduced to the second step, and then the temperature during the second step is linearly increased to the first step; or during the repeated cyclic alternation process, the temperature during the first step is linearly increased to the second step, and then the temperature during the second step is linearly reduced to the first step.

[0124] By controlling the linear change of the growth temperature, on the one hand, the time that the growth temperature is in a relatively high temperature section during the entire pre-treatment thermal annealing process is reduced, thereby preventing the growth temperature from damaging the light-emitting structure during the thermal annealing process, and effectively improving the stability of the optoelectronic performance of the epitaxial wafer; on the other hand, the linear change of the growth temperature plays a role in annealing the light-emitting layer, and the deep energy level defects in the light-emitting layer can be effectively eliminated during the temperature change process. The atoms in the light-emitting layer can be fully migrated to improve the uniformity of the components, which can effectively improve the stability of the light-emitting wavelength and reduce wavelength drift and brightness attenuation.

[0125] The present invention provides an epitaxial wafer prepared by the above preparation method, comprising a substrate 1, an N-type layer 2, a light-emitting layer 3, an intermediate layer 4 and a P-type layer 5 which are stacked in sequence.

[0126] The light-emitting layer includes a first light-emitting layer and a second light-emitting layer which are stacked in sequence, the first light-emitting layer includes at least one first light-emitting structure 31, the first light-emitting structure 31 includes a first quantum well layer 311 and a first quantum barrier layer 312 which are stacked in sequence; the second light-emitting layer includes at least one second light-emitting structure 32, the second light-emitting structure 32 includes a second quantum well layer 321 and a second quantum barrier layer 322 which are stacked in sequence.

[0127] In one embodiment, see the attached Figure 1 As shown, the intermediate layer 4 includes a first barrier layer 41 , a second barrier layer 42 , and a diffusion layer 43 which are stacked.

[0128] In another embodiment, see the attached Figure 2 As shown, the intermediate layer 4 includes a diffusion layer 43 , a second barrier layer 42 , and a first barrier layer 41 which are stacked.

[0129] The P-type layer 5 includes a first P-type layer 51 and a second P-type layer 52 which are stacked.

[0130] The present invention provides a semiconductor device, which comprises an epitaxial wafer, and the epitaxial wafer is prepared by adopting the above-mentioned epitaxial wafer preparation method.

[0131] The technical solution of the present application will be described in more detail below, but it should be understood that the following examples are only for explaining and illustrating the technical solution, but do not limit the scope of the present application. Moreover, unless otherwise specified, the various raw materials, reaction equipment, detection equipment and methods used in the following examples are all known in the art.

[0132] Example 1

[0133] The present invention provides an embodiment, which provides a method for preparing an epitaxial wafer. The method includes the following steps S1 to S4.

[0134] Step S1: providing a substrate 1.

[0135] The substrate 1 is a Si substrate.

[0136] Step S2: epitaxially growing an N-type layer 2,

[0137] The laminated structure of the light emitting layer 3 and the intermediate layer 4.

[0138] Step S2 includes steps S21 to S23.

[0139] Step S21: epitaxially growing a Si-doped N-type layer 2 on the substrate 1 by MOCVD.

[0140] The material of the N-type layer 2 is n-type GaN, and the growth thickness of the N-type layer 2 is 1 μm; the doping concentration of Si in the N-type layer 2 is 1×10 18 cm -3 The growth conditions of the N-type layer 2 include: a growth temperature of 1000° C., a growth pressure of 100 torr, and a V / III ratio of 500.

[0141] Step S22: epitaxially growing the light emitting layer 3 on the N-type layer 2 by MOCVD.

[0142] The light emitting layer 3 includes a first light emitting layer and a second light emitting layer that are grown in sequence. The process of growing the light emitting layer 3 includes steps S221 and S222.

[0143] Step S221: growing at least one first light emitting structure 31 on the N-type layer 2 to obtain a first light emitting layer. The number of the first light emitting structure 31 is one.

[0144] The first light emitting structure 31 includes a first quantum well layer 311 and a first quantum barrier layer 312 that are sequentially stacked. Growing the first light emitting structure 31 includes:

[0145] A) Under a first growth condition, a first quantum well layer 311 with a thickness of 1 nm is grown on the N-type layer 2; the first growth condition includes: a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 1000.

[0146] B) Under a second growth condition, a first quantum barrier layer with a thickness of 6 nm is grown on the first quantum well layer; the second growth condition includes: a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 1000.

[0147] Step S222: growing at least one second light emitting structure 32 on the first light emitting layer to obtain a second light emitting layer, wherein the number of the second light emitting structure 32 is one.

[0148] The second light emitting structure 32 includes a second quantum well layer 321 and a second quantum barrier layer 322 that are sequentially stacked. Growing the second light emitting structure 32 includes:

[0149] C) Under the third growth condition, a second quantum well layer 321 with a thickness of 2 nm is grown on the first quantum barrier layer 312; the third growth condition includes: a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 2000.

[0150] D) Under the fourth growth condition, a second quantum barrier layer 322 with a thickness of 3 nm is grown on the second quantum well layer 321 ; the fourth growth condition includes: a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 2000.

[0151] The material of the first quantum well layer 311 and the second quantum well layer 321 is InGaN, and the material of the first quantum barrier layer 312 and the second quantum barrier layer 322 is GaN.

[0152] Step S23: epitaxially growing the intermediate layer 4 on the light emitting layer 3 by MOCVD process.

[0153] See attached Figure 1 As shown, the intermediate layer 4 includes a first barrier layer 41, a second barrier layer 42 and a diffusion layer 43 which are grown in sequence. The growth of the intermediate layer 4 includes steps S23a to S25a.

[0154] Step S23a: Under the fifth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 3000, a first barrier layer 41 with a thickness of 1 to 3 nm is grown on the light emitting layer (specifically, the second quantum barrier layer of the light emitting layer). The material of the first barrier layer 41 is AlN.

[0155] Step S24a: Under the sixth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 2000, a second barrier layer 42 with a thickness of 1 nm is grown on the first barrier layer 41. The material of the second barrier layer 42 is AlGaN.

[0156] Step S25a: Under the seventh growth condition of a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 5000, a diffusion layer 43 with a thickness of 2 nm is grown on the second barrier layer 42 . The material of the diffusion layer 43 is InGaN.

[0157] Based on the above steps, a stacked structure is obtained, which includes an N-type layer 2, a light-emitting layer 3 and an intermediate layer 4 which are sequentially stacked on a substrate 1.

[0158] Step S3: pre-processing the stacked structure.

[0159] Specifically, the pretreatment includes at least a first step, and the first step includes: after introducing a Mg source into the reaction chamber, performing a thermal annealing treatment under a first condition; the first condition includes at least a first annealing temperature.

[0160] The first condition also includes: annealing pressure of 300 torr, Mg source introduction time of 5 seconds, and first annealing temperature of 900°C.

[0161] Step S4: After pretreatment, epitaxially grow a P-type layer 5 on the middle layer 4 of the stacked structure by MOCVD process.

[0162] The P-type layer 5 includes a first P-type layer 51 and a second P-type layer 52 that are grown in sequence, and growing the P-type layer 5 includes steps S41 and S42 .

[0163] Step S41 : growing a first P-type layer 51 doped with Mg on the intermediate layer 4 under the eighth growth condition of a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 300.

[0164] The material of the first P-type layer 51 is p-type GaN, the growth thickness of the first P-type layer 51 is 10 nm, and the doping concentration of Mg in the first P-type layer 51 is 1×10 19 cm -3 .

[0165] Step S41 : growing a second P-type layer 52 doped with Mg on the first P-type layer 51 under the ninth growth condition of a growth temperature of 850° C., a growth pressure of 200 torr, and a V / III ratio of 300.

[0166] The material of the second P-type layer 52 is p-type GaN, the growth thickness of the second P-type layer 52 is 20-200 nm, and the doping concentration of Mg in the second P-type layer 52 is 1×10 19 cm -3 .

[0167] Example 2

[0168] The difference from Example 1 is:

[0169] The growth thickness of the N-type layer 2 is 5 μm; the doping concentration of Si in the N-type layer 2 is 4×10 18 cm -3 The growth conditions of the N-type layer 2 include: a growth temperature of 1100° C., a growth pressure of 300 torr, and a V / III ratio of 3000.

[0170] The number of the first light emitting structures 31 is eight.

[0171] A) Under the first growth condition, a first quantum well layer 311 with a thickness of 3 nm is grown on the N-type layer 2; the first growth condition includes: a growth temperature of 750° C., a growth pressure of 350 torr, and a V / III ratio of 5000.

[0172] B) Under a second growth condition, a first quantum barrier layer with a thickness of 16 nm is grown on the first quantum well layer; the second growth condition includes: a growth temperature of 800° C., a growth pressure of 350 torr, and a V / III ratio of 6000.

[0173] The number of the second light emitting structures 32 is eight.

[0174] C) Under the third growth condition, a second quantum well layer 321 with a thickness of 4 nm is grown on the first quantum barrier layer 312; the third growth condition includes: a growth temperature of 750° C., a growth pressure of 350 torr, and a V / III ratio of 11000.

[0175] D) Under the fourth growth condition, a second quantum barrier layer 322 with a thickness of 7 nm is grown on the second quantum well layer 321 ; the fourth growth condition includes: a growth temperature of 800° C., a growth pressure of 350 torr, and a V / III ratio of 11000.

[0176] Under the fifth growth condition of a growth temperature of 900° C., a growth pressure of 100 torr, and a V / III ratio of 6500, a first barrier layer 41 with a thickness of 2 nm is grown on the light emitting layer 3 (specifically, the second quantum barrier layer 322 of the light emitting layer 3 ).

[0177] Under the sixth growth condition of a growth temperature of 850° C., a growth pressure of 100 torr, and a V / III ratio of 5000, a second barrier layer 42 with a thickness of 2 nm is grown on the first barrier layer 41 .

[0178] Under the seventh growth condition of a growth temperature of 800° C., a growth pressure of 350 torr, and a V / III ratio of 12000, a diffusion layer 43 with a thickness of 3 nm is grown on the second barrier layer 42 .

[0179] The first condition includes: annealing pressure of 450 torr, introduction time of Mg source of 7 seconds, and first annealing temperature of 1000°C.

[0180] Under the eighth growth condition of a growth temperature of 750° C., a growth pressure of 300 torr, and a V / III ratio of 2600, a first P-type layer 51 doped with Mg is grown on the intermediate layer 4 .

[0181] The growth thickness of the first P-type layer 51 is 50 nm, and the doping concentration of Mg in the first P-type layer 51 is 5×10 19 cm -3 .

[0182] Under the ninth growth condition of a growth temperature of 950° C., a growth pressure of 400 torr, and a V / III ratio of 2600, a second P type layer 52 doped with Mg is grown on the first P type layer 51 .

[0183] The growth thickness of the second P-type layer 52 is 110 nm, and the doping concentration of Mg in the second P-type layer 52 is 5×10 19 cm -3 .

[0184] Example 3

[0185] The growth thickness of the N-type layer 2 is 10 μm; the doping concentration of Si in the N-type layer 2 is 8×10 18 cm -3 The growth conditions of the N-type layer 2 include: a growth temperature of 1200° C., a growth pressure of 600 torr, and a V / III ratio of 5000.

[0186] The number of the first light emitting structures 31 is fifteen.

[0187] A) Under a first growth condition, a first quantum well layer 311 with a thickness of 5 nm is grown on the N-type layer 2; the first growth condition includes: a growth temperature of 850° C., a growth pressure of 500 torr, and a V / III ratio of 10,000.

[0188] B) Under a second growth condition, growing a first quantum barrier layer with a thickness of 25 nm on the first quantum well layer; the second growth condition includes: a growth temperature of 950° C., a growth pressure of 500 torr, and a V / III ratio of 10,000.

[0189] The number of the second light emitting structures 32 is fifteen.

[0190] C) Under the third growth condition, a second quantum well layer 321 with a thickness of 6 nm is grown on the first quantum barrier layer 312; the third growth condition includes: a growth temperature of 850° C., a growth pressure of 500 torr, and a V / III ratio of 20,000.

[0191] D) Under the fourth growth condition, a second quantum barrier layer 322 with a thickness of 10 nm is grown on the second quantum well layer 321 ; the fourth growth condition includes: a growth temperature of 950° C., a growth pressure of 500 torr, and a V / III ratio of 20,000.

[0192] Under the fifth growth condition of a growth temperature of 1000° C., a growth pressure of 150 torr, and a V / III ratio of 10000, a first barrier layer 41 with a thickness of 3 nm is grown on the light emitting layer 3 (specifically, the second quantum barrier layer 322 of the light emitting layer 3 ).

[0193] Under the sixth growth condition of a growth temperature of 1000° C., a growth pressure of 150 torr, and a V / III ratio of 8000, a second barrier layer 42 with a thickness of 3 nm is grown on the first barrier layer 41 .

[0194] Under the seventh growth condition of a growth temperature of 950° C., a growth pressure of 500 torr, and a V / III ratio of 20000, a diffusion layer 43 with a thickness of 5 nm is grown on the second barrier layer 42 .

[0195] The first conditions include: annealing pressure of 600 torr, introduction time of Mg source of 10 seconds, and first annealing temperature of 1100°C.

[0196] Under the eighth growth condition of a growth temperature of 850° C., a growth pressure of 400 torr, and a V / III ratio of 5000, a first P-type layer 51 doped with Mg is grown on the intermediate layer 4 .

[0197] The growth thickness of the first P-type layer 51 is 100 nm, and the doping concentration of Mg in the first P-type layer 51 is 1×10 20 cm -3 .

[0198] Under the ninth growth condition of a growth temperature of 1050° C., a growth pressure of 600 torr, and a V / III ratio of 5000, a second P type layer 52 doped with Mg is grown on the first P type layer 51 .

[0199] The growth thickness of the second P-type layer 52 is 200 nm, and the doping concentration of Mg in the second P-type layer 52 is 1×10 20 cm -3 .

[0200] Example 4

[0201] The difference from Example 2 is:

[0202] The third growth condition includes: a V / III ratio of 5000.

[0203] The fourth growth condition includes: a V / III ratio of 5000.

[0204] It can be seen from Examples 2 and 4 that when the V / III ratio of growing the second quantum well layer and the second quantum barrier layer is not greater than the V / III ratio of growing the first quantum well layer and the first quantum barrier layer, the brightness is significantly reduced, the voltage increases, and the leakage performance and ESD performance are reduced.

[0205] Example 5

[0206] The difference from Example 2 is:

[0207] The third growth condition includes: a V / III ratio of 5500.

[0208] The fourth growth condition includes: a V / III ratio of 6600.

[0209] Example 6

[0210] The difference from Example 2 is:

[0211] The third growth condition includes: a V / III ratio of 6500.

[0212] The fourth growth condition includes: a V / III ratio of 7500.

[0213] Through Examples 5 and 6, it can be seen that when the V / III ratio of the second quantum well layer and the first quantum well layer and the V / III ratio of the second quantum barrier layer and the first quantum barrier layer are both greater than 1.2, the brightness increases, the voltage decreases, and the leakage and ESD performances are improved.

[0214] Example 7

[0215] The difference from Example 2 is:

[0216] Under the fifth growth condition of a V / III ratio of 6500, a first barrier layer 41 with a thickness of 2 nm is grown on the light emitting layer 3 .

[0217] Under the sixth growth condition in which the V / III ratio is 8000, the second barrier layer 42 with a thickness of 2 nm is grown on the first barrier layer 41 .

[0218] Under the seventh growth condition in which the V / III ratio is 12000, a diffusion layer 43 with a thickness of 3 nm is grown on the second barrier layer 42 .

[0219] It can be seen from Examples 2 and 7 that when the V / III ratio of the growing diffusion layer 43 is greater than the V / III ratio of the growing second barrier layer and greater than the V / III ratio of the growing first barrier layer, the brightness increases, the voltage decreases, and the leakage and ESD performances improve.

[0220] Example 8

[0221] The difference from Example 2 is:

[0222] The intermediate layer 4 includes a diffusion layer 43 , a second barrier layer 42 , and a first barrier layer 41 which are sequentially stacked and grown.

[0223] Under the seventh growth condition of a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 5000, a diffusion layer 43 with a thickness of 2 nm is grown on the light emitting layer 3 (specifically, the second quantum barrier layer 322 of the light emitting layer 3). The material of the diffusion layer 43 is InGaN.

[0224] Under the sixth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 2000, a second barrier layer 42 with a thickness of 1 nm is grown on the diffusion layer 43. The material of the second barrier layer 42 is AlGaN.

[0225] Under the fifth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 3000, a first barrier layer 41 with a thickness of 1 to 3 nm is grown on the second barrier layer 42. The material of the first barrier layer 41 is AlN.

[0226] It can be seen from Examples 2 and 8 that when the growth positions of the diffusion layer 43 and the first barrier layer 41 are interchanged, the brightness is improved under high current conditions.

[0227] Example 9

[0228] The difference from Example 2 is:

[0229] The pretreatment further includes a second step which is repeated and cycled alternately with the first step, the second step including: after interrupting the introduction of the Mg source into the reaction chamber, performing thermal annealing under second conditions, the second conditions including at least a second annealing temperature.

[0230] The second condition also includes: an annealing pressure of 450 torr, an interruption time of the Mg source of 7 seconds, and a second annealing temperature of 900°C.

[0231] It can be seen from Examples 2 and 9 that when the Mg source is introduced into the annealing and the annealing is interrupted in a cycle and alternating manner, and the annealing temperature is greater than the temperature of the P-type layer, the wavelength uniformity is significantly improved and the brightness is increased.

[0232] Example 10

[0233] The difference from Example 9 is:

[0234] Under the ninth growth condition of a growth temperature of 960° C., a second P type layer 52 doped with Mg is grown on the first P type layer 51 .

[0235] Embodiment 11

[0236] The difference from Example 9 is:

[0237] Under the ninth growth condition of a growth temperature of 970° C., a second P type layer 52 doped with Mg is grown on the first P type layer 51 .

[0238] Example 12

[0239] The difference from Example 9 is:

[0240] Under the ninth growth condition of a growth temperature of 900° C., a second P type layer 52 doped with Mg is grown on the first P type layer 51 .

[0241] Embodiment 13

[0242] The difference from Example 9 is:

[0243] Under the ninth growth condition of a growth temperature of 890° C., a second P type layer 52 doped with Mg is grown on the first P type layer 51 .

[0244] It can be seen from Examples 9-13 that when the temperature difference between the second annealing temperature and the growth temperature of the second P-type layer 52 is less than 40°C, the brightness decreases, the voltage increases, and the leakage and ESD performances decrease; when the temperature difference is greater than or equal to 40°C and less than or equal to 100°C, the brightness, voltage, leakage and ESD performances are optimal; when the temperature difference is greater than 100°C, the brightness, voltage, leakage and ESD performances do not change much, the parameter performance no longer increases, and the significant performance tends to be stable.

[0245] Embodiment 14

[0246] The difference from Example 9 is:

[0247] The first growth condition includes: a growth temperature of 690°C.

[0248] Embodiment 15

[0249] The difference from Example 9 is:

[0250] The third growth condition includes: a growth temperature of 690°C.

[0251] It can be seen from Examples 9, 14 and 15 that when the second annealing temperature is higher than the growth temperature of the first quantum well 311 and the second quantum well layer 321 by more than 300°C, the wavelength uniformity deteriorates significantly, and the brightness, voltage, leakage and ESD performances are significantly reduced.

[0252] Example 16

[0253] The difference from Example 12 is:

[0254] During the repeated cycle alternation, the temperature is linearly decreased during the first step to the second step, and then the temperature is linearly increased to the first step during the second step.

[0255] Specifically, during the first step, the first annealing temperature of 1000°C is linearly reduced at a frequency of 2°C per second within 20 seconds to the second retreating temperature of 960°C in the second step, and then during the second step, the second retreating temperature of 960°C is linearly increased at a frequency of 2°C per second within 20 seconds to the first annealing temperature of 1000°C in the first step.

[0256] It can be seen from Examples 12 and 16 that the temperature is linearly reduced to the second step during the first step, and then the temperature is linearly increased to the first step during the second step, and the wavelength uniformity and brightness parameters are significantly improved, and the performance is more excellent.

[0257] Embodiment 17

[0258] The difference from Example 16 is that:

[0259] During the repeated cycle alternation, the temperature increases linearly during the first step to the second step, and then decreases linearly to the first step during the second step.

[0260] Specifically, during the first step, the first annealing temperature of 1000°C is linearly increased at a frequency of 2°C per second within 30 seconds to the second retreating temperature of 1060°C in the second step, and then during the second step, the second retreating temperature of 1060°C is linearly reduced at a frequency of 2°C per second within 30 seconds to the first annealing temperature of 1000°C in the first step.

[0261] It can be seen from Examples 16 and 17 that the temperature increases linearly from the first step to the second step, and then decreases linearly to the first step during the second step, and the wavelength uniformity and brightness parameters are further significant, and the performance is more excellent.

[0262] Comparative Example 1

[0263] The present invention provides a comparative example 1, which provides a method for preparing an epitaxial wafer, and the method includes the following steps S1 to S4.

[0264] Step S1: providing a substrate 1.

[0265] The substrate 1 is a Si substrate.

[0266] Step S2: epitaxially growing an N-type layer 2,

[0267] The laminated structure of the light emitting layer 3 and the intermediate layer 4.

[0268] Step S2 includes steps S21 to S23.

[0269] Step S21: epitaxially growing a Si-doped N-type layer 2 on the substrate 1 by MOCVD.

[0270] The material of the N-type layer 2 is n-type GaN, and the growth thickness of the N-type layer 2 is 1 μm; the doping concentration of Si in the N-type layer 2 is 1×10 18 cm -3 The growth conditions of the N-type layer 2 include: a growth temperature of 1000° C., a growth pressure of 100 torr, and a V / III ratio of 500.

[0271] Step S22: epitaxially growing the light emitting layer 3 on the N-type layer 2 by MOCVD.

[0272] The light emitting layer 3 includes a first light emitting layer and a second light emitting layer that are grown in sequence. The process of growing the light emitting layer 3 includes steps S221 and S222.

[0273] Step S221: growing at least one first light emitting structure 31 on the N-type layer 2 to obtain a first light emitting layer. The number of the first light emitting structure 31 is one.

[0274] The first light emitting structure 31 includes a first quantum well layer 311 and a first quantum barrier layer 312 that are sequentially stacked. Growing the first light emitting structure 31 includes:

[0275] A) Under a first growth condition, a first quantum well layer 311 with a thickness of 1 nm is grown on the N-type layer 2; the first growth condition includes: a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 1000.

[0276] B) Under a second growth condition, a first quantum barrier layer with a thickness of 6 nm is grown on the first quantum well layer; the second growth condition includes: a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 1000.

[0277] Step S222: growing at least one second light emitting structure 32 on the first light emitting layer to obtain a second light emitting layer, wherein the number of the second light emitting structure 32 is one.

[0278] The second light emitting structure 32 includes a second quantum well layer 321 and a second quantum barrier layer 322 that are sequentially stacked. Growing the second light emitting structure 32 includes:

[0279] C) Under the third growth condition, a second quantum well layer 321 with a thickness of 2 nm is grown on the first quantum barrier layer 312; the third growth condition includes: a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 2000.

[0280] D) Under the fourth growth condition, a second quantum barrier layer 322 with a thickness of 3 nm is grown on the second quantum well layer 321 ; the fourth growth condition includes: a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 2000.

[0281] The material of the first quantum well layer 311 and the second quantum well layer 321 is InGaN, and the material of the first quantum barrier layer 312 and the second quantum barrier layer 322 is GaN.

[0282] Step S23: epitaxially growing the intermediate layer 4 on the light emitting layer 3 by MOCVD process.

[0283] See attached Figure 1 As shown, the intermediate layer 4 includes a first barrier layer 41, a second barrier layer 42 and a diffusion layer 43 which are grown in sequence. The growth of the intermediate layer 4 includes steps S23a to S25a.

[0284] Step S23a: Under the fifth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 3000, a first barrier layer 41 with a thickness of 1 to 3 nm is grown on the light emitting layer (specifically, the second quantum barrier layer of the light emitting layer). The material of the first barrier layer 41 is AlN.

[0285] Step S24a: Under the sixth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 2000, a second barrier layer 42 with a thickness of 1 nm is grown on the first barrier layer 41. The material of the second barrier layer 42 is AlGaN.

[0286] Step S25a: Under the seventh growth condition of a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 5000, a diffusion layer 43 with a thickness of 2 nm is grown on the second barrier layer 42 . The material of the diffusion layer 43 is InGaN.

[0287] Based on the above steps, a stacked structure is obtained, which includes an N-type layer 2, a light-emitting layer 3 and an intermediate layer 4 which are sequentially stacked on a substrate 1.

[0288] Step S3: epitaxially growing a P-type layer 5 on the middle layer 4 of the stacked structure by MOCVD process.

[0289] The P-type layer 5 includes a first P-type layer 51 and a second P-type layer 52 that are grown in sequence, and growing the P-type layer 5 includes steps S41 and S42 .

[0290] Step S31 : growing a first P-type layer 51 doped with Mg on the intermediate layer 4 under the eighth growth condition of a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 300.

[0291] The material of the first P-type layer 51 is p-type GaN, the growth thickness of the first P-type layer 51 is 10 nm, and the doping concentration of Mg in the first P-type layer 51 is 1×10 19 cm -3 .

[0292] Step S32 : growing a second P-type layer 52 doped with Mg on the first P-type layer 51 under the ninth growth condition of a growth temperature of 850° C., a growth pressure of 200 torr, and a V / III ratio of 300.

[0293] The material of the second P-type layer 52 is p-type GaN, the growth thickness of the second P-type layer 52 is 20-200 nm, and the doping concentration of Mg in the second P-type layer 52 is 1×10 19 cm -3 .

[0294] Comparative Example 2

[0295] The present invention provides a comparative example 2, which provides a method for preparing an epitaxial wafer, and the method includes the following steps S1 to S4.

[0296] Step S1: providing a substrate 1.

[0297] The substrate 1 is a Si substrate.

[0298] Step S2: epitaxially growing an N-type layer 2,

[0299] The laminated structure of the light emitting layer 3 and the intermediate layer 4.

[0300] Step S2 includes steps S21 to S23.

[0301] Step S21: epitaxially growing a Si-doped N-type layer 2 on the substrate 1 by MOCVD.

[0302] The material of the N-type layer 2 is n-type GaN, and the growth thickness of the N-type layer 2 is 1 μm; the doping concentration of Si in the N-type layer 2 is 1×10 18 cm -3 The growth conditions of the N-type layer 2 include: a growth temperature of 1000° C., a growth pressure of 100 torr, and a V / III ratio of 500.

[0303] Step S22: epitaxially growing the light emitting layer 3 on the N-type layer 2 by MOCVD.

[0304] The light emitting layer 3 includes a first light emitting layer and a second light emitting layer that are grown in sequence. The process of growing the light emitting layer 3 includes steps S221 and S222.

[0305] Step S221: growing at least one first light emitting structure 31 on the N-type layer 2 to obtain a first light emitting layer. The number of the first light emitting structure 31 is one.

[0306] The first light emitting structure 31 includes a first quantum well layer 311 and a first quantum barrier layer 312 that are sequentially stacked. Growing the first light emitting structure 31 includes:

[0307] A) Under a first growth condition, a first quantum well layer 311 with a thickness of 1 nm is grown on the N-type layer 2; the first growth condition includes: a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 1000.

[0308] B) Under a second growth condition, a first quantum barrier layer with a thickness of 6 nm is grown on the first quantum well layer; the second growth condition includes: a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 1000.

[0309] Step S222: growing at least one second light emitting structure 32 on the first light emitting layer to obtain a second light emitting layer, wherein the number of the second light emitting structure 32 is one.

[0310] The second light emitting structure 32 includes a second quantum well layer 321 and a second quantum barrier layer 322 that are sequentially stacked. Growing the second light emitting structure 32 includes:

[0311] C) Under the third growth condition, a second quantum well layer 321 with a thickness of 2 nm is grown on the first quantum barrier layer 312; the third growth condition includes: a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 2000.

[0312] D) Under the fourth growth condition, a second quantum barrier layer 322 with a thickness of 3 nm is grown on the second quantum well layer 321 ; the fourth growth condition includes: a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 2000.

[0313] The material of the first quantum well layer 311 and the second quantum well layer 321 is InGaN, and the material of the first quantum barrier layer 312 and the second quantum barrier layer 322 is GaN.

[0314] Step S23: epitaxially growing the intermediate layer 4 on the light emitting layer 3 by MOCVD process.

[0315] See attached Figure 1 As shown, the intermediate layer 4 includes a first barrier layer 41, a second barrier layer 42 and a diffusion layer 43 which are grown in sequence. The growth of the intermediate layer 4 includes steps S23a to S25a.

[0316] Step S23a: Under the fifth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 3000, a first barrier layer 41 with a thickness of 1 to 3 nm is grown on the light emitting layer (specifically, the second quantum barrier layer of the light emitting layer). The material of the first barrier layer 41 is AlN.

[0317] Step S24a: Under the sixth growth condition of a growth temperature of 750° C., a growth pressure of 50 torr, and a V / III ratio of 2000, a second barrier layer 42 with a thickness of 1 nm is grown on the first barrier layer 41. The material of the second barrier layer 42 is AlGaN.

[0318] Step S25a: Under the seventh growth condition of a growth temperature of 700° C., a growth pressure of 200 torr, and a V / III ratio of 5000, a diffusion layer 43 with a thickness of 2 nm is grown on the second barrier layer 42 . The material of the diffusion layer 43 is InGaN.

[0319] Based on the above steps, a stacked structure is obtained, which includes an N-type layer 2, a light-emitting layer 3 and an intermediate layer 4 which are sequentially stacked on a substrate 1.

[0320] Step S3: pre-processing the stacked structure.

[0321] Specifically, the pretreatment includes at least a first step, and the first step includes: after introducing a Mg source into the reaction chamber, performing a thermal annealing treatment under a first condition; the first condition includes at least a first annealing temperature.

[0322] The first condition also includes: annealing pressure of 300 torr, Mg source introduction time of 5 seconds, and first annealing temperature of 600°C.

[0323] Step S4: After pretreatment, epitaxially grow a P-type layer 5 on the middle layer 4 of the stacked structure by MOCVD process.

[0324] The P-type layer 5 includes a first P-type layer 51 and a second P-type layer 52 that are grown in sequence, and growing the P-type layer 5 includes steps S41 and S42 .

[0325] Step S41 : growing a first P-type layer 51 doped with Mg on the intermediate layer 4 under the eighth growth condition of a growth temperature of 650° C., a growth pressure of 200 torr, and a V / III ratio of 300.

[0326] The material of the first P-type layer 51 is p-type GaN, the growth thickness of the first P-type layer 51 is 10 nm, and the doping concentration of Mg in the first P-type layer 51 is 1×10 19 cm -3 .

[0327] Step S41 : growing a second P-type layer 52 doped with Mg on the first P-type layer 51 under the ninth growth condition of a growth temperature of 850° C., a growth pressure of 200 torr, and a V / III ratio of 300.

[0328] The material of the second P-type layer 52 is p-type GaN, the growth thickness of the second P-type layer 52 is 20-200 nm, and the doping concentration of Mg in the second P-type layer 52 is 1×10 19 cm -3 .

[0329] Comparative Example 3

[0330] The difference from Comparative Example 2 is:

[0331] The first annealing temperature is 800°C.

[0332] It can be seen from Example 1 and Comparative Examples 1-3 that when the first annealing temperature is greater than the growth temperature of the P-type layer 5, that is, the growth temperature of the second P-type layer 52, the wavelength uniformity is improved and the brightness performance is significantly improved.

[0333] The performance of the epitaxial wafers prepared in the above embodiments and comparative examples was tested, and the test results are shown in Table 1.

[0334] (i) Pass the photoluminescence (PL) test, including wavelength uniformity std and half-peak width HW.

[0335] (ii) The above-mentioned epitaxial wafers are made into LED chips using the same preparation process, and are tested using an LED photoelectric performance tester, including testing the voltage VF / V, luminous brightness Lop / mW under current injection conditions of 1mA and 5mA, and anti-static release ESD yield under a reverse breakdown voltage of 2000V, and leakage IR yield performance testing under a reverse voltage of 7V.

[0336] Table 1: Test data of epitaxial wafers of embodiments and comparative examples

[0337]

[0338]

[0339] It can be seen from the test data of the above Examples 1 to 17 and Comparative Examples 1 to 3 that:

[0340] Examples 1-17 have lower voltage, higher brightness, higher ESD and IR yields, indicating that the present invention solves the problem that the P-type structure doping caused by the Mg doping memory effect is difficult to reach the doping concentration set by the process, improves the brightness and anti-static release performance of the epitaxial wafer, and ensures the luminous efficiency of the epitaxial wafer. It should be noted that:

[0341] 1) Under the condition of 1mA current, Example 1-3 has higher brightness than Example 8, and under the condition of 5mA current, Example 8 has higher brightness than Example 1-3. This is because in Example 1-3, the P-type layer has a lower band gap barrier height toward the light-emitting layer, which is conducive to the injection of holes from the P-type layer to the light-emitting layer, improves the distribution uniformity of electrons and holes in the light-emitting layer, significantly improves the luminous brightness of the epitaxial wafer, and improves the luminous efficiency of the epitaxial wafer under low current working conditions; as the current injection increases, there is a risk of leakage of electrons in the light-emitting layer, which to a certain extent makes the luminous efficiency of the epitaxial wafer slightly lower than the luminous efficiency of the epitaxial wafer under low current working conditions, and in Example 8, the P-type layer has a high band gap barrier height difference toward the light-emitting layer, which affects the injection of holes from the P-type layer to the light-emitting layer under low current injection conditions, but can more effectively block the leakage of electrons injected from the N-type layer into the light-emitting layer into the P-type layer, so as the current injection increases, it has a higher luminous brightness under high current working conditions.

[0342] 2) Compared with Example 12, Examples 16 and 17 not only have lower voltage, higher brightness, higher ESD and IR yield, but also have lower emission wavelength uniformity std. This is because by controlling the linear change of the growth temperature, on the one hand, the time that the growth temperature is in a relatively high temperature section during the entire pretreatment thermal annealing process is reduced, thereby preventing the growth temperature from damaging the light-emitting structure during the thermal annealing process, thereby effectively improving the stability of the optoelectronic properties of the epitaxial wafer; on the other hand, the linear change of the growth temperature plays a role in annealing the light-emitting layer, and the deep energy level defects in the light-emitting layer can be effectively eliminated during the temperature change process. The atoms in the light-emitting layer can be fully migrated to improve the uniformity of the components, which can effectively improve the stability of the light-emitting wavelength and reduce wavelength drift and brightness attenuation.

[0343] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, substitute and modify the above embodiments within the scope of the invention without departing from the principles and purpose of the present invention. All such changes should fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: include: providing a substrate; epitaxially growing a stacked structure including an N-type layer, a light-emitting layer and an intermediate layer in sequence on the substrate; Pre-treating the stacked structure, the pre-treating comprising at least a first step, the first step comprising: after introducing a Mg source into a reaction chamber, performing a thermal annealing treatment under a first condition; the first condition comprising at least a first annealing temperature; After pretreatment, epitaxially growing a P-type layer on the middle layer of the stacked structure; Wherein, the intermediate layer has the function of preventing Mg from diffusing into the light-emitting layer during the pretreatment process; The first annealing temperature is higher than a growth temperature of the P-type layer.

2. The preparation method according to claim 1, characterized in that: The pretreatment further comprises a second step which is repeated and cycled alternately with the first step, wherein the second step comprises: after interrupting the introduction of the Mg source into the reaction chamber, performing a thermal annealing treatment under a second condition, wherein the second condition comprises at least a second annealing temperature; The second annealing temperature is higher than a growth temperature of the P-type layer.

3. The preparation method according to claim 2, characterized in that: The first condition includes: annealing pressure of 300-600 torr, Mg source introduction time of 5-20 seconds, first annealing temperature of 900-1100° C.; and / or The second conditions include: annealing pressure of 300-600 torr, interruption time of Mg source of 5-40 seconds, and second annealing temperature of 900-1100°C.

4. The preparation method according to claim 3, characterized in that: The light-emitting layer at least includes a first light-emitting layer and a second light-emitting layer that are grown in sequence. Growing the light-emitting layer includes: At least one first light-emitting structure is grown on the N-type layer to obtain a first light-emitting layer; the first light-emitting structure includes a first quantum well layer and a first quantum barrier layer that are grown in sequence, and growing the first light-emitting structure includes: Under the first growth condition, growing the first quantum well layer with a thickness of 1 to 5 nm on the N-type layer; the first growth condition includes: a growth temperature of 650 to 850° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 1000 to 10000; Under the second growth condition, the first quantum barrier layer with a thickness of 6 to 25 nm is grown on the first quantum well layer; the second growth condition includes: a growth temperature of 700 to 950° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 1000 to 10000; At least one second light-emitting structure is grown on the first light-emitting layer to obtain a second light-emitting layer; the second light-emitting structure includes a second quantum well layer and a second quantum barrier layer grown in sequence, and growing the second light-emitting structure includes: Under the third growth condition, growing the second quantum well layer with a thickness of 2 to 6 nm on the first quantum barrier layer; the growth temperature is 650 to 850° C., the growth pressure is 200 to 500 torr, and the V / III ratio is 2000 to 20000; Under the fourth growth condition, growing the second quantum barrier layer with a thickness of 3 to 10 nm on the second quantum well layer; the growth temperature is 700 to 950° C., the growth pressure is 200 to 500 torr, and the V / III ratio is 2000 to 20000; The V / III ratios of growing the second quantum well layer and the second quantum barrier layer are both greater than the V / III ratios of growing the first quantum well layer and the first quantum barrier layer.

5. The preparation method according to claim 1, characterized in that: The intermediate layer at least includes a first barrier layer, a second barrier layer and a diffusion layer that are grown in sequence; growing the intermediate layer includes: Under the fifth growth condition, the first barrier layer with a thickness of 1 to 3 nm is grown on the light-emitting layer, wherein the fifth growth condition includes: a growth temperature of 750 to 1000° C., a growth pressure of 50 to 150 torr, and a V / III ratio of 100 to 2000; Under the sixth growth condition, growing the second barrier layer with a thickness of 1 to 3 nm on the first barrier layer, the sixth growth condition comprising: a growth temperature of 750 to 1000° C., a growth pressure of 50 to 150 torr, and a V / III ratio of 2000 to 8000; Under the seventh growth condition, the diffusion layer with a thickness of 2-5 nm is grown on the second barrier layer, wherein the seventh growth condition includes: a growth temperature of 700-950° C., a growth pressure of 200-500 torr, and a V / III ratio of 5000-20000; The V / III ratio of growing the diffusion layer is greater than the V / III ratio of growing the second barrier layer and greater than the V / III ratio of growing the first barrier layer.

6. The preparation method according to claim 1, characterized in that: The intermediate layer at least includes a diffusion layer, a second barrier layer and a first barrier layer which are grown in sequence; and growing the intermediate layer includes: Under the seventh growth condition, the diffusion layer with a thickness of 2 to 5 nm is grown on the light-emitting layer; the seventh growth condition includes: a growth temperature of 700 to 950° C., a growth pressure of 200 to 500 torr, and a V / III ratio of 5000 to 20000; Under the sixth growth condition, growing the second barrier layer with a thickness of 1-3 nm on the diffusion layer; the sixth growth condition includes: a growth temperature of 750-1000° C., a growth pressure of 50-150 torr, and a V / III ratio of 2000-8000; Under the fifth growth condition, the first barrier layer with a thickness of 1 to 3 nm is grown on the second barrier layer; the fifth growth condition includes: a growth temperature of 750 to 1000° C., a growth pressure of 50 to 150 torr, and a V / III ratio of 100 to 2000; The V / III ratio of growing the diffusion layer is greater than the V / III ratio of growing the second barrier layer and greater than the V / III ratio of growing the first barrier layer.

7. The preparation method according to claim 4, characterized in that: The P-type layer at least includes a first P-type layer and a second P-type layer that are grown in sequence, and growing the P-type layer includes: Under the eighth growth condition, a first P-type layer with a thickness of 10-100 nm is grown on the intermediate layer, wherein the eighth growth condition includes: a growth temperature of 650-850° C., a growth pressure of 200-400 torr, and a V / III ratio of 300-5000; Under the ninth growth condition, a second P type layer with a thickness of 20 to 200 nm is grown on the first P type layer. The ninth growth condition includes: a growth temperature of 850 to 1050° C., a growth pressure of 200 torr to 600 torr, and a V / III ratio of 300 to 5000.

8. The preparation method according to claim 7, characterized in that: The second annealing temperature is higher than the growth temperature of the second P-type layer and is in the range of 40° C. to 100° C.; and / or The second annealing temperature is not higher than the growth temperature of the first quantum well layer and the second quantum well layer, which is 300° C.

9. The preparation method according to claim 8, characterized in that: During the repeated cycle alternation, the temperature during the first step is linearly reduced to the second step, and then the temperature during the second step is linearly increased to the first step; or during the repeated cycle alternation, the temperature during the first step is linearly increased to the second step, and then the temperature during the second step is linearly reduced to the first step.

10. A semiconductor device, characterized in that: The semiconductor device comprises an epitaxial wafer, and the epitaxial wafer is prepared by the method for preparing an epitaxial wafer according to any one of claims 1 to 9.

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