Voltage-withstanding MOSFET device for high-load shutdown of robot dog and preparation method of voltage-withstanding MOSFET device

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a voltage-withstanding MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device for high-load shutdown of a robot dog and a preparation method thereof, the voltage-withstanding MOSFET device comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; laterally symmetrical L-type P-layers with inclined tops and arc-shaped opposite side tops are introduced to the two sides of an N drift layer, and in cooperation with the middle buffering effect of a lightly doped N layer, local electric field concentration at the edge of the N drift layer in a traditional device can be accurately dispersed; the arc-shaped and L-shaped contours defined by the photoetching process can effectively guide the electric field to be uniformly distributed, so that the breakdown risk caused by too strong local electric field is avoided.

Description

High-voltage MOSFET device for high-load shutdown of robot dogs and its fabrication method Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a voltage-resistant MOSFET device for high-load shutdown of a robot dog and its fabrication method. Background Technology

[0002] In the fields of power semiconductors and special robot drives, power MOSFETs, as the core switching devices for robot dog joint control, high-load emergency stop, and safe shutdown, directly determine the overall dynamic response, energy efficiency, and operational reliability. Faced with the harsh operating conditions of robot dogs, including high dynamics, high current, frequent start-stop, and sudden shutdown, traditional silicon-based MOSFETs struggle to balance voltage margin, electric field uniformity, conduction losses, and switching speed. In particular, they are susceptible to back EMF and voltage spikes during high-load shutdown, becoming a key bottleneck restricting the upgrading of quadruped robots towards high load, high reliability, and long endurance.

[0003] Existing patent (publication number CN120201742A) discloses a variable-doped planar gate silicon carbide VDMOS device and its fabrication process. The device comprises several parallel MOS cells. Each MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, a P+ layer, an N-well layer, and a P-well layer. A lightly doped N-layer is located in the middle of the N-drift layer of each MOS cell. Laterally symmetric P-layers are located inside each MOS cell and on both sides of the N-drift layer, with corresponding side cross-sectional profiles of the laterally symmetric P-layers being arc-shaped. This invention optimizes the electric field distribution of the device by placing a lightly doped N-layer in the middle of the N-drift layer and introducing arc-shaped laterally symmetric P-layers on both sides. This reduces local electric field concentration, significantly improves the breakdown voltage, and enhances the charge balance capability through enhanced contact between the laterally symmetric P-layers and the N-substrate layer, reducing leakage current.

[0004] However, key challenges remain to be overcome. Regarding electric field control, while semiconductor die layout and connections have been considered, the problem of localized electric field concentration remains unresolved. Traditional devices are prone to electric field concentration at the edges of the N-drift layer due to structural and doping distribution limitations, creating a potential breakdown risk. Under high-voltage conditions, this also reduces the breakdown voltage, limiting their application in high-voltage power electronics. Existing methods also have significant shortcomings in terms of on-resistance and switching losses: they fail to effectively construct low-resistance carrier transport channels, making it difficult to increase carrier concentration; high on-resistance increases energy loss and heat dissipation costs, and reduces energy conversion efficiency; furthermore, they fail to optimize carrier extraction paths and suppress minority carrier storage effects, resulting in high reverse recovery charge and switching losses during high-frequency switching, which cannot meet the requirements of high-frequency scenarios. It is evident that existing patented technologies have significant room for improvement in these key performance indicators, and innovative solutions are urgently needed to overcome bottlenecks and comprehensively improve semiconductor device performance. Therefore, we propose a high-voltage MOSFET device for high-load shutdown of a robot dog and its fabrication method. Summary of the Invention

[0005] This invention provides a high-voltage MOSFET device and its fabrication method for high-load shutdown of a robot dog to solve the existing technical problems, thus resolving the issues mentioned in the background art.

[0006] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a voltage-resistant MOSFET device for high-load shutdown of a robot dog, comprising a plurality of parallel MOS cells, each MOS cell including a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer including an N-substrate layer, an N-drift layer, a P+ layer, an N-well layer, and a P-well layer, wherein a lightly doped N-layer is provided in the middle of the N-drift layer of each MOS cell; a laterally symmetrical L-type P-layer is provided inside the MOS cell and on the left and right sides of the N-drift layer, the top cross-sectional profile of the opposite side of the laterally symmetrical L-type P-layer is arc-shaped; the bottom end of the laterally symmetrical L-type P-layer contacts the N-substrate layer, and the top ends of the laterally symmetrical L-type P-layer are relatively inclined.

[0007] Furthermore, a heavily doped N layer is formed at the bottom of the lightly doped N layer through ion implantation. The bottom of the heavily doped N layer is in contact with the N substrate. The top middle part of the cross-sectional profile of the heavily doped N layer is concave semi-circular, and the two sides of the top are relatively inclined.

[0008] Furthermore, a concave P-layer is formed in the inner middle region of the heavily doped N layer through ion implantation. The bottom end of the concave P-layer contacts the N substrate layer, and the top of the cross-sectional profile of the concave P-layer is a concave arc surface.

[0009] Furthermore, lightly doped trapezoidal N layers are formed on both sides of the concave P-layer by ion implantation. The tops of the two lightly doped trapezoidal N layers are relatively inclined, and the tops of the lightly doped trapezoidal N layers are parallel to the bottom sides of the lightly doped N layers.

[0010] Furthermore, a convex P-layer is formed inside the lightly doped N-layer by ion implantation. The top of the convex P-layer contacts the lower surface of the gate, and the bottom of the cross-sectional profile of the convex P-layer is arc-shaped.

[0011] Furthermore, strip-shaped P-layers are formed on both sides of the interior of the heavily doped N-layer through ion implantation, and the top of the cross-sectional profile of the strip-shaped P-layers has a concave arc shape.

[0012] Furthermore, a concave N-layer is formed in the inner middle region of the heavily doped N-layer through ion implantation. The bottom end of the concave N-layer is in contact with the N substrate layer, and the two sides of the concave N-layer are in contact with the opposite sides of the two strip-shaped P-layers. The top of the cross-sectional profile of the concave N-layer is a concave arc surface.

[0013] Furthermore, the tops of both concave P-layers are formed with lightly doped trapezoidal N-layers by ion implantation. The top of the lightly doped trapezoidal N-layers is an inclined surface, and the top and bottom sides of the lightly doped trapezoidal N-layers are parallel.

[0014] A high-voltage MOSFET device for high-load shutdown of a robot dog and its fabrication method, comprising: S1, sequentially growing an N-substrate layer, an N-drift layer, a P+ layer, an N-well layer, and a P-well layer on a semiconductor epitaxial layer by chemical vapor deposition; S2, forming a lightly doped N-layer in the middle region of the N-drift layer by low-dose nitrogen ion implantation, followed by high-temperature annealing to activate the doped ions; S3, defining L-shaped mask windows with inclined tops and arc-shaped cross-sectional profiles at opposite ends on both sides of the N-drift layer using photolithography, forming a laterally symmetrical L-shaped P-layer by boron ion implantation to ensure that its bottom end contacts the N-substrate layer, and performing an annealing process after ion implantation to repair lattice damage; S4, in the bottom region of the lightly doped N-layer, through... S5. High-dose nitrogen ion implantation forms a heavily doped N-layer, followed by high-temperature annealing to activate impurities; S6. In the bottom region of the heavily doped N-layer, boron ion implantation is performed using a concave arc mask window to form a concave P-layer, followed by annealing; S7. In the bottom region of the heavily doped N-layer and on both sides of the concave P-layer, nitrogen ions are implanted using photolithography and ion implantation processes to form a lightly doped N-type half-layer, followed by annealing; S8. In the top region of the lightly doped N-layer, boron ion implantation is performed using a convex arc mask window to form a convex P-layer, followed by annealing; S9. Metal layers are sequentially deposited and patterned using photolithography or sputtering processes to form ohmic and Schottky contacts for the drain, source, and gate.

[0015] The present invention provides a high-voltage MOSFET device and its fabrication method for high-load shutdown of robot dogs. Compared with the prior art, the advantages of this method are as follows: 1. By introducing a laterally symmetrical L-shaped P-layer with a "top tilt + opposite side top arc shape" on both sides of the N drift layer, combined with the intermediate buffering effect of the lightly doped N layer, the local electric field concentration at the edge of the N drift layer in traditional devices can be accurately dispersed; the arc-shaped and L-shaped contours defined by the photolithography process can effectively guide the uniform distribution of the electric field and avoid the risk of breakdown caused by excessive local electric field; 2. The device's withstand voltage capability is significantly improved, making it more suitable for the high-voltage impact requirements under high-load shutdown conditions such as robot dogs. Compared with the traditional planar gate structure, the breakdown voltage improvement effect is outstanding.

[0016] 3. The concave arc surface of the concave P-layer, the inclined top of the lightly doped trapezoidal N-layer, and the parallel design of the bottom of the lightly doped N-layer ensure that the electric field direction is highly matched with the device structure outline, reducing electric field distortion. The concave N-layer and the strip P-layer work together to form a local electric field buffer region, further reducing the probability of electric field concentration under high load conditions, ensuring that the device works stably under high voltage and high stress environments, and meeting the instantaneous high withstand voltage requirements during the shutdown process of the robot dog.

[0017] 4. A heavily doped N-layer is formed by high-dose nitrogen ion implantation at the bottom of the lightly doped N-layer. After high-temperature annealing to activate impurities, a low-resistance carrier transport channel is constructed, which significantly increases the carrier concentration and reduces the on-resistance. The contour design of the heavily doped N-layer, which features a concave semi-circle at the top and tilted sides, shortens the carrier migration path and further reduces current transmission loss. The concentration gradient formed by the lightly doped trapezoidal N-layer and the local carrier buffer region constructed by the concave N-layer make carrier migration smoother and avoid the increase in transmission resistance caused by abrupt changes in concentration. The on-resistance is significantly reduced compared to the traditional structure, and the energy conversion efficiency is improved. This is beneficial for reducing power consumption and improving energy efficiency when the robot dog is shut down under high load.

[0018] 5. Concave, convex, and strip-shaped P-layers introduce holes through boron ion implantation, neutralizing excess electrons in heavily doped and lightly doped N-layers, achieving local charge balance, effectively suppressing parasitic bipolar conduction—a core problem leading to device latch-up failure—significantly reducing latch-up risk and preventing accidental device damage in high-load applications such as robot mode. Each ion implantation process is followed by high-temperature annealing, which activates the doped ions and repairs lattice damage caused by ion implantation, improving the crystal quality of the semiconductor layer. Laterally symmetrical L-type P-layers and complementary concave / convex layers are in direct contact with the N-substrate, enhancing structural stability and charge balance, reducing leakage current, and further improving device reliability under long-term, repeated high-load shutdown conditions. 6. The convex P-layer at the top of the lightly doped N-layer optimizes the tunneling effect—the core working mechanism of tunneling field-effect MOS transistors—by adjusting the local carrier distribution, enabling carriers to achieve "tunneling on" and "turn-off" faster under gate control, significantly improving switching response speed and making it more suitable for… This device meets the control requirements of high-frequency, fast switching. The combination of concave N-layer and strip P-layer reduces minority carrier storage effect, and the lightly doped trapezoidal N-layer optimizes the carrier extraction path, reducing reverse recovery charge when the device is turned off and lowering switching losses by 20%–30%. It has higher energy utilization efficiency under high-frequency conditions and can meet the stringent requirements of high-load fast shutdown and frequent start-stop in robot dogs. 7. This device has the advantages of improved breakdown voltage, reduced leakage current, and enhanced anti-latch-up capability. It can stably withstand the instantaneous high voltage and current surges during the high-load shutdown process of robot dogs. It is also suitable for high-voltage power electronics fields such as new energy vehicle inverters and industrial frequency converters, meeting the core requirements of "high voltage tolerance + long-term reliability". Its low on-resistance, fast switching response, and low switching loss characteristics can be used in high-frequency power modules, RF power devices, and other scenarios, solving the problem of "excessive loss and slow response" of traditional devices under high frequency and high load. It significantly expands the application boundaries of tunneling field-effect MOS transistors in special power electronics scenarios such as robot dog power systems and high-load actuators. Attached Figure Description

[0019] Figure 1 is a structural schematic diagram of embodiment 1 of the present invention; Figure 2 is a structural schematic diagram of embodiment 2 of the present invention; Figure 3 is a structural schematic diagram of embodiment 3 of the present invention; Figure 4 is a structural schematic diagram of embodiment 4 of the present invention; Figure 5 is a structural schematic diagram of embodiment 5 of the present invention; Figure 6 is a structural schematic diagram of embodiment 6 of the present invention; Figure 7 is a structural schematic diagram of embodiment 7 of the present invention; Figure 8 is a structural schematic diagram of embodiment 8 of the present invention.

[0020] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. Gate; 6. Lightly doped N layer; 7. Laterally symmetric L-type P- layer; 8. P+ layer; 9. N-well layer; 10. P-well layer; 11. Heavily doped N layer; 12. Concave P- layer; 13. Lightly doped trapezoidal N layer; 14. Convex P- layer; 15. Strip P- layer; 16. Concave N- layer; 17. Lightly doped trapezoidal N layer. Detailed Implementation

[0021] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] As shown in Figures 1-8, according to one aspect of the present invention, a voltage-resistant MOSFET device for high-load shutdown of a robot dog and a method for fabricating the same are provided, comprising: Step 1, sequentially growing an N-substrate layer 2, an N-drift layer 3, a P+ layer 8, an N-well layer 9, and a P-well layer 10 on a semiconductor epitaxial layer by chemical vapor deposition; sequentially growing an N-substrate layer 2, an N-drift layer 3, a P+ layer 8, an N-well layer 9, and a P-well layer 10 by chemical vapor deposition to construct the basic epitaxial structure of the device, ensuring that the thickness and doping concentration of each functional layer are controllable.

[0023] Step 2: A lightly doped N layer 6 is formed in the middle region of the N drift layer 3 by low-dose nitrogen ion implantation, followed by high-temperature annealing in an inert gas environment to activate the dopant ions; the formation of a lightly doped N layer 6 in the middle region of the N drift layer 3 by low-dose nitrogen ion implantation and high-temperature annealing reduces the resistance of the drift region and optimizes the conduction characteristics.

[0024] Step 3: Using photolithography, define L-shaped mask windows with tilted tops and rounded top cross-sectional profiles on both sides of the N drift layer 3. Form a side-symmetric L-shaped P-layer 7 by boron ion implantation to ensure that its bottom end contacts the N substrate layer. After ion implantation, perform an annealing process to repair lattice damage. Boron ions are implanted on both sides of the N drift layer 3 through L-shaped mask windows with tilted tops and rounded top cross-sectional profiles on both sides to form a side-symmetric L-shaped P-layer 7, which optimizes the electric field distribution, avoids local electric field concentration, and enhances charge balance by contacting the N substrate layer.

[0025] Step 4: In the bottom region of the lightly doped N layer 6, a heavily doped N layer 11 is formed by high-dose nitrogen ion implantation. After ion implantation, high-temperature annealing is performed to activate the impurities. High-dose nitrogen ions are implanted at the bottom of the lightly doped N layer 6 to form a heavily doped N layer 11, which increases the carrier concentration, reduces the on-resistance, and activates the impurities by high-temperature annealing.

[0026] Step 5: In the bottom region of the heavily doped N layer 11, boron ions are implanted using a concave arc mask window to form a concave P-layer 12, and then annealed. Implanting a concave P-layer 12 at the bottom of the heavily doped N layer 11 neutralizes excess electrons, suppresses parasitic bipolar effects, and improves latch-up resistance.

[0027] Step 6: In the bottom region of the heavily doped N-layer 11 and on both sides of the concave P-layer 16, nitrogen ions are implanted using photolithography and ion implantation processes to form a lightly doped N-type half-layer 13. After implantation, annealing is performed. Lightly doped N-type half-layers 13 are implanted on both sides of the bottom of the heavily doped N-layer 11 to form a concentration gradient, optimize the carrier migration path, and reduce conduction loss.

[0028] Step 7: In the top region of the lightly doped N-layer 6, boron ions are implanted using a convex arc mask window to form a convex P-layer 14, and then annealed. Implanting a convex P-layer 14 on the top of the lightly doped N-layer 6 adjusts the local carrier distribution, optimizes the tunneling effect, and improves the device switching performance.

[0029] Step 8: Sequentially deposit and pattern metal layers using photolithography or sputtering processes to form ohmic and Schottky contacts for drain 1, source 4, and gate 5; ohmic and Schottky contacts for drain 1, source 4, and gate 5 are formed using photolithography or sputtering processes to achieve electrical connection of the device and ensure good electrical performance and stability.

[0030] Example 1, as shown in Figure 1, describes a voltage-resistant MOSFET device for high-load shutdown of a robot dog. It comprises several parallel MOSFET cells. Each MOSFET cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer includes an N-substrate layer 2, an N-drift layer 3, a P+ layer 8, an N-well layer 9, and a P-well layer 10. The device is characterized by: a lightly doped N-layer 6 at the center of the N-drift layer 3 of each MOSFET cell; a laterally symmetrical L-type P-layer 7 located inside the MOSFET cell and on both sides of the N-drift layer 3, with the top cross-sectional profile of the opposite sides of the laterally symmetrical L-type P-layer 7 being arc-shaped; and the bottom end of the laterally symmetrical L-type P-layer 7 contacting the N-substrate layer 2. The tops of the side-symmetric L-type P-layer 7 are relatively tilted. The lightly doped N-layer 6 is formed by low-dose nitrogen ion implantation to reduce the drift region resistance. The side-symmetric L-type P-layer 7, with its tilted top and the opposite side having a rounded top, is formed by boron ion implantation through an L-shaped mask window defined by photolithography. Photolithography technology enables high-precision pattern transfer, ensuring that the shape and position of the P-layer meet the design requirements. After boron ion implantation, a high-temperature annealing process is used to repair lattice defects, promoting effective activation of dopant ions and ensuring the stability of the P-layer performance. This structure optimizes the device's electric field distribution by placing a lightly doped N-layer 6 in the middle of the N drift layer and introducing side-symmetric L-type P-layers 7 with tilted tops and the opposite side having a rounded top on both sides. The problem of local electric field concentration in traditional devices is significantly improved, effectively increasing the device breakdown voltage. The contact between the side-symmetric L-type P-layer 7 and the N substrate layer 2 enhances the charge balance capability, reduces leakage current, and improves the device's reliability and stability.

[0031] As shown in Figure 2, in Example 2, a heavily doped N-layer 11 is formed at the bottom of the lightly doped N-layer 6 through ion implantation. The bottom of the heavily doped N-layer 11 is in contact with the N-substrate layer 2. The top middle part of the cross-sectional profile of the heavily doped N-layer 11 is concave semi-circular, and the two sides of the top are relatively inclined. The heavily doped N-layer 11 is formed at the bottom of the lightly doped N-layer using high-dose nitrogen ion implantation technology. Its unique profile has an upward convex semi-circle at the top middle and relatively inclined sides. High-dose implantation significantly increases the carrier concentration. After implantation, high-temperature annealing is performed to fully activate the impurities and form a low-resistance channel inside the device. The introduction of this heavily doped N-layer 11 at the bottom of the lightly doped N-layer 6 not only further reduces the on-resistance, but also improves the carrier injection efficiency through high-concentration doping. The improved carrier injection efficiency allows the device to respond to signal changes faster during switching, significantly improving the switching performance and making it perform better in high-frequency applications. At the same time, the special profile design optimizes the current conduction path, taking into account both low resistance and electric field uniformity.

[0032] As shown in Figure 3, in Example 3, a concave P-layer 12 is formed in the middle region of the heavily doped N-layer 11 through ion implantation. The bottom end of the concave P-layer 12 contacts the N-substrate layer 2, and the top of the cross-sectional profile of the concave P-layer 12 has a concave arc-shaped surface. Boron ions are implanted through a concave arc mask window to form a concave P-layer 12 in the middle of the heavily doped N-layer. After implantation, it undergoes high-temperature annealing to ensure doping uniformity and performance stability. The concave arc-shaped surface design at the top of the concave P-layer 12 allows it to form a good electric field interaction with the surrounding structure. In the operation of semiconductor devices, high concentration of electrons can easily lead to charge distribution imbalance. This structure neutralizes high concentration of electrons through hole implantation in the concave P-layer 12, achieving local charge compensation. Charge compensation effectively suppresses parasitic bipolar effects, enhances the device's anti-latch-up capability, and further improves the overall performance and stability of the device while maintaining low on-resistance, thus avoiding unexpected device failure.

[0033] Example 4, as shown in Figure 4, involves ion implantation forming lightly doped trapezoidal N-layers 13 on both sides of the concave P-layer 16. The tops of the two lightly doped trapezoidal N-layers 13 are relatively inclined, and their tops are parallel to the bottom sides of the lightly doped N-layer 6. The lightly doped trapezoidal N-layers 13 are formed by precisely controlling the ion implantation dose and process parameters. Their relatively inclined tops and parallel bottom sides of the lightly doped N-layer 6 are followed by high-temperature annealing to ensure the activation and stable distribution of doped ions, which work synergistically with the concave P-layer 16 to improve the structural design. This structure optimizes the current conduction path, reduces on-resistance, and regulates the electric field distribution of the device. The inclined tops match the electric field direction, reducing electric field distortion and further improving the breakdown voltage while maintaining low on-resistance characteristics. In high-voltage and high-frequency applications, this effectively enhances the device's performance and operational stability.

[0034] As shown in Figure 5, in Example 5, a convex P-layer 14 is formed inside the lightly doped N-layer 6 through ion implantation. The top of the convex P-layer 14 contacts the lower surface of the gate 5, and the bottom of the cross-sectional profile of the convex P-layer 14 has an arc-shaped surface. The convex P-layer 14 is formed by boron ion implantation through a convex arc mask window. After implantation, it undergoes high-temperature annealing to ensure uniform doping concentration and stable performance. Its top contacts the lower surface of the gate 5, and the arc-shaped bottom surface design adapts to the electric field distribution below the gate. The introduction of the convex P-layer 14 adjusts the local carrier distribution at the top of the lightly doped N-layer 6, optimizing the tunneling effect. The improved tunneling effect makes carrier transport more efficient during device switching, significantly improving switching speed and response sensitivity. At the same time, the contact with the gate enhances the gate's control over the device's conductive channel, further optimizing the device's switching performance and operational stability.

[0035] As shown in Figure 6, in Example 6, strip-shaped P-layers 15 are formed on both sides of the heavily doped N-layer 11 through ion implantation, and the top of the cross-sectional profile of the strip-shaped P-layer 15 has a concave arc-shaped surface. The strip-shaped P-layer 15 is formed on both sides of the heavily doped N-layer 11 through ion implantation. The concave arc-shaped surface design at the top is achieved through precise mask window control. After implantation, it undergoes high-temperature annealing to ensure the activation of doped ions and structural stability. The strip-shaped P-layer 15 and the heavily doped N-layer 11 work together to further optimize the charge distribution and electric field distribution inside the device. The concave arc-shaped surface effectively disperses the local electric field, avoids electric field concentration, and improves the breakdown voltage of the device. At the same time, by injecting holes to neutralize some electrons, the parasitic bipolar effect is suppressed, the latch-up resistance of the device is enhanced, and the device maintains good stability under complex operating conditions.

[0036] As shown in Figure 7, in Example 7, a concave N-layer 16 is formed in the middle region of the heavily doped N-layer 11 through ion implantation. The bottom end of the concave N-layer 16 contacts the N-substrate layer 2, and the two sides of the concave N-layer 16 contact the opposite sides of the two strip P-layers 15. The top of the cross-sectional profile of the concave N-layer 16 has a concave arc-shaped surface. The concave N-layer 16 is formed in the middle region of the heavily doped N-layer 11 through ion implantation. Its bottom end contacts the N-substrate layer 2, and its two sides contact the strip P-layers 15. The concave arc-shaped surface at the top is designed to adapt to the electric field characteristics of the surrounding structure. After implantation, the impurities are activated by high-temperature annealing. The introduction of the concave N-layer 16 forms a local concentration gradient, optimizes the carrier migration path, reduces conduction loss, and works synergistically with the two strip P-layers 15 to further enhance charge balance capability, suppress leakage current generation, improve the internal electric field distribution of the device, reduce electric field distortion, and improve breakdown voltage and reliability. It is suitable for applications with high voltage and high reliability requirements.

[0037] As shown in Figure 8, in Example 8, the tops of the two concave P-layers 16 are formed with lightly doped trapezoidal N-layers 17 by ion implantation. The top of the lightly doped trapezoidal N-layers 17 is an inclined surface, and the top of the lightly doped trapezoidal N-layers 17 is parallel to the bottom sides of the lightly doped N-layers 6. The lightly doped trapezoidal N-layers 17 are formed on the top of the concave P-layers 16 by ion implantation. The inclined surface of the top is parallel to the bottom sides of the lightly doped N-layers 6. By precisely controlling the implantation process parameters, the shape and doping concentration are ensured to meet the design. After implantation, the performance is stabilized by high-temperature annealing. This structure, together with the concave P-layers 16 and the heavily doped N-layers 11, further optimizes the current conduction path and electric field distribution. The inclined top matches the electric field direction, reducing electric field concentration, improving the breakdown voltage, and reducing the on-resistance. During the switching process, it optimizes the carrier transport efficiency and reduces switching losses, enabling the device to perform better in high-voltage and high-frequency applications.

[0038] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A high-voltage MOSFET device for high-load shutdown of a robot dog, comprising a plurality of parallel MOS cells, each MOS cell including a drain (1), a semiconductor epitaxial layer, a source (4), and a gate (5); the semiconductor epitaxial layer including an N-substrate layer (2), an N-drift layer (3), a P+ layer (8), an N-well layer (9), and a P-well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; a side-symmetric L-type P-layer (7) is provided inside the single MOS cell and on the left and right sides of the N drift layer (3), and the top cross-sectional profile of the side-symmetric L-type P-layer (7) on both sides is arc-shaped; the bottom end of the side-symmetric L-type P-layer (7) is in contact with the N substrate layer (2), and the top ends of the side-symmetric L-type P-layer (7) on both sides are relatively inclined.

2. The withstand voltage MOSFET device for high-load shutdown of a robot dog according to claim 1, characterized in that: The bottom of the lightly doped N layer (6) is formed by ion implantation to form a heavily doped N layer (11). The bottom of the heavily doped N layer (11) is in contact with the N substrate layer (2). The top middle part of the cross-sectional profile of the heavily doped N layer (11) is concave semi-circular, and the top two sides are relatively inclined.

3. The withstand voltage MOSFET device for high-load shutdown of a robot dog according to claim 2, characterized in that: The heavily doped N layer (11) has a concave P-layer (12) formed in the middle region through ion implantation. The bottom end of the concave P-layer (12) is in contact with the N substrate layer (2), and the top of the cross-sectional profile of the concave P-layer (12) is a concave arc surface.

4. The voltage-resistant MOSFET device for high-load shutdown of a robot dog according to claim 3, characterized in that: The concave P-layer (16) has lightly doped trapezoidal N-layers (13) formed on both sides by ion implantation. The tops of the two lightly doped trapezoidal N-layers (13) are relatively inclined, and the tops of the lightly doped trapezoidal N-layers (13) are parallel to the bottom sides of the lightly doped N-layer (6).

5. The withstand voltage MOSFET device for high-load shutdown of a robot dog according to claim 4, characterized in that: The interior of the lightly doped N layer (6) is formed by ion implantation of a convex P-layer (14). The top of the convex P-layer (14) is in contact with the lower surface of the gate (5), and the bottom of the cross-sectional profile of the convex P-layer (14) is arc-shaped.

6. The withstand voltage MOSFET device for high-load shutdown of a robot dog according to claim 2, characterized in that: The heavily doped N-layer (11) has strip-shaped P-layers (15) formed on both sides of its interior by ion implantation, and the top of the cross-sectional profile of the strip-shaped P-layer (15) is a concave arc surface.

7. The voltage-resistant MOSFET device for high-load shutdown of a robot dog according to claim 6, characterized in that: The heavily doped N-layer (11) has a concave N-layer (16) formed in the middle region by ion implantation. The bottom end of the concave N-layer (16) is in contact with the N substrate layer (2). The two sides of the concave N-layer (16) are in contact with the opposite sides of the two strip-shaped P-layers (15). The top of the cross-sectional profile of the concave N-layer (16) is a concave arc surface.

8. The withstand voltage MOSFET device for high-load shutdown of a robot dog according to claim 7, characterized in that: The top of each of the two concave P-layers (16) is formed by ion implantation with a lightly doped trapezoidal N-layer (17). The top of the lightly doped trapezoidal N-layer (17) is an inclined surface, and the top of the lightly doped trapezoidal N-layer (17) is parallel to the bottom sides of the lightly doped N-layer (6).

9. A method for fabricating a voltage-resistant MOSFET device for high-load shutdown of a robot dog, characterized in that, The voltage-resistant MOSFET device for high-load shutdown of a robot dog as described in any one of claims 1-5, wherein the fabrication process includes: S1, sequentially growing an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9), and a P well layer (10) on a semiconductor epitaxial layer by chemical vapor deposition; S2, forming a lightly doped N layer (6) in the middle region of the N drift layer (3) by low-dose nitrogen ion implantation, followed by high-temperature annealing to activate the doped ions; S3, defining L-shaped mask windows with inclined tops and arc-shaped cross-sectional profiles at opposite ends on both sides of the N drift layer (3) using photolithography, forming a side-symmetric L-shaped P- layer (7) by boron ion implantation to ensure that its bottom end contacts the N substrate layer, and performing an annealing process after ion implantation to repair lattice damage; S4, in the bottom region of the lightly doped N layer (6) In the region, a heavily doped N layer (11) is formed by high-dose nitrogen ion implantation, and high-temperature annealing is performed after ion implantation to achieve impurity activation; S5, in the bottom region of the heavily doped N layer (11), boron ion implantation is performed using a concave arc mask window to form a concave P- layer (12), and annealing is performed; S6, in the bottom region of the heavily doped N layer (11) and on both sides of the concave P- layer (16), nitrogen ions are implanted using photolithography and ion implantation processes to form the lightly doped N-type half-layer (13), and annealing is performed after implantation; S7, in the top region of the lightly doped N layer (6), boron ion implantation is performed using a convex arc mask window to form a convex P- layer (14), and annealing is performed; S8, metal layers are sequentially deposited and patterned using photolithography or sputtering processes to form ohmic contacts and Schottky contacts for the drain (1), source (4) and gate (5).

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