Embedded flash memory structure and method of manufacturing the same

Abstract

The application provides an embedded flash memory structure and a manufacturing method thereof. The gate stack layer comprises a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer which are stacked in sequence. The floating gate layer comprises a plurality of mutually electrically isolated nano storage points. During programming, charges can be stored in the plurality of mutually electrically isolated nano storage points. When breakdown occurs in any nano storage point, the remaining undamaged nano storage points can still normally store charges due to the electric isolation between the nano storage points, so that the floating gate layer can maintain normal storage function, thereby improving the overall stability of the memory and increasing the service life of the memory. The application has six kinds of embedded flash memory cell structures. In particular, the tunneling oxide layer and the floating gate layer are arranged to protrude from both sides of the gate dielectric layer and the control gate layer, thereby greatly improving the programming speed of the embedded flash memory.

Description

Embedded flash memory structure and fabrication method Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an embedded flash memory structure and its fabrication method. Background Technology

[0002] In recent years, with the rapid development of the smart electronics market, the use of various microcontrollers (MCUs) and system-on-a-chip (SoC) chips has penetrated into all aspects of daily life, including automotive electronics, industrial control, and medical products. High-performance MCUs or SoCs rely heavily on high-performance embedded flash memory (eflash) cores. Whether considering chip area, system performance, power consumption, manufacturing yield, or design cycle time, the dominant role of embedded memory in SoC design is constantly increasing. Embedded flash memory combines existing flash memory with existing logic modules, either physically or electrically, to provide more diverse performance.

[0003] Embedded flash memory (eFlash), as the core storage unit of system-on-a-chip (SoC), is experiencing a surge in demand in fields such as the Internet of Things (IoT), automotive electronics, and artificial intelligence. However, existing embedded flash memory (eFlash) suffers from the following problems:

[0004] 1) Current mainstream floating-gate transistors employ a monolithic continuous polysilicon floating-gate structure. This involves placing a single continuous polysilicon floating gate between the control gate (CG) and the channel region, utilizing FN tunneling or hot carrier injection to store charge. However, monolithic floating gates are prone to dielectric layer breakdown (TDDB) induced by localized electric field concentration during high-voltage programming / erasing cycles. Once a point or region within the polysilicon floating gate breaks down, the charge stored throughout the entire floating gate is rapidly discharged through the breakdown point, resulting in global data loss.

[0005] 2) Due to the channel width limitation, the hot electron injection path is long, which greatly limits the improvement of embedded flash memory programming speed.

[0006] 3) The small contact area of ​​the planar eraser gate makes it easy for the driving capability to be insufficient, which can easily lead to instability in the erasure process and fluctuations in the actual voltage applied to the eraser gate.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an embedded flash memory structure and its manufacturing method, which solves the problems of easy overall failure of polysilicon floating gate and slow programming speed in the prior art embedded flash memory structure.

[0009] To achieve the above and other related objectives, the present invention provides an embedded flash memory structure, comprising: a semiconductor substrate; a gate stack layer formed on the semiconductor substrate, the gate stack layer comprising a tunnel oxide layer, a floating gate layer, a gate dielectric layer, and a control gate layer stacked sequentially, the floating gate layer including a plurality of electrically isolated nanometer storage points; isolation sidewalls and tunneling sidewalls respectively covering a first sidewall and a second sidewall on both sides of the tunnel oxide layer, the floating gate layer, the gate dielectric layer, and the control gate layer; a word line gate disposed on the side of the isolation sidewall; a drain region disposed in the semiconductor substrate and located on the side of the word line gate; a source region disposed in the semiconductor substrate on the side of the tunneling sidewall, the source region being covered by an insulating layer; and an erase gate disposed on the side of the tunneling sidewall and located on the insulating layer to isolate it from the source region.

[0010] Optionally, the nano-storage points include at least one of silicon nano-storage points, germanium nano-storage points, and silicon carbide nano-storage points; the particle size of the nano-storage points is 50 angstroms to 130 angstroms.

[0011] Optionally, the erase gate is made of polycrystalline silicon, and a groove structure is formed on the top of the erase gate. The groove structure is also filled with a metal layer, and the metal layer forms an ohmic contact with the polycrystalline silicon in the groove structure.

[0012] Optionally, the depth of the groove structure is 10% to 50% of the eraser gate height, and the groove structure includes one of a rectangular groove, a V-shaped groove, and a U-shaped groove.

[0013] Optionally, the width of the tunneling oxide layer and the floating gate layer is greater than the width of the gate dielectric layer and the control gate layer, and the tunneling oxide layer and the floating gate layer protrude from both sides of the gate dielectric layer and the control gate layer, and the isolation sidewall and the tunneling sidewall have corners at the top corners of the floating gate layer.

[0014] Optionally, the word line grid protrudes along the tunneling oxide layer and the floating gate layer and is recessed inward by a distance; the area between the drain area and the tunneling oxide layer and the floating gate layer is a channel area, and the width of the channel area is reduced by controlling the distance of the word line grid recessed inward.

[0015] Optionally, the tunneling oxide layer and the floating gate layer protrude from either side of the gate dielectric layer and the control gate layer by a width of 5 nm to 15 nm; or / and the width of the tunneling oxide layer and the floating gate layer is 100 nm to 130 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.

[0016] Optionally, the width of the tunneling oxide layer and the floating gate layer is greater than the width of the gate dielectric layer and the control gate layer, and the tunneling oxide layer and the floating gate layer protrude from the gate dielectric layer and the control gate layer on one side toward the erasure gate, while the other side is flush with the tunneling oxide layer and the floating gate layer, and the tunneling sidewall has a corner at the top corner of the floating gate layer.

[0017] Optionally, the tunneling oxide layer and the floating gate layer protrude from the gate dielectric layer and the control gate layer towards the erase gate side with a width of 5 nm to 15 nm; or / and the width of the tunneling oxide layer and the floating gate layer is 85 nm to 125 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.

[0018] Optionally, the tunneling oxide layer and the floating gate layer are equal to the width of the gate dielectric layer and the control gate layer, and the tunneling oxide layer and the floating gate layer are flush with both sides of the gate dielectric layer and the control gate layer.

[0019] Optionally, the thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer includes a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer, the thickness of the gate dielectric layer is 130 angstroms to 170 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, and the gate stack layer further includes a hard mask disposed on the control gate layer, the thickness of the hard mask being 500 angstroms to 1100 angstroms.

[0020] Optionally, the thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall is 90 angstroms to 110 angstroms.

[0021] Optionally, the cross-section of the insulating layer on the source region is elliptical, with both ends of the ellipse connected to the tunnel sidewall, wherein the thickness of the insulating layer in the middle is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms.

[0022] This invention also provides a method for fabricating an embedded flash memory structure, the method comprising the following steps: providing a semiconductor substrate; forming a gate stack layer on the semiconductor substrate, the gate stack layer comprising a tunnel oxide layer, a floating gate layer, a gate dielectric layer, and a control gate layer stacked sequentially, the floating gate layer comprising forming an amorphous material layer on the tunnel oxide layer, and annealing the amorphous material layer to aggregate into multiple electrically isolated nanometer storage points to form the floating gate layer; forming isolation sidewalls and tunnel sidewalls, the isolation sidewalls and tunnel sidewalls respectively covering the... The process includes a tunneling oxide layer, a floating gate layer, a gate dielectric layer, and first and second sidewalls on both sides of the control gate layer; a source region is formed in the semiconductor substrate, the source region being disposed in the semiconductor substrate on the side of the tunneling sidewall, and an insulating layer covering the source region; a word line gate is formed on the side of the isolation sidewall; an erase gate is formed, the erase gate being disposed on the side of the tunneling sidewall and located on the insulating layer to isolate it from the source region; and a drain region is formed in the semiconductor substrate, the drain region being disposed in the semiconductor substrate and located on the side of the word line gate.

[0023] Optionally, the annealing process is carried out under a nitrogen atmosphere, with an annealing temperature of 700℃~850℃, an annealing pressure of 70Torr~90Torr, an annealing time of 10s~20s, and a nitrogen flow rate of 5slm~15slm. The amorphous material layer includes at least one of silicon, germanium, and silicon carbide, and the nano-storage points include at least one of silicon nano-storage points, germanium nano-storage points, and silicon carbide nano-storage points, with a particle size of 50 angstroms~130 angstroms.

[0024] Optionally, forming a gate stack layer on the semiconductor substrate includes the steps of: sequentially forming a tunneling oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer, and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer, and the gate dielectric layer using photolithography and etching processes; forming sidewall structures on both sides of the patterned hard mask, the control gate layer, and the gate dielectric layer; using the patterned hard mask, the control gate layer, the gate dielectric layer, and the sidewall structures as masks, etching the floating gate layer and the tunneling oxide layer to pattern them, wherein the width of the tunneling oxide layer and the floating gate layer is greater than the width of the gate dielectric layer and the control gate layer, and the tunneling oxide layer and the floating gate layer protrude from both sides of the gate dielectric layer and the control gate layer, and the isolation sidewalls and tunneling sidewalls have corners at the top corners of the floating gate layer, wherein the width of the tunneling oxide layer and the floating gate layer protruding from the gate dielectric layer and the control gate layer is controlled by controlling the width of the sidewall structure.

[0025] Optionally, the word line grid protrudes along the tunneling oxide layer and the floating gate layer and is recessed inward by a distance. The area between the drain area and the tunneling oxide layer and the floating gate layer is a channel area. By controlling the distance of the word line grid being recessed inward, the width of the channel area can be reduced.

[0026] Optionally, the tunneling oxide layer and the floating gate layer protrude from either side of the gate dielectric layer and the control gate layer by a width of 5 nm to 15 nm; or the width of the tunneling oxide layer and the floating gate layer is 100 nm to 130 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.

[0027] Optionally, forming a gate stack layer on the semiconductor substrate includes the following steps: sequentially forming a tunnel oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer, and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer, and the gate dielectric layer using photolithography and etching processes; forming a sidewall structure on one side of the patterned hard mask, the control gate layer, and the gate dielectric layer facing the erase gate, while not forming a sidewall structure on the other side; using the patterned hard mask, the control gate layer, the gate dielectric layer, and the sidewall structure as a mask, etching the... The floating gate layer and the tunneling oxide layer are described in a graphical manner. The width of the tunneling oxide layer and the floating gate layer is greater than the width of the gate dielectric layer and the control gate layer. The tunneling oxide layer and the floating gate layer protrude from the gate dielectric layer and the control gate layer towards the erase gate side. The tunneling sidewall has a corner at the top corner of the floating gate layer. The other side of the tunneling oxide layer and the floating gate layer is flush with the tunneling oxide layer and the floating gate layer. The width of the tunneling oxide layer and the floating gate layer protruding from the gate dielectric layer and the control gate layer is controlled by controlling the width of the sidewall structure.

[0028] Optionally, forming a gate stack layer on the semiconductor substrate includes the steps of: sequentially forming a tunnel oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer, and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer, and the gate dielectric layer using photolithography and etching processes; and using the patterned hard mask, the control gate layer, and the gate dielectric layer as masks, etching the floating gate layer and the tunnel oxide layer to pattern them, wherein the width of the tunnel oxide layer and the floating gate layer is equal to the width of the gate dielectric layer and the control gate layer, and the tunnel oxide layer and the floating gate layer are flush with both sides of the gate dielectric layer and the control gate layer.

[0029] Optionally, forming the isolation sidewall and the tunneling sidewall includes the steps of: forming a first dielectric layer on the sidewall of the sidewall structure, the tunneling oxide layer, and the floating gate layer; removing the sidewall structure and the first dielectric layer on the second sidewall of the tunneling oxide layer, the floating gate layer, the gate dielectric layer, and the control gate layer; and forming a tunneling sidewall on the second sidewall of the tunneling oxide layer, the floating gate layer, the gate dielectric layer, and the control gate layer, whereby the sidewall structure, the first dielectric layer, and the tunneling oxide layer on the first sidewall of the control gate layer together constitute the isolation sidewall.

[0030] Optionally, forming the word line gate and the erase gate includes the steps of: forming a gate oxide layer on the surface of a semiconductor substrate by a thermal oxidation process; depositing a polysilicon layer on the semiconductor substrate and planarizing it to remove excess polysilicon layer from the surface, wherein the polysilicon layer deposited on one side of the tunnel sidewall serves as the erase gate, and by controlling the deposition parameters of the polysilicon layer, a groove structure is formed on the top of the erase gate; the polysilicon layer deposited on one side of the isolation sidewall serves as word line polysilicon; and etching the word line silicon to divide the word line polysilicon into two word line gates.

[0031] Optionally, the depth of the groove structure is 10% to 50% of the height of the erase gate, and the groove structure is further filled with a metal layer, which forms an ohmic contact with the polysilicon in the groove structure. The groove structure in the erase gate includes one of a rectangular groove, a V-groove, and a U-groove.

[0032] Optionally, forming the word line gate and erase gate includes the following steps: forming a gate oxide layer on the surface of a semiconductor substrate by thermal oxidation; depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on the tunnel sidewall serves as the erase gate, and the first polysilicon layer deposited on the isolation sidewall serves as word line polysilicon, and a groove structure is formed on the top of the erase gate and the top of the word line polysilicon; spin-coating an organic dielectric layer onto the erase gate and the word line polysilicon, the organic dielectric layer filling the groove structure; etching the organic dielectric layer by plasma etching until the first polysilicon layer is exposed, the organic dielectric layer remaining in the groove structure; selectively etching the first polysilicon layer to remove excess first polysilicon layer from the surface; removing the organic dielectric layer in the groove structure by wet etching; and etching the word line polysilicon to divide the word line polysilicon into two word line gates.

[0033] Optionally, forming the word line gate and the erase gate includes the step of: forming a gate oxide layer on the surface of a semiconductor substrate by a thermal oxidation process;

[0034] A first polysilicon layer is deposited on a semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunnel sidewall serves as an erase gate, and the first polysilicon layer deposited on one side of the isolation sidewall serves as word line polysilicon. A groove structure is formed on the top of both the erase gate and the top of the word line polysilicon. A second polysilicon layer is deposited on the erase gate and the word line polysilicon, and the second polysilicon layer fills the groove structure. Excess second polysilicon layer and first polysilicon layer on the surface are removed by planarization. The word line polysilicon is etched to divide the word line polysilicon into two word line gates.

[0035] Optionally, the thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer includes a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer, the thickness of the gate dielectric layer is 130 angstroms to 170 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, the thickness of the hard mask is 500 angstroms to 1100 angstroms; the thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall is 90 angstroms to 110 angstroms.

[0036] Optionally, an insulating layer is applied to the source region by a thermal oxidation process. The insulating layer on the source region has an elliptical cross-section, with both ends of the ellipse connected to the tunnel sidewall. The thickness of the insulating layer in the middle is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms.

[0037] As described above, the embedded flash memory structure and its manufacturing method of the present invention have the following beneficial effects:

[0038] The floating gate layer of this invention comprises multiple electrically isolated nano-storage points. During programming, charge can be stored in these electrically isolated nano-storage points. When any nano-storage point breaks down, because the nano-storage points are electrically isolated, the remaining undamaged nano-storage points can still store charge normally, allowing the floating gate layer to maintain normal storage function, thereby improving the overall stability of the memory and increasing its lifespan. The inclusion of multiple electrically isolated nano-storage points in the floating gate layer of this invention results in a more uniform electric field distribution, reduces electric field distortion in areas such as edges, and improves the voltage withstand capability of the floating gate layer.

[0039] This invention sets the width of the tunnel oxide layer and floating gate layer of the embedded flash memory to be greater than the width of the gate dielectric layer and the control gate layer, so that the tunnel oxide layer and floating gate layer protrude from both sides of the gate dielectric layer and the control gate layer. The word line gate protrudes along the tunnel oxide layer and floating gate layer and is recessed inward by a distance. By controlling the inward recess distance of the word line gate, the width of the channel region can be effectively reduced, thereby greatly shortening the path of electron injection into the floating gate layer during programming, and thus greatly improving the programming speed of the embedded flash memory. At the erase gate end, the protrusion of the floating gate layer can reduce the voltage required to pull electrons from the floating gate layer to the erase gate. At the same time, the insulating layer under the erase gate, due to ion implantation and oxidation during the process, naturally becomes very thick. This allows for a higher voltage to be applied to the erase gate without causing the insulating layer to break down, thereby greatly improving the process variation window. Our embedded flash memory and its manufacturing method combine all the above advantages, making this embedded flash memory cell more process compatible, more reliable, and with better performance.

[0040] The erasure grid of the present invention has a groove structure on the top. The groove structure forms an ohmic contact with the metal layer, which can greatly increase the contact area between the metal layer and the erasure grid, improve its driving effect, and thus improve the speed and stability of the erasure grid erasure operation.

[0041] This invention features a thick insulating layer on the source region, which effectively increases the erase voltage that can be applied to the erase gate without damaging the device, thus ensuring extremely high erase efficiency and stability. Since a sufficiently high voltage can be applied to the erase gate, there is no need to apply a negative voltage to the control gate, significantly reducing the design complexity of the application circuit. Attached Figure Description

[0042] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0043] Figure 1 shows a schematic diagram of the embedded flash memory structure of Embodiment 1 of the present invention.

[0044] Figure 2 shows a schematic diagram of the embedded flash memory structure of Embodiment 2 of the present invention.

[0045] Figure 3 shows a schematic diagram of the embedded flash memory structure of Embodiment 3 of the present invention.

[0046] Figure 4 shows a schematic diagram of the embedded flash memory structure of Embodiment 4 of the present invention.

[0047] Figure 5 shows a schematic diagram of the embedded flash memory structure of Embodiment 5 of the present invention.

[0048] Figure 6 shows a schematic diagram of the embedded flash memory structure of Embodiment 6 of the present invention.

[0049] Figures 7 and 8 show example diagrams of the operation method of the embedded flash memory according to an embodiment of the present invention.

[0050] Figures 9 to 35 show schematic diagrams of the corresponding steps in the fabrication method of embedded flash memory according to Embodiments 1 to 6 of the present invention.

[0051] Component designation explanation

[0052] 101 Semiconductor Substrate

[0053] 102 then penetrated the oxide layer

[0054] 103 Floating Grid Layer

[0055] 1031 nanometer storage point

[0056] 104 Gate dielectric layer

[0057] 105 Control Gate Layer

[0058] 106 Hard Mask

[0059] 107 Isolation Sidewall

[0060] 108 Tunnel Penetration Sidewall

[0061] 109-line grid

[0062] 110 Erase Gate

[0063] 111 Insulation layer

[0064] 112 source region

[0065] 113 Leakage Zone

[0066] 114 Groove Structure

[0067] 115 Gate oxide layer

[0068] 201 Logic Circuit Area

[0069] 202 Shallow trench isolation structure

[0070] 301 Side Wall Structure

[0071] 302 First Dielectric Layer

[0072] 303 First polycrystalline silicon layer

[0073] 304 Second Polycrystalline Silicon Layer

[0074] 305 Organic dielectric layer Detailed Implementation

[0075] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0076] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0077] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0078] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0079] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0080] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0081] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0082] Example 1

[0083] As shown in Figure 1, this embodiment provides an embedded flash memory structure, which includes: a semiconductor substrate 101; a gate stack layer formed on the semiconductor substrate 101, the gate stack layer including a tunnel oxide layer 102, a floating gate layer 103, a gate dielectric layer 104 and a control gate layer 105 stacked sequentially, the width of the tunnel oxide layer 102 and the floating gate layer 103 being greater than the width of the gate dielectric layer 104 and the control gate layer 105, so that the tunnel oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105; an isolation sidewall 107 and a tunneling sidewall 108, respectively covering the first sidewall and the second sidewall on both sides of the tunnel oxide layer 102, the floating gate layer 103, the gate dielectric layer 104 and the control gate layer 105; A word line gate 109 is disposed on the side of the isolation sidewall 107. The word line gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed inward by a distance. A drain region 113 is disposed in the semiconductor substrate 101 and located on the side of the word line gate 109. The area between the drain region 113 and the tunneling oxide layer 102 and the floating gate layer 103 is a channel region. The width of the channel region is reduced by controlling the inward recess distance of the word line gate 109. A source region 112 is disposed in the semiconductor substrate 101 on the side of the tunneling sidewall 108. An insulating layer 111 covers the source region 112. An erase gate 110 is disposed on the side of the tunneling sidewall 108 and located on the insulating layer 111 to isolate it from the source region 112.

[0084] In some embodiments, the semiconductor substrate 101 may be, for example, a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, a III-V compound substrate, etc., and is not limited to the examples listed above. The semiconductor substrate 101 includes a core device region and a logic circuit region 201. The device region and the logic circuit region 201 are isolated by a shallow trench isolation structure 202.

[0085] As shown in FIG1, a gate stack layer is formed on the semiconductor substrate 101. The gate stack layer includes a tunnel oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, and a control gate layer 105 stacked sequentially. The widths of the tunnel oxide layer 102 and the floating gate layer 103 are greater than the widths of the gate dielectric layer 104 and the control gate layer 105, so that the tunnel oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105.

[0086] In some embodiments, the material of the tunneling oxide layer 102 may be silicon dioxide, and its thickness may be 90 angstroms to 110 angstroms. For example, the thickness of the tunneling oxide layer may be 90 angstroms, 100 angstroms, 110 angstroms, etc.

[0087] As shown in Figure 1, the floating gate layer 103 is composed of multiple nano-storage points 1031, which include one, a combination of two, or a combination of three of silicon (Si) nano-storage points, germanium (Ge) nano-storage points, and silicon carbide (SiC) nano-storage points. For example, silicon nano-storage points have high charge retention capability, while germanium nano-storage points can improve programming speed. The nano-storage points have a particle size of 50 Å to 130 Å, such as 100 Å or 110 Å. This particle size range ensures charge retention capability while increasing storage density.

[0088] In traditional monolithic continuous polysilicon floating gate structures, when any point is broken down and a defect is formed, the charge stored in the entire floating gate is rapidly discharged through the breakdown point, resulting in global data loss. As shown in Figure 1, the floating gate layer 103 of this invention includes multiple electrically isolated nano-storage points 1031. During programming, charge can be stored in the multiple electrically isolated nano-storage points 1031. When any nano-storage point 1031 breaks down and forms a defect, because the nano-storage points 1031 are electrically isolated, the remaining undamaged nano-storage points 1031 can still store charge normally, allowing the floating gate layer 103 to maintain normal storage function, thereby improving the overall stability of the memory and increasing its lifespan. Simultaneously, this invention can make the electric field distribution more uniform, reduce electric field distortion in areas such as edges, and improve the withstand voltage capability of the floating gate layer 103.

[0089] In one embodiment, two adjacent nano-storage points 1031 are electrically isolated by oxides (such as silicon oxide or germanium oxide).

[0090] The thickness of the gate dielectric layer 104 is 130 angstroms to 170 angstroms, for example, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, etc.; the gate dielectric layer 104 includes a first silicon oxide layer and a silicon nitride layer located on the first silicon oxide layer. The thickness of the first silicon oxide layer can be, for example, 40 angstroms, 50 angstroms, 60 angstroms, etc., the thickness of the silicon nitride layer can be, for example, 40 angstroms, 50 angstroms, 60 angstroms, etc., and the thickness of the second silicon oxide layer can be, for example, 40 angstroms, 50 angstroms, 60 angstroms, etc. The thickness of the control gate layer 105 is 500 angstroms to 700 angstroms, and the material of the control gate layer 105 can be polysilicon, with a thickness of, for example, 500 angstroms, 600 angstroms, 700 angstroms, etc.; the gate stack layer also includes a hard mask 106 disposed on the control gate layer 105, with a thickness of 500 angstroms to 1100 angstroms, for example, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 1000 angstroms, 1100 angstroms, etc.

[0091] In some embodiments, the tunneling oxide layer 102 and the floating gate layer 103 protrude from either side of the gate dielectric layer 104 and the control gate layer 105 with a width of 5 nanometers to 15 nanometers. For example, the width of the tunneling oxide layer 102 and the floating gate layer 103 protruding from either side of the gate dielectric layer 104 and the control gate layer 105 can be 5 nanometers, 8 nanometers, 10 nanometers, 12 nanometers, 15 nanometers, etc.

[0092] In some embodiments, the width of the tunneling oxide layer 102 and the floating gate layer 103 is 100 nm to 130 nm, for example, 110 nm, 120 nm, 130 nm, etc., and the width of the gate dielectric layer 104 and the control gate layer 105 is 80 nm to 110 nm, for example, 90 nm, 100 nm, 110 nm, etc.

[0093] As shown in Figure 1, the isolation sidewall 107 and the tunneling sidewall 108 respectively cover the first and second sidewalls on both sides of the tunneling oxide layer 102, the floating gate layer 103, the gate dielectric layer 104, and the control gate layer 105. The isolation sidewall 107 and the tunneling sidewall 108 have corners at the top corners of the floating gate layer 103. In some embodiments, the thickness of the isolation sidewall 107 is 160 angstroms to 220 angstroms, for example, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms, etc.; the thickness of the tunneling sidewall 108 is 90 angstroms to 110 angstroms, for example, 90 angstroms, 100 angstroms, 110 angstroms, etc. The material of the isolation sidewall 107 can be silicon dioxide, which is used to isolate the word line gate 109 and the gate stack structure. The material of the tunneling sidewall 108 can also be silicon dioxide, which is used to isolate the erase gate 110 and the gate stack structure. At the same time, by applying an appropriate voltage to the erase gate 110, electrons in the floating gate layer 103 can be extracted through the tunneling effect of the tunneling sidewall 108 to remove the charge in the floating gate layer 103. The isolation sidewall 107 has a corner at the top corner of the floating gate layer 103, which can effectively ensure that the subsequent word line gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed into the word line gate 109 by a certain distance. The tunneling sidewall 108 has a corner at the top corner of the floating gate layer 103, which can effectively ensure the uniformity of the thickness of the tunneling oxide layer 102 between the erase gate 110 and the floating gate layer 103, and ensure the stability of the erase gate 110 when extracting electrons from the floating gate layer 103 under the same voltage.

[0094] As shown in Figure 1, a word line gate 109 is disposed on the side of the isolation sidewall 107. The word line gate 109 protrudes along the tunnel oxide layer 102 and the floating gate layer 103 and is recessed into the interior of the word line gate 109 by a certain distance. Specifically, one side of the word line gate 109 is recessed into the interior of the word line gate 109 by a certain distance, and the other side has a sidewall that is perpendicular or nearly perpendicular to the semiconductor substrate 101. This makes the width of the lower part of the word line gate 109 smaller than the width of the upper part of the word line gate 109. Generally speaking, the manufacturing process defines the shape and size of the upper part of the word line gate 109. Therefore, when the upper size of the word line gate 109 is the same as that of the conventional process, the lower width of the word line gate 109 is smaller than that of the lower width of the word line gate 109 in the conventional process, which can effectively shorten the width of the channel region. In some embodiments, the word line gate 109 may include a gate oxide layer located on the substrate surface and a polysilicon layer located on the gate oxide layer. The word line gate 109 is used to turn on the channel beneath it during programming, so that electrons can pass through the tunnel oxide layer and be stored in the floating gate layer 103 through the hot electron injection effect.

[0095] As shown in Figure 1, a drain region 113 is disposed in the semiconductor substrate 101 and located on the side of the word line gate 109. The region between the drain region 113 and the tunneling oxide layer 102 and the floating gate layer 103 is a channel region. By controlling the inward concavity of the word line gate 109, the width of the channel region is reduced. The drain region 113 can be connected to the bit lines of the embedded flash memory. In some embodiments, the drain region 113 can be N-type doped, and the shortened width of the channel region is equal to the inward concavity of the word line gate 109. Therefore, by controlling the protrusion of the tunneling oxide layer 102 and the floating gate layer 103 from the gate dielectric layer 104 and controlling the width of both sides of the gate layer 105, the width of the channel region can be effectively controlled.

[0096] In this invention, the width of the embedded flash memory, including the tunnel oxide layer 102 and the floating gate layer 103, is set to be greater than the width of the gate dielectric layer 104 and the control gate layer 105. This allows the tunnel oxide layer 102 and the floating gate layer 103 to protrude from both sides of the gate dielectric layer 104 and the control gate layer 105. The word line gate 109 protrudes along the tunnel oxide layer 102 and the floating gate layer 103 and is recessed inward by a certain distance. By controlling the inward recess distance of the word line gate 109, the width of the channel region can be effectively reduced. This significantly shortens the path for electron injection into the floating gate layer 103 during programming, thereby greatly improving the programming speed of the embedded flash memory.

[0097] As shown in Figure 1, a source region 112 is disposed in the semiconductor substrate 101 on the side of the tunnel sidewall 108, and an insulating layer 111 covers the source region 112. In some embodiments, the source region 112 can be N-type doped. The source region 112 can be connected to the source line of the embedded flash memory. The insulating layer 111 on the source region has an elliptical cross-section, with both ends of the ellipse connected to the tunnel sidewall. The thickness of the insulating layer in the middle is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms. By providing a relatively thick insulating layer 111 on the source region, the present invention can effectively increase the erase voltage that can be applied to the erase gate 110 above it without damaging the device, thereby ensuring that the erase operation has extremely high erase efficiency and erase stability. For example, in this embodiment, during the erase operation, the erase gate 110 can be applied with an erase voltage ranging from 12V to 13V. Since the erase gate 110 can be applied with a sufficiently high voltage, there is no need to apply a negative voltage to the control gate, which greatly reduces the design difficulty of the application circuit. In addition, the insulating layer 111 is set to an ellipse shape. Typically, the electric field is concentrated in the middle of the erase gate 110. Therefore, the larger thickness in the middle of the ellipse can prevent the insulating layer 111 from being damaged due to the concentrated electric field in the middle. On the other hand, the relatively smaller thickness at both ends of the ellipse can ensure the stability of the distance between the two sides of the erase gate 110 and the floating gate layer 103, thereby ensuring the stability of the erase operation.

[0098] As shown in Figure 1, an erase gate 110 is disposed on the side of the tunneling sidewall 108 and located on the insulating layer 111 to isolate it from the source region 112. In some embodiments, the erase gate 110 may be made of polysilicon. By applying an appropriate voltage to the erase gate 110, electrons in the floating gate layer 103 can be extracted through the tunneling effect of the tunneling sidewall 108 to erase the floating gate layer 103.

[0099] As shown in Figures 7 and 8, the embedded flash memory structure of this embodiment includes multiple signal lines, including a bit line (BL) connected to the drain region 113, a word line (WL) connected to the word line gate 109, a control gate line (CG) connected to the control gate layer 105, an erase gate line (EG) connected to the erase gate 110, and a source line (SL) connected to the source region 112.

[0100] This embodiment also provides an erasure method for an embedded flash memory structure, wherein, during the erasure process, the bit line (BL) is applied with a voltage of 0V, the word line (WL) / select gate is applied with a voltage of 0V, the control gate (CG) is applied with a voltage of 0V, the erase gate 110 line (EG) is applied with a voltage of 11-13V, the source line (SL) is applied with a voltage of 0V, and the electronic path for erasure is to extract electrons from the floating gate layer 103 to the erase gate 110.

[0101] This embodiment also provides a programming method for an embedded flash memory structure. During the programming process, the thermal current applied to the bit line (BL) is 0.8–1.1 μA, the voltage applied to the word line (WL) / select gate is 0.9–1.1 V, the voltage applied to the control gate (CG) is 9–12 V, the voltage applied to the erase gate (EG) is 4–6 V, and the voltage applied to the source line (SL) is 4–6 V. The electronic path for programming is to inject electrons from the drain region 113 into the floating gate layer 103 via thermionic injection.

[0102] This embodiment also provides a readout method for an embedded flash memory structure, wherein, during the readout process, the thermal voltage applied to the bit line (BL) is 0.9–1.2V, the voltage applied to the word line (WL) / select gate is 0.8–2.5V, the voltage applied to the control gate (CG) is 0.9–3V, the voltage applied to the erase gate (EG) is 0V, and the voltage applied to the source line (SL) is 0V. The presence of electronic charge in the floating gate layer 103 is determined by the readout current.

[0103] As shown in Figures 9 to 24, the present invention also provides a method for manufacturing an embedded flash memory structure. This method can be used to manufacture the embedded flash memory structure described in the above embodiments. Specific parameters of some embedded flash memory structures can be found in the above embodiments. The manufacturing method of this embodiment includes the following steps:

[0104] As shown in Figure 9, step 1) is performed first, providing a semiconductor substrate 101.

[0105] In some embodiments, the semiconductor substrate 101 may be, for example, a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, a III-V compound substrate, etc., and is not limited to the examples listed above.

[0106] As shown in Figures 9 to 15, step 2) is then performed, in which a gate stack layer is formed on the semiconductor substrate 101. The gate stack layer includes a tunnel oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, and a control gate layer 105 stacked sequentially. The widths of the tunnel oxide layer 102 and the floating gate layer 103 are greater than the widths of the gate dielectric layer 104 and the control gate layer 105, so that the tunnel oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105.

[0107] In some embodiments, the thickness of the tunneling oxide layer 102 is 90 angstroms to 110 angstroms, the thickness of the floating gate layer 103 is 300 angstroms to 450 angstroms, the gate dielectric layer 104 includes a first silicon oxide layer and a silicon nitride layer located on the first silicon oxide layer, the thickness of the gate dielectric layer 104 is 130 angstroms to 170 angstroms, the thickness of the control gate layer 105 is 500 angstroms to 700 angstroms, the thickness of the hard mask 106 is 500 angstroms to 1100 angstroms, the thickness of the isolation sidewall 107 is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall 108 is 90 angstroms to 110 angstroms.

[0108] In some embodiments, the tunneling oxide layer 102 and the floating gate layer 103 protrude from either side of the gate dielectric layer 104 and the control gate layer 105 with a width of 5 nm to 15 nm; or the width of the tunneling oxide layer 102 and the floating gate layer 103 is 100 nm to 130 nm, and the width of the gate dielectric layer 104 and the control gate layer 105 is 80 nm to 110 nm.

[0109] In one embodiment, forming a gate stack layer on the semiconductor substrate 101 includes the steps of:

[0110] As shown in Figures 9 to 12, a tunnel oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105, and a hard mask 106 are sequentially formed on the semiconductor substrate 101; the hard mask 106, the control gate layer 105, and the gate dielectric layer 104 are patterned by photolithography and etching processes.

[0111] As shown in Figure 9, forming the floating gate layer 103 includes: forming an amorphous material layer on the first dielectric layer 102, and annealing the amorphous material layer to form a plurality of electrically isolated nano-storage points 1031 to form the floating gate layer 103.

[0112] In one embodiment, the amorphous material layer includes at least one of silicon, germanium, and silicon carbide, and the nano-storage point 1031 includes at least one of silicon nano-storage point 1031, germanium nano-storage point 1031, and silicon carbide nano-storage point 1031, with a particle size of 50 angstroms to 130 angstroms.

[0113] In one embodiment, the annealing process is carried out under a nitrogen atmosphere, the annealing temperature is 700℃~850℃ (e.g., 700℃, 750℃, 800℃, 850℃), the annealing pressure is 70 Torr~90 Torr (e.g., 70 Torr, 75 Torr, 80 Torr, 85 Torr, 90 Torr), the annealing time is 10s~20s (e.g., 10s, 15s, 20s), and the nitrogen flow rate is 5slm~15slm (e.g., 5slm, 10slm, 15slm).

[0114] Specifically, an amorphous silicon layer can be deposited using chemical vapor deposition processes such as PECVD, followed by rapid thermal annealing (RTA) or laser annealing in a nitrogen (N2) atmosphere at a temperature of, for example, 800°C, a pressure of, for example, 80 Torr, a time of, for example, 15 s, and an N2 flow rate of, for example, 10 slm. Annealing causes the amorphous silicon layer to aggregate into isolated nano-storage sites 1031.

[0115] As shown in Figure 13, a sidewall structure 301 is formed on the sidewalls of the patterned hard mask 106, the control gate layer 105 and the gate dielectric layer 104.

[0116] As shown in Figure 14, the floating gate layer 103 and the tunneling oxide layer 102 are etched to pattern them using the patterned hard mask 106, the control gate layer 105, the gate dielectric layer 104, and the sidewall structure 301 as masks. The tunneling oxide layer 102 and the floating gate layer 103 protrude beyond the gate dielectric layer 104 and the control gate layer 105 by controlling the width of the sidewall structure 301.

[0117] As shown in Figures 15 to 17, step 3) is then performed to form an isolation sidewall 107 and a tunneling sidewall 108. The isolation sidewall 107 and the tunneling sidewall 108 respectively cover the first sidewall and the second sidewall on both sides of the tunneling oxide layer 102, the floating grid layer 103, the grid dielectric layer 104, and the control grid layer 105. The isolation sidewall 107 and the tunneling sidewall 108 have corners at the top corners of the floating grid layer 103.

[0118] In one embodiment, forming the isolation sidewall 107 and the tunnel sidewall 108 includes the steps of:

[0119] As shown in Figure 15, a first dielectric layer 302 is formed on the sidewall of the sidewall structure 301, the tunnel oxide layer 102 and the floating grid layer 103.

[0120] As shown in Figure 16, the tunneling oxide layer 102, the floating gate layer 103, the gate dielectric layer 104, and the sidewall structure 301 and the first dielectric layer 302 on the second sidewall of the control gate layer 105 are removed.

[0121] As shown in Figure 17, a tunneling sidewall 108 is formed on the second sidewall of the tunneling oxide layer 102, the floating gate layer 103, the gate dielectric layer 104, and the control gate layer 105. At this time, the sidewall structure 301, the first dielectric layer 302, and the tunneling oxide layer on the first sidewall of the tunneling oxide layer 102, the floating gate layer 103, the gate dielectric layer 104, and the control gate layer 105 together constitute the isolation sidewall 107.

[0122] As shown in Figure 18, step 4) is then performed, forming a source region 112 in the semiconductor substrate 101. The source region 112 is disposed in the semiconductor substrate 101 on the side of the tunneling sidewall 108, and an insulating layer 111 is covered on the source region 112. The insulating layer 111 is covered on the source region 112 by a thermal oxidation process. The cross-section of the insulating layer 111 on the source region 112 is elliptical, and the two ends of the ellipse are connected to the tunneling sidewall 108. The thickness of the insulating layer 111 in the middle is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms.

[0123] As shown in Figures 18-24, step 5) is then performed, forming a word line grid 109 on the side of the isolation sidewall 107. The word line grid 109 protrudes along the tunneling oxide layer 102 and the floating grid layer 103 and is recessed inward by a distance. An erase grid 110 is formed, which is disposed on the side of the tunneling sidewall 108 and located on the insulating layer 111 to isolate it from the source region 112.

[0124] In one embodiment, forming the word line grid 109 and the erase grid 110 includes the steps of:

[0125] As shown in Figures 18-24, a gate oxide layer 115 is formed on the surface of a semiconductor substrate 101 by a thermal oxidation process; a first polysilicon layer 303 is deposited on the semiconductor substrate and planarized to remove excess first polysilicon layer 303 from the surface. The polysilicon layer deposited on one side of the tunnel sidewall 108 serves as an erase gate 110. By controlling the deposition parameters of the first polysilicon layer 303, a groove structure 114 is formed on the top of the erase gate 110. The polysilicon layer deposited on one side of the isolation sidewall 107 is word line polysilicon. Of course, the groove structure 114 can be formed naturally by deposition, or the erase gate 110 can be further etched to form a groove structure 114 of the desired shape and depth.

[0126] In some instances, the depth of the groove structure 114 is 10% to 50% of the height of the erase gate 110. The groove structure 114 is also filled with a metal layer that forms an ohmic contact with the polysilicon in the groove structure 114. The groove structure 114 in the erase gate 110 includes one of a rectangular groove, a V-groove, and a U-groove.

[0127] Specifically, as shown in Figures 18 to 24, forming the word line grid and the erase grid includes the following steps:

[0128] As shown in Figure 18, a gate oxide layer is formed on the surface of the semiconductor substrate 101 by a thermal oxidation process.

[0129] As shown in Figure 19, a first polysilicon layer 303 is deposited on a semiconductor substrate. The first polysilicon layer 303 deposited on the side of the tunnel sidewall 108 serves as an erase gate 110, and the first polysilicon layer 303 deposited on the side of the isolation sidewall 107 serves as word line polysilicon. A groove structure 114 is formed on the top of the erase gate 110 and the top of the word line polysilicon.

[0130] As shown in Figure 20, an organic dielectric layer 305 is spin-coated onto the erase gate 110 and the word line polysilicon, and the organic dielectric layer 305 fills the groove structure 114.

[0131] As shown in Figure 21, the organic dielectric layer 305 is etched by plasma without a mask until the first polysilicon layer 303 is exposed, and the organic dielectric layer 305 is retained in the groove structure 114.

[0132] As shown in Figure 22, the first polysilicon layer is selectively etched to remove excess first polysilicon layer on the surface; wherein, the selective etching has a high selectivity for the first polysilicon layer 303 and a low etching rate for the organic dielectric layer 305, so that the organic dielectric layer 305 is always maintained in the groove structure 114, thereby protecting the groove structure 114 from being etched and damaged.

[0133] As shown in Figure 23, the organic medium layer 305 in the groove structure 114 is removed by wet etching. The solution used for wet etching can be, for example, an acidic solution.

[0134] This process method can remove excess first polysilicon layer on the surface by etching. During the etching process, an organic dielectric layer is filled in the groove structure, which can avoid damage caused by etching of the groove structure. Compared with the traditional planarization process, it can further avoid mechanical damage to the device, and the etching process has higher selectivity, which can effectively improve process stability.

[0135] As shown in Figure 24, the word line silicon is etched to divide the word line polysilicon into two word line gates 109.

[0136] As shown in Figure 24, the final step is step 6), in which a drain region 113 is formed in the semiconductor substrate 101 by ion implantation. The drain region 113 is disposed in the semiconductor substrate 101 and located on the side of the word line gate 109. The area between the drain region 113 and the tunnel oxide layer 102 and the floating gate layer 103 is a channel region. The width of the channel region is reduced by controlling the inward concavity of the word line gate 109.

[0137] Example 2

[0138] As shown in Figure 2, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 1. The main difference from Embodiment 1 is that the erase gate 110 is made of polysilicon, and a groove structure 114 is formed on the top of the erase gate 110. The groove structure 114 is also filled with a metal layer. The metal layer forms an ohmic contact with the polysilicon in the groove structure 114. The metal layer can be, for example, a stack or alloy of one or more of titanium, nickel, tantalum, aluminum, tungsten, copper, and gold, and is not limited to the examples listed here.

[0139] The depth of the groove structure 114 is 10% to 50% of the height of the erase gate 110. For example, the depth of the groove structure 114 is 20%, 30%, 40%, 50%, 60%, etc., of the height of the erase gate 110. The metal layer can be deposited on the inner wall of the groove structure 114 or filling the groove structure 114, and then formed into a metal silicide with the polysilicon of the erase gate 110 through processes such as annealing. In some embodiments, the groove structure 114 includes one of a rectangular groove, a V-groove, and a U-groove. By forming an ohmic contact between the groove structure 114 and the metal layer, the contact area between the metal layer and the erase gate 110 can be greatly increased, improving its driving effect and thus enhancing the speed and stability of the erasure operation of the erase gate 110.

[0140] As shown in Figures 25-27, in another embodiment, forming the word line grid 109 and the erase grid 110 may also include the following steps:

[0141] As shown in Figure 25, a gate oxide layer is formed on the surface of a semiconductor substrate 101 by a thermal oxidation process; a first polysilicon layer 303 is deposited on the semiconductor substrate, wherein the first polysilicon layer 303 deposited on the side of the tunnel sidewall 108 serves as an erase gate 110, and the first polysilicon layer 303 deposited on the side of the isolation sidewall 107 serves as word line polysilicon. A groove structure 114 is formed on the top of the erase gate 110 and the top of the word line polysilicon.

[0142] As shown in FIG26, a second polysilicon layer 304 is deposited on the erase gate 110 and the word line polysilicon, and the second polysilicon layer 304 fills the groove structure 114.

[0143] As shown in Figure 27, the excess second polysilicon layer 304 and first polysilicon layer 303 on the surface are removed by planarization; the word line polysilicon is etched to divide the word line polysilicon into two word line gates 109.

[0144] In this embodiment, by depositing a second polysilicon layer 304 to fill the groove structure 114 in the first polysilicon layer 303, the stability of the subsequent planarization process can be greatly improved, and the device yield can be increased.

[0145] Example 3

[0146] As shown in Figure 3, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 1. The main difference from Embodiment 1 is that the width of the tunneling oxide layer 102 and the floating gate layer 103 is greater than the width of the gate dielectric layer 104 and the control gate layer 105. The tunneling oxide layer 102 and the floating gate layer 103 protrude from the gate dielectric layer 104 and the control gate layer 105 on one side toward the erase gate 110, and are flush with the tunneling oxide layer 102 and the floating gate layer 103 on the other side. The tunneling sidewall 108 has a corner at the top corner of the floating gate layer 103, which can effectively ensure the uniformity of the thickness of the tunneling oxide layer 102 between the erase gate 110 and the floating gate layer 103, and ensure the stability of the erase gate 110 when extracting electrons from the floating gate layer 103 under the same voltage. The tunneling oxide layer 102 and the floating gate layer 103 protrude from the gate dielectric layer 104 and the control gate layer 105 on the side of the erase gate 110, with a width of 5 nm to 15 nm; or / and the width of the tunneling oxide layer 102 and the floating gate layer 103 is 85 nm to 125 nm, and the width of the gate dielectric layer 104 and the control gate layer 105 is 80 nm to 110 nm.

[0147] As shown in Figures 28-30, this embodiment provides a method for fabricating an embedded flash memory structure. The basic steps are the same as in Embodiment 1, except that the main difference from Embodiment 1 is that forming a gate stack layer on the semiconductor substrate includes the following steps:

[0148] A tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105, and a hard mask 106 are sequentially formed on the semiconductor substrate.

[0149] The hard mask 106, the control gate layer 105, and the gate dielectric layer 104 are patterned using photolithography and etching processes.

[0150] As shown in Figure 28, a sidewall structure is formed on one side of the patterned hard mask 106, control gate layer 105 and gate dielectric layer 104 facing the erase gate 110, while no sidewall structure is formed on the other side.

[0151] As shown in Figure 29, using the patterned hard mask 106, control gate layer 105, gate dielectric layer 104, and sidewall structure as masks, the floating gate layer 103 and tunneling oxide layer 102 are etched to pattern them. The width of the tunneling oxide layer 102 and floating gate layer 103 is greater than the width of the gate dielectric layer 104 and control gate layer 105, and the tunneling oxide layer 102 and floating gate layer 103 protrude from the gate dielectric layer 104 and control gate layer 105 towards the erase gate 110. The tunneling sidewall 108 has a corner at the top corner of the floating gate layer 103, and the other side of the tunneling oxide layer 102 and floating gate layer 103 is flush with the tunneling oxide layer 102 and floating gate layer 103. The width of the tunneling oxide layer 102 and floating gate layer 103 protruding from the gate dielectric layer 104 and control gate layer 105 is controlled by controlling the width of the sidewall structure.

[0152] The embedded flash memory structure formed after other process steps is shown in Figure 30.

[0153] Example 4

[0154] As shown in Figure 4, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 2. The main difference from Embodiment 2 is that the width of the tunneling oxide layer 102 and the floating gate layer 103 is greater than the width of the gate dielectric layer 104 and the control gate layer 105. The tunneling oxide layer 102 and the floating gate layer 103 protrude from the gate dielectric layer 104 and the control gate layer 105 on one side toward the erase gate 110, and are flush with the tunneling oxide layer 102 and the floating gate layer 103 on the other side. The tunneling sidewall 108 has a corner at the top corner of the floating gate layer 103, which can effectively ensure the uniformity of the thickness of the tunneling oxide layer 102 between the erase gate 110 and the floating gate layer 103, and ensure the stability of the erase gate 110 when extracting electrons from the floating gate layer 103 under the same voltage. The tunneling oxide layer 102 and the floating gate layer 103 protrude from the gate dielectric layer 104 and the control gate layer 105 on the side of the erase gate 110, with a width of 5 nm to 15 nm; or / and the width of the tunneling oxide layer 102 and the floating gate layer 103 is 85 nm to 125 nm, and the width of the gate dielectric layer 104 and the control gate layer 105 is 80 nm to 110 nm.

[0155] As shown in Figures 28, 29, and 31, this embodiment provides a method for fabricating an embedded flash memory structure. The basic steps are the same as in Embodiment 2, except that the main difference lies in the following: forming a gate stack layer on the semiconductor substrate includes the following steps:

[0156] A tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105, and a hard mask 106 are sequentially formed on the semiconductor substrate.

[0157] The hard mask 106, the control gate layer 105 and the gate dielectric layer 104 are patterned using photolithography and etching processes.

[0158] As shown in Figure 28, a sidewall structure is formed on one side of the patterned hard mask 106, control gate layer 105 and gate dielectric layer 104 facing the erase gate 110, while no sidewall structure is formed on the other side.

[0159] As shown in Figure 29, using the patterned hard mask 106, control gate layer 105, gate dielectric layer 104, and sidewall structure as masks, the floating gate layer 103 and tunneling oxide layer 102 are etched to pattern them. The width of the tunneling oxide layer 102 and floating gate layer 103 is greater than the width of the gate dielectric layer 104 and control gate layer 105, and the tunneling oxide layer 102 and floating gate layer 103 protrude from the gate dielectric layer 104 and control gate layer 105 towards the erase gate 110. The tunneling sidewall 108 has a corner at the top corner of the floating gate layer 103, and the other side of the tunneling oxide layer 102 and floating gate layer 103 is flush with the tunneling oxide layer 102 and floating gate layer 103. The width of the tunneling oxide layer 102 and floating gate layer 103 protruding from the gate dielectric layer 104 and control gate layer 105 is controlled by controlling the width of the sidewall structure.

[0160] The embedded flash memory structure formed after other process steps is shown in Figure 31.

[0161] Example 5

[0162] As shown in Figure 5, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 1. The main difference from Embodiment 1 is that the tunneling oxide layer 102 and the floating gate layer 103 are equal to the width of the gate dielectric layer 104 and the control gate layer 105, and the tunneling oxide layer 102 and the floating gate layer 103 are flush with both sides of the gate dielectric layer 104 and the control gate layer 105. This embedded flash memory structure and manufacturing process are simple, and can effectively improve process stability and process window.

[0163] As shown in Figures 32-34, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 1. The main difference from Embodiment 1 is that forming a gate stack layer on the semiconductor substrate includes the following steps:

[0164] A tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105, and a hard mask 106 are sequentially formed on the semiconductor substrate.

[0165] As shown in Figure 32, the hard mask 106, the control gate layer 105 and the gate dielectric layer 104 are patterned through photolithography and etching processes.

[0166] As shown in Figure 33, using the patterned hard mask 106, control gate layer 105, and gate dielectric layer 104 as masks, the floating gate layer 103 and tunnel oxide layer 102 are etched to pattern them. The tunnel oxide layer 102 and floating gate layer 103 are equal to the width of the gate dielectric layer 104 and control gate layer 105, and the tunnel oxide layer 102 and floating gate layer 103 are flush with the two sides of the gate dielectric layer 104 and control gate layer 105.

[0167] The embedded flash memory structure formed after other process steps is shown in Figure 34.

[0168] Example 6

[0169] As shown in Figure 6, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 2. The main difference from Embodiment 2 is that the tunneling oxide layer 102 and the floating gate layer 103 are equal to the width of the gate dielectric layer 104 and the control gate layer 105, and the tunneling oxide layer 102 and the floating gate layer 103 are flush with both sides of the gate dielectric layer 104 and the control gate layer 105. This embedded flash memory structure and manufacturing process are simple, and can effectively improve process stability and process window.

[0170] As shown in Figures 32, 33, and 35, this embodiment provides an embedded flash memory structure, the basic structure of which can be referred to in Embodiment 2. The main difference from Embodiment 2 is that forming a gate stack layer on the semiconductor substrate includes the following steps:

[0171] A tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105, and a hard mask 106 are sequentially formed on the semiconductor substrate.

[0172] As shown in Figure 32, the hard mask 106, the control gate layer 105 and the gate dielectric layer 104 are patterned through photolithography and etching processes.

[0173] As shown in Figure 33, using the patterned hard mask 106, control gate layer 105, and gate dielectric layer 104 as masks, the floating gate layer 103 and tunnel oxide layer 102 are etched to pattern them. The tunnel oxide layer 102 and floating gate layer 103 are equal to the width of the gate dielectric layer 104 and control gate layer 105, and the tunnel oxide layer 102 and floating gate layer 103 are flush with the two sides of the gate dielectric layer 104 and control gate layer 105.

[0174] The embedded flash memory structure formed after other process steps is shown in Figure 35.

[0175] As described above, the embedded flash memory structure and its manufacturing method of the present invention have the following beneficial effects:

[0176] The floating gate layer 103 of the present invention includes a plurality of electrically isolated nano-storage points 1031. During programming, charge can be stored in the plurality of electrically isolated nano-storage points. When any nano-storage point 1031 breaks down, because the nano-storage points 1031 are electrically isolated from each other, the remaining undamaged nano-storage points 1031 can still store charge normally, so that the floating gate layer 103 can maintain normal storage function, thereby improving the overall stability of the memory and increasing the memory's lifespan. The floating gate layer 103 of the present invention includes a plurality of electrically isolated nano-storage points 1031, which can make the electric field distribution more uniform, reduce electric field distortion in areas such as edges, and improve the withstand voltage capability of the floating gate layer 103.

[0177] In this invention, the width of the embedded flash memory, including the tunnel oxide layer 102 and the floating gate layer 103, is set to be greater than the width of the gate dielectric layer 104 and the control gate layer 105. This allows the tunnel oxide layer 102 and the floating gate layer 103 to protrude from both sides of the gate dielectric layer 104 and the control gate layer 105. The word line gate 109 protrudes along the tunnel oxide layer 102 and the floating gate layer 103 and is recessed inward by a certain distance. By controlling the inward recess distance of the word line gate 109, the width of the channel region can be effectively reduced. This significantly shortens the path for electron injection into the floating gate layer 103 during programming, thereby greatly improving the programming speed of the embedded flash memory. At the erase gate, the protrusion of the floating gate layer 103 reduces the voltage required to pull electrons from the floating gate layer 103 to the erase gate 110. At the same time, the insulating layer under the erase gate becomes thick due to ion implantation and oxidation during the process. This allows for a higher voltage to be applied to the erase gate 110 without causing the insulating layer 111 to break down, thus greatly improving the process variation window. Our embedded flash memory and its fabrication method combine all the above advantages, making this embedded flash memory cell more process compatible, more reliable, and with better performance.

[0178] The eraser gate 110 of the present invention has a groove structure 114 on its top. The groove structure 114 forms an ohmic contact with the metal layer, which can greatly increase the contact area between the metal layer and the eraser gate 110, improve its driving effect, and thus improve the speed and stability of the erasure operation of the eraser gate 110.

[0179] The present invention provides a relatively thick insulating layer 111 on the source region, which effectively increases the amount of erase voltage that can be applied to the erase gate 110 above it without damaging the device, thereby ensuring extremely high erase efficiency and erase stability during the erase operation. For example, in this embodiment, during the erase operation, the erase voltage range that can be applied to the erase gate 110 is 12V to 13V. Since the erase gate 110 can be applied with a sufficiently high voltage, it is not necessary to apply a negative voltage to the control gate, which greatly reduces the design difficulty of the application circuit.

[0180] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0181] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An embedded flash memory structure, characterized in that, The embedded flash memory structure includes: a semiconductor substrate; a gate stack layer formed on the semiconductor substrate, the gate stack layer including a tunnel oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked sequentially, the floating gate layer containing a plurality of electrically isolated nanometer storage points; isolation sidewalls and tunneling sidewalls, respectively covering a first sidewall and a second sidewall on both sides of the tunnel oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer; a word line gate disposed on the side of the isolation sidewall; a drain region disposed in the semiconductor substrate and located on the side of the word line gate; a source region disposed in the semiconductor substrate on the side of the tunneling sidewall, the source region being covered by an insulating layer; an erase gate disposed on the side of the tunneling sidewall and located on the insulating layer to isolate it from the source region; the erase gate is made of polysilicon, a groove structure is formed on the top of the erase gate, the groove structure is further filled with a metal layer, the metal layer forming an ohmic contact with the polysilicon in the groove structure.

2. The embedded flash memory structure according to claim 1, characterized in that: The nano-storage points include at least one of silicon nano-storage points, germanium nano-storage points, and silicon carbide nano-storage points; the particle size of the nano-storage points is 50 angstroms to 130 angstroms.

3. The embedded flash memory structure according to claim 1, characterized in that: The depth of the groove structure is 10% to 50% of the height of the erase grid, and the groove structure includes one of rectangular groove, V-shaped groove and U-shaped groove.

4. The embedded flash memory structure according to claim 1, characterized in that: The width of the tunneling oxide layer and the floating gate layer is greater than the width of the gate dielectric layer and the control gate layer, and the tunneling oxide layer and the floating gate layer protrude from both sides of the gate dielectric layer and the control gate layer. The isolation sidewall and the tunneling sidewall have corners at the top corners of the floating gate layer.

5. The embedded flash memory structure according to claim 4, characterized in that: The word line grid protrudes along the tunnel oxide layer and the floating grid layer and is recessed into the word line grid by a certain distance; the area between the drain area and the tunnel oxide layer and the floating grid layer is the channel area, and the width of the channel area is reduced by controlling the distance of the word line grid recessed into the interior.

6. The embedded flash memory structure according to claim 4, characterized in that: The tunneling oxide layer and the floating gate layer protrude from either side of the gate dielectric layer and the control gate layer with a width of 5 nm to 15 nm; or / and the width of the tunneling oxide layer and the floating gate layer is 100 nm to 130 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.

7. The embedded flash memory structure according to claim 1, characterized in that: The width of the tunneling oxide layer and the floating gate layer is greater than the width of the gate dielectric layer and the control gate layer. The tunneling oxide layer and the floating gate layer protrude from the gate dielectric layer and the control gate layer on one side toward the erasure gate, and are flush with the tunneling oxide layer and the floating gate layer on the other side. The tunneling sidewall has a corner at the top corner of the floating gate layer.

8. The embedded flash memory structure according to claim 7, characterized in that: The tunneling oxide layer and the floating gate layer protrude from the gate dielectric layer toward the erase gate side, and the width of the control gate layer is 5 nm to 15 nm; or / and the width of the tunneling oxide layer and the floating gate layer is 85 nm to 125 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.

9. The embedded flash memory structure according to claim 1, characterized in that: The tunneling oxide layer and the floating gate layer are equal to the width of the gate dielectric layer and the control gate layer, and the tunneling oxide layer and the floating gate layer are flush with both sides of the gate dielectric layer and the control gate layer.

10. The embedded flash memory structure according to claim 1, characterized in that: The thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer includes a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer, the thickness of the gate dielectric layer is 130 angstroms to 170 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, and the gate stack layer further includes a hard mask disposed on the control gate layer, the thickness of the hard mask being 500 angstroms to 1100 angstroms.

11. The embedded flash memory structure according to claim 1, characterized in that: The thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall is 90 angstroms to 110 angstroms.

12. The embedded flash memory structure according to claim 1, characterized in that: The insulating layer on the source region has an elliptical cross-section, with both ends of the ellipse connected to the tunnel sidewall. The thickness of the insulating layer in the middle is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms.

13. A method for fabricating an embedded flash memory structure, characterized in that, The steps include: providing a semiconductor substrate; forming a gate stack layer on the semiconductor substrate, the gate stack layer comprising a tunnel oxide layer, a floating gate layer, a gate dielectric layer, and a control gate layer stacked sequentially, wherein forming the floating gate layer includes forming an amorphous material layer on the tunnel oxide layer, and annealing the amorphous material layer to aggregate into multiple electrically isolated nanometer storage points to form the floating gate layer; forming isolation sidewalls and tunnel sidewalls, the isolation sidewalls and tunnel sidewalls respectively covering a first sidewall and a second sidewall on both sides of the tunnel oxide layer, the floating gate layer, the gate dielectric layer, and the control gate layer; forming a source region in the semiconductor substrate, the source region being disposed in the semiconductor substrate on the side of the tunnel sidewall, and an insulating layer covering the source region; and forming a word line gate on the side of the isolation sidewall. An erasure grid is formed, which is disposed on the side of the tunnel sidewall and located on the insulating layer to isolate it from the source region; A drain region is formed in the semiconductor substrate, the drain region being disposed in the semiconductor substrate and located on the side of the word line gate; forming the word line gate and erase gate includes the steps of: forming a gate oxide layer on the surface of the semiconductor substrate by a thermal oxidation process; depositing a polysilicon layer on the semiconductor substrate and performing planarization to remove excess polysilicon layer from the surface, wherein the polysilicon layer deposited on one side of the tunnel sidewall serves as the erase gate, and by controlling the deposition parameters of the polysilicon layer, a groove structure is formed on the top of the erase gate; the polysilicon layer deposited on one side of the isolation sidewall is word line polysilicon; etching the word line silicon to divide the word line polysilicon into two word line gates; the groove structure is further filled with a metal layer, the metal layer forming an ohmic contact with the polysilicon in the groove structure.

14. The method for fabricating an embedded flash memory structure according to claim 13, characterized in that: The annealing process is carried out under a nitrogen atmosphere, with an annealing temperature of 700℃~850℃, an annealing pressure of 70 Torr~90 Torr, an annealing time of 10s~20s, and a nitrogen flow rate of 5slm~15slm. The amorphous material layer includes at least one of silicon, germanium, and silicon carbide. The nano-storage points include at least one of silicon nano-storage points, germanium nano-storage points, and silicon carbide nano-storage points, and the particle size of the nano-storage points is 50 angstroms~130 angstroms.

15. The method for fabricating an embedded flash memory structure according to claim 13, characterized in that: Forming a gate stack layer on the semiconductor substrate includes the steps of: sequentially forming a tunnel oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer, and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer, and the gate dielectric layer using photolithography and etching processes; and forming sidewall structures on the two sidewalls of the patterned hard mask, the control gate layer, and the gate dielectric layer. Using the patterned hard mask, control gate layer, gate dielectric layer, and sidewall structure as a mask, the floating gate layer and tunneling oxide layer are etched to pattern them. The width of the tunneling oxide layer and floating gate layer is greater than the width of the gate dielectric layer and control gate layer, and the tunneling oxide layer and floating gate layer protrude from both sides of the gate dielectric layer and control gate layer. The isolation sidewall and tunneling sidewall have corners at the top corners of the floating gate layer. The width of the tunneling oxide layer and floating gate layer protruding from the gate dielectric layer and control gate layer is controlled by controlling the width of the sidewall structure.

16. The method for fabricating an embedded flash memory structure according to claim 15, characterized in that: The word line grid protrudes along the tunnel oxide layer and the floating grid layer and is recessed into the inside of the word line grid by a certain distance. The area between the drain area and the tunnel oxide layer and the floating grid layer is the channel area. By controlling the distance of the word line grid recessed into the inside, the width of the channel area can be reduced.

17. The method for fabricating an embedded flash memory structure according to claim 15, characterized in that: The tunneling oxide layer and the floating gate layer protrude from either side of the gate dielectric layer and the control gate layer with a width of 5 nm to 15 nm; or the width of the tunneling oxide layer and the floating gate layer is 100 nm to 130 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.

18. The method for fabricating an embedded flash memory structure according to claim 13, characterized in that: Forming a gate stack layer on the semiconductor substrate includes the steps of: sequentially forming a tunnel oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer, and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer, and the gate dielectric layer using photolithography and etching processes; forming a sidewall structure on one side of the patterned hard mask, the control gate layer, and the gate dielectric layer facing the erase gate, while not forming a sidewall structure on the other side; Using the patterned hard mask, control gate layer, gate dielectric layer, and sidewall structure as a mask, the floating gate layer and tunneling oxide layer are etched to pattern them. The width of the tunneling oxide layer and floating gate layer is greater than the width of the gate dielectric layer and control gate layer, and the tunneling oxide layer and floating gate layer protrude from the gate dielectric layer and control gate layer towards the erase gate side. The tunneling sidewall has a corner at the top corner of the floating gate layer, and the other side of the tunneling oxide layer and floating gate layer is flush with the tunneling oxide layer and floating gate layer. The width of the tunneling oxide layer and floating gate layer protruding from the gate dielectric layer and control gate layer is controlled by controlling the width of the sidewall structure.

19. The method for fabricating an embedded flash memory structure according to claim 15 or 18, characterized in that: Forming a gate stack layer on the semiconductor substrate includes the following steps: sequentially forming a tunnel oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer, and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer, and the gate dielectric layer using photolithography and etching processes; using the patterned hard mask, the control gate layer, and the gate dielectric layer as masks, etching the floating gate layer and the tunnel oxide layer to pattern them, wherein the width of the tunnel oxide layer and the floating gate layer is equal to the width of the gate dielectric layer and the control gate layer, and the tunnel oxide layer and the floating gate layer are flush with both sides of the gate dielectric layer and the control gate layer.

20. The method for fabricating an embedded flash memory structure according to claim 19, characterized in that: Forming the isolation sidewall and the tunneling sidewall includes the step of: forming a first dielectric layer on the sidewall of the sidewall structure, the tunneling oxide layer and the floating grid layer; Remove the tunneling oxide layer, floating gate layer, gate dielectric layer, and the sidewall structure and first dielectric layer on the second sidewall of the control gate layer; form a tunneling sidewall on the tunneling oxide layer, floating gate layer, gate dielectric layer, and the second sidewall of the control gate layer. At this time, the tunneling oxide layer, floating gate layer, gate dielectric layer, and the sidewall structure, first dielectric layer, and tunneling oxide layer on the first sidewall of the control gate layer together constitute the isolation sidewall.

21. The method for fabricating an embedded flash memory structure according to claim 13, characterized in that: The depth of the groove structure is 10% to 50% of the height of the erase grid, and the groove structure in the erase grid includes one of rectangular groove, V-shaped groove and U-shaped groove.

22. The method for fabricating an embedded flash memory structure according to any one of claims 13 to 18, characterized in that: The steps of forming word line gates and erase gates include: forming a gate oxide layer on the surface of a semiconductor substrate by thermal oxidation; depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunnel sidewall serves as the erase gate, and the first polysilicon layer deposited on the other side of the isolation sidewall serves as word line polysilicon, and a groove structure is formed on the top of the erase gate and the top of the word line polysilicon; spin-coating an organic dielectric layer on the erase gate and the word line polysilicon, wherein the organic dielectric layer fills the groove structure; etching the organic dielectric layer by plasma etching until the first polysilicon layer is exposed, wherein the organic dielectric layer is retained in the groove structure; selectively etching the first polysilicon layer to remove excess first polysilicon layer from the surface; removing the organic dielectric layer in the groove structure by wet etching; and etching the word line polysilicon to divide the word line polysilicon into two word line gates.

23. The method for manufacturing an embedded flash memory structure according to any one of claims 13 to 18, characterized in that: The steps of forming a word line gate and an erase gate include: forming a gate oxide layer on the surface of a semiconductor substrate by a thermal oxidation process; depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunnel sidewall serves as the erase gate, and the first polysilicon layer deposited on the other side of the isolation sidewall serves as word line polysilicon, and a groove structure is formed on the top of the erase gate and the top of the word line polysilicon; depositing a second polysilicon layer on the erase gate and the word line polysilicon, wherein the second polysilicon layer fills the groove structure; removing excess second polysilicon layer and first polysilicon layer from the surface by planarization; and etching the word line polysilicon to divide the word line polysilicon into two word line gates.

24. The method for manufacturing an embedded flash memory structure according to claim 15 or 18, characterized in that: The thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer includes a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer, the thickness of the gate dielectric layer is 130 angstroms to 170 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, the thickness of the hard mask is 500 angstroms to 1100 angstroms, the thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall is 90 angstroms to 110 angstroms.

25. The method for fabricating an embedded flash memory structure according to claim 13, characterized in that: An insulating layer is applied to the source region by a thermal oxidation process. The cross-section of the insulating layer on the source region is elliptical, and the two ends of the ellipse are connected to the tunnel sidewall. The thickness of the insulating layer in the middle is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms.

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