Method for writing mask data

Abstract

The invention provides an interface system which comprises a main controller, an interface module and a function module, the main controller is connected with the interface module, and the interface module is connected with the function module. Based on the interface system, the invention provides a method for writing mask data, the main controller sends a command packet to the interface module, the command packet comprises one or more commands, at least one command is a mask writing command, the mask writing command comprises an address field, a data field and a mask field, and after the interface module receives the command packet, the mask field is a mask field. The command packet is sent to the function module, after the function module receives the command packet, a command contained in the command packet is executed, and the step of executing the mask writing command comprises the substeps that the bit of the mask writing command data field corresponding to the bit with the mask field being 1 in the mask writing command is written into the storage space pointed by the mask writing command address field.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method for writing mask data. Background Art

[0002] The I2C (Inter-Integrated Circuit) bus is a simple, bidirectional serial bus developed by Philips. The I2C master device connects one or more I2C slave devices through the I2C bus. The I2C bus contains the I2C clock line (usually named SCL) and the I2C data line (usually named SDA). The I2C master device drives the I2C clock line, initiates an I2C write or read operation to the I2C slave device, and determines whether the data transmission is successful through the response bit returned by the I2C slave device.

[0003] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus. SPI usually has four signal lines, including SPI_CSN signal line, SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line. The SPI master device connects to the SPI slave device through these four signal lines. The SPI master device drives the SPI_CSN signal line, SPI_CK signal line, and SPI_MOSI signal line. The SPI slave device receives the SPI_CSN signal line, SPI_CK signal line, and SPI_MOSI signal line. The SPI slave device drives the SPI_MISO signal line, and the SPI master device receives the SPI_MISO signal line. The SPI_CSN signal line is a selection signal. In the SPI protocol, the SPI slave device can only transmit data when the SPI_CSN signal line is low. An SPI master device can be connected to one or more SPI slave devices: when an SPI master device is connected to multiple SPI slave devices, at any time, the SPI_CSN signal line connected to only one SPI slave device is low; when an SPI master device is only connected to one SPI slave device, there may be no SPI_CSN signal line between the SPI master device and the SPI slave device. At this time, the SPI master device and the SPI slave device can be connected only through the SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line.

[0004] In the present invention, the I2C master controller is the I2C master device, the I2C interface module is the I2C slave device, the SPI master controller is the SPI master device, and the SPI interface module is the SPI slave device.

[0005] In the present invention, the main controller can be an I2C main controller or an SPI main controller, or a main controller that complies with other interface protocols such as serial port UART protocol, CAN protocol, LIN protocol, etc.; the interface module can be an I2C interface module or an SPI interface module, or an interface module that complies with other interface protocols such as serial port UART protocol, CAN protocol, LIN protocol, etc.

[0006] The main controller sends commands or data to the functional module through the interface module. In the present invention, the module that ultimately receives the command or data is called the functional module. The interface module and the functional module can be in the same chip, the same circuit board, or the same device, or can be located in a different device from the interface module. The interface module and the functional module can communicate through an existing or custom communication protocol.

[0007] In some applications, the main controller needs to write data to some bits in the storage space pointed to by the target address in the functional module. For example, the main controller configures some bits in a register in the functional module. When configuring, some bits in the register need to be overwritten by new values, while the remaining bits of the register should keep the original values ​​unchanged. When the main controller can directly configure the functional module, the main controller often uses a write mask method to configure some bits in the storage space in the functional module.

[0008] If the main controller cannot directly configure the functional module, but needs to configure the functional module through an interface module such as I2C or SPI, in the prior art, the following configuration method is generally adopted: the main controller first initiates a write operation to the interface module, sends a read command to the interface module, the interface module forwards the read command to the functional module, the functional module executes the read command, reads the data in the storage space pointed to by the target address (the read data is referred to as read data in the present invention) and sends it to the interface module, and the interface module receives the read data; then the main controller initiates a read operation to the interface module, the main controller reads the read data from the interface module, and replaces the bits in the read data corresponding to the bits with a value of 1 in the mask with the configuration data, and the remaining bits of the read data remain unchanged, and the replaced read data is used as the data to be written; then the main controller initiates a write operation to the interface module again, sends a write command containing the data to be written to the interface module, the interface module forwards the write command to the functional module, the functional module executes the write command, and writes the data to be written into the storage space pointed to by the target address. This method is cumbersome and time-consuming.

[0009] Currently, there is a lack of a method for the main controller to quickly configure some bits in the storage space pointed to by the target address in the functional module through an interface module such as I2C or SPI, that is, there is a lack of a method for the main controller to quickly write mask data to the target device through an I2C interface or SPI interface. Summary of the invention

[0010] The technical problem to be solved by the present invention is how the main controller can quickly configure some bits in the storage space pointed to by the target address in the functional module through interface modules such as I2C or SPI, that is, how the main controller can quickly write mask data to the target device through the I2C interface or SPI interface.

[0011] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0012] As a method for writing mask data of the present invention, based on an interface system, the interface system includes a main controller, an interface module, and a functional module. The main controller is connected to the interface module, and the interface module is connected to the functional module. The main controller sends a command packet to the interface module, and the command packet includes one or more commands, at least one command is a write mask command, and the write mask command includes an address field, a data field, and a mask field. After receiving the command packet, the interface module sends the command packet to the functional module. After receiving the command packet, the functional module executes the command contained in the command packet. Executing the write mask command includes: writing the bits of the write mask command data field corresponding to the bits of the mask field 1 in the write mask command into the storage space pointed to by the write mask command address field.

[0013] Preferably, after the functional module executes the command included in the command packet, the function module returns a status packet to the interface module, including: when the result of the functional module executing each command included in the command packet is successful, the function module returns a status packet with success status information; when the result of the functional module executing at least one command included in the command packet is failure, the function module returns a status packet with failure status information; after the interface module receives the status packet from the functional module, it returns the status information of the status packet to the main controller.

[0014] Preferably, the command packet contains one or more commands, at least one command is a write command, and the write command contains an address field and a data field. After receiving the command packet, the functional module executes the command contained in the command packet. Executing the write command includes: writing the data field in the write command into the storage space pointed to by the address field of the write command.

[0015] Furthermore, the main controller is an I2C main controller, the interface module is an I2C interface module, and the I2C main controller is connected to the I2C interface module via an I2C clock line and an I2C data line.

[0016] Furthermore, the I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module. After receiving the command packet, the I2C interface module pulls down the I2C clock line level and sends the command packet to the functional module.

[0017] Further, when the I2C interface module receives a status packet from the functional module and the status information of the status packet is success, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller; when the I2C interface module receives a status packet from the functional module and the status information of the status packet is failure, the I2C interface module stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller.

[0018] Further, when the I2C interface module receives a status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK or I2C NAK to the I2C master controller. If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns status information of the status packet to the I2C master controller.

[0019] Further, after the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status packet to the I2C master controller after receiving the status packet from the functional module.

[0020] Further, after the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is success, then the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller; after the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is failure, then the I2C interface module returns an I2C NAK to the I2C master controller.

[0021] Furthermore, the I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module, and then the I2C master controller initiates a subsequent I2C read operation to read status information. After receiving the address byte of the subsequent I2C read operation, the I2C interface module pulls down the I2C clock line level and sends the received command packet to the functional module. After the functional module executes the command contained in the command packet, it returns the status packet to the interface module. When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns the status information of the status packet to the I2C master controller.

[0022] Furthermore, the main controller is an SPI main controller, the interface module is an SPI interface module, and the SPI main controller is connected to the SPI interface module via an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line.

[0023] Further, the SPI master controller generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module through the SPI_MOSI signal line, the SPI interface module reads the command packet through the SPI_MOSI signal line, the command packet starts with a first identification field, after the SPI interface module receives the status packet from the functional module, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sends a feedback packet to the SPI master controller through the SPI_MISO signal line, the SPI master controller reads the feedback packet through the SPI_MISO signal line, the feedback packet starts with a second identification field, and the feedback packet includes the status information included in the status packet.

[0024] Further, when the SPI master controller generates a clock edge on SPI_CK, if the SPI interface module has not received status packets from all functional modules, the SPI interface module sends data that cannot be identified as the feedback packet to the SPI master controller via the SPI_MISO signal line.

[0025] Furthermore, after the SPI interface module sends the feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets sent by the SPI master controller through the SPI_MOSI signal line.

[0026] Further, the feedback packet is divided into a success feedback packet and a failure feedback packet. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is success, the SPI interface module sends a success feedback packet through the SPI_MISO signal line. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is failure, the SPI interface module sends a failure feedback packet through the SPI_MISO signal line. The second identification field of the success feedback packet is different from the second identification field of the failure feedback packet.

[0027] As a write mask command of the present invention, it includes an address field, a data field, and a mask field. The write mask command is included in a command packet. The command packet includes one or more commands, at least one command is a write mask command, and the command packet is transmitted and executed based on an interface system. The interface system includes a main controller, an interface module, and a functional module. The main controller is connected to the interface module, and the interface module is connected to the functional module. The main controller sends the command packet to the interface module. After receiving the command packet, the interface module sends the command packet to the functional module. After receiving the command packet, the functional module executes the command included in the command packet. Executing the write mask command includes: writing the bits of the write mask command data field corresponding to the bits of the mask field 1 in the write mask command into the storage space pointed to by the write mask command address field.

[0028] Preferably, after the functional module executes the command included in the command packet, the function module returns a status packet to the interface module, including: when the result of the functional module executing each command included in the command packet is successful, the function module returns a status packet with success status information; when the result of the functional module executing at least one command included in the command packet is failure, the function module returns a status packet with failure status information; after the interface module receives the status packet from the functional module, it returns the status information of the status packet to the main controller.

[0029] Furthermore, the main controller is an I2C main controller, the interface module is an I2C interface module, and the I2C main controller is connected to the I2C interface module via an I2C clock line and an I2C data line.

[0030] Furthermore, the I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module. After receiving the command packet, the I2C interface module pulls down the I2C clock line level and sends the command packet to the functional module.

[0031] Further, when the I2C interface module receives a status packet from the functional module and the status information of the status packet is success, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller; when the I2C interface module receives a status packet from the functional module and the status information of the status packet is failure, the I2C interface module stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller.

[0032] Further, when the I2C interface module receives a status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK or I2C NAK to the I2C master controller. If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns status information of the status packet to the I2C master controller.

[0033] Further, after the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status packet to the I2C master controller after receiving the status packet from the functional module.

[0034] Further, after the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is success, then the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller; after the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is failure, then the I2C interface module returns an I2C NAK to the I2C master controller.

[0035] Furthermore, the I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module, and then the I2C master controller initiates a subsequent I2C read operation to read status information. After receiving the address byte of the subsequent I2C read operation, the I2C interface module pulls down the I2C clock line level and sends the received command packet to the functional module. After the functional module executes the command contained in the command packet, it returns the status packet to the interface module. When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns the status information of the status packet to the I2C master controller.

[0036] Furthermore, the main controller is an SPI main controller, the interface module is an SPI interface module, and the SPI main controller is connected to the SPI interface module via an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line.

[0037] Further, the SPI master controller generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module through the SPI_MOSI signal line, the SPI interface module reads the command packet through the SPI_MOSI signal line, the command packet starts with a first identification field, after the SPI interface module receives the status packet from the functional module, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sends a feedback packet to the SPI master controller through the SPI_MISO signal line, the SPI master controller reads the feedback packet through the SPI_MISO signal line, the feedback packet starts with a second identification field, and the feedback packet includes the status information included in the status packet.

[0038] Further, when the SPI master controller generates a clock edge on SPI_CK, if the SPI interface module has not received status packets from all functional modules, the SPI interface module sends data that cannot be identified as the feedback packet to the SPI master controller via the SPI_MISO signal line.

[0039] Furthermore, after the SPI interface module sends the feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets sent by the SPI master controller through the SPI_MOSI signal line.

[0040] Further, the feedback packet is divided into a success feedback packet and a failure feedback packet. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is success, the SPI interface module sends a success feedback packet through the SPI_MISO signal line. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is failure, the SPI interface module sends a failure feedback packet through the SPI_MISO signal line. The second identification field of the success feedback packet is different from the second identification field of the failure feedback packet.

[0041] The present invention provides a method for writing mask data. A main controller can quickly configure some bits in a storage space pointed to by a target address in a functional module through an interface module such as I2C or SPI, that is, the main controller can quickly write mask data to a target device through an I2C interface or an SPI interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A structural block diagram of an interface system of the present invention is schematically shown;

[0044] Figure 2 A schematic diagram showing the transmission of a command packet, a status packet and status information in an interface system of the present invention is shown;

[0045] Figure 3 A schematic diagram of the data structure of a command packet of the present invention is shown;

[0046] Figure 4 A schematic diagram of the structure of a command packet including a write mask command of the present invention is shown;

[0047] Figure 5 A data structure diagram of a write mask command of the present invention is shown;

[0048] Figure 6 A schematic diagram of the structure of a command packet including a write mask command and a write command according to the present invention is shown;

[0049] Figure 7 A data structure diagram of a write command of the present invention is shown;

[0050] Figure 8 A schematic diagram of the structure of a command packet including a write mask command and a read command according to the present invention is shown;

[0051] Fig. 9 A data structure diagram of a read command of the present invention is shown;

[0052] Fig.10 A schematic diagram of the structure of a command packet including a write mask command, a write command and a read command according to the present invention is shown;

[0053] Fig.11 A structural block diagram showing an interface system of the present invention in which the main controller is an I2C main controller and the interface module is an I2C interface module;

[0054] Fig.12 Shown is a timing diagram of an I2C write operation of the present invention;

[0055] Fig.13 Shown is a timing diagram of an I2C read operation of the present invention;

[0056] Fig.14 The timing diagram of the I2C continuous read and write operation of the present invention is shown;

[0057] Fig.15 The timing diagram of initiating an I2C write operation and sending a command packet of the present invention is shown;

[0058] Fig.16 It shows a timing diagram of initiating an I2C write operation to send a command packet and the status information of the status packet is a success and a timing diagram of the status information of the status packet is a failure in one embodiment of the present invention;

[0059] Fig.17 A timing diagram showing an I2C write operation sending a command packet and a subsequent I2C operation being an I2C read operation in one embodiment of the present invention is shown;

[0060] Fig.18 A timing diagram showing another embodiment of the present invention in which an I2C write operation is initiated to send a command packet and the subsequent I2C operation is an I2C read operation;

[0061] Fig.19 It shows a timing diagram of another embodiment of the present invention in which an I2C write operation is initiated to send a command packet and the status information of the status packet is successful;

[0062] Fig. 20 A timing diagram showing another embodiment of the present invention in which an I2C write operation is initiated to send a command packet and the status information of the status packet is failure;

[0063] Fig.21 A structural block diagram showing a main controller of an interface system of the present invention is an SPI main controller, and an interface module is an SPI interface module;

[0064] Fig. 22 A schematic diagram of the data structure of a command packet is shown when the main controller of the present invention is an SPI main controller and the interface module is an SPI interface module;

[0065] Fig.23 A timing diagram of a first embodiment of SPI data writing of the present invention is shown;

[0066] Fig.24 A timing diagram of a second embodiment of SPI data writing of the present invention is shown;

[0067] Fig.25 A timing diagram of a third embodiment of SPI data writing according to the present invention is shown.

[0068] The meanings of the text symbols in the above drawings are as follows:

[0069] 100: main controller; 100a: I2C main controller; 100b: SPI main controller;

[0070] 200: interface module; 200a: I2C interface module; 200b: SPI interface module;

[0071] 300: Functional module;

[0072] SDA: I2C data line; SCL: I2C clock line;

[0073] S: indicates the I2C START signal. The corresponding I2C bus state is that when SCL is at a high level, SDA jumps from a high level to a low level.

[0074] P: indicates the I2C STOP signal. The corresponding I2C bus state is that when SCL is at a high level, SDA jumps from a low level to a high level.

[0075] Sr: The corresponding I2C bus state is the same as S;

[0076] Sr / P: The corresponding I2C bus status is Sr or P;

[0077] ADR: I2C address;

[0078] R / W: indicates the read / write operation indication bit. When this bit is R, it indicates that the current operation is an I2C read operation. When this bit is W, it indicates that the current operation is an I2C write operation.

[0079] R: indicates the read operation indicator bit. The corresponding I2C bus state is that SDA is high during the period when SCL is high.

[0080] W: indicates the write operation indicator bit. The corresponding I2C bus state is that SDA is low while SCL is high.

[0081] BYTE: write operation data or read operation data, usually a multi-byte sequence. The content in the brackets behind it indicates the sequence number of the byte in the sequence. The command packet is sent through the write operation data, and the read data or status information is read through the read operation data. The smaller sequence number is sent first;

[0082] A: Indicates I2C ACK. The corresponding I2C bus state is that SDA is always low while SCL is high.

[0083] N: indicates I2C NAK. The corresponding I2C bus state is that SDA is always high while SCL is high.

[0084] STATUS: Bytes containing status information and a sequence of I2C ACK / I2C NAK between bytes;

[0085] A / N: The corresponding I2C bus state is that SDA is always high or always low during the period when SCL is high.

[0086] HOLD: SCL is a continuous low level;

[0087] IDLE: The corresponding I2C bus status includes the following two possibilities:

[0088] (1) Both SCL and SDA are high level;

[0089] (2) SCL and SDA may have other level states, but the combination of these level states does not indicate a legal I2C operation. When IDLE is about to end, SCL and SDA are both high levels.

[0090] SPI_CK: SPI_CK signal line; SPI_MOSI: SPI_MOSI signal line; SPI_MISO: SPI_MISO signal line; SPI_CSN: SPI_CSN signal line. DETAILED DESCRIPTION

[0091] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0092] like Figure 1 As shown, according to an embodiment of the present invention, an interface system is provided, the interface system comprising a main controller 100, an interface module 200, and a functional module 300, the main controller 100 is connected to the interface module 200, and the interface module 200 is connected to the functional module 300. The interface module 200 and the functional module 300 can be in the same chip, the same circuit board, or the same device, or can be located in a different device from the interface module, and the present invention does not limit the distance between the interface module 200 and the functional module 300. The interface module 200 and the functional module 300 can communicate through an existing or custom communication protocol.

[0093] like Figure 2As shown, according to an embodiment of the present invention, a method for writing mask data is provided, the main controller 100 sends a command packet to the interface module 200, the command packet includes one or more commands, after the interface module 200 receives the command packet, it sends the command packet to the functional module 300, when the interface module 200 sends the command packet to the functional module 300, the content in the command packet can be modified, added or deleted, and the present invention does not limit or stipulate this, after the functional module 300 receives the command packet, it executes the command included in the command packet, and returns a status packet to the interface module 200, including: when the result of the functional module 300 executing each command included in the command packet is successful, the functional module 300 returns a status packet with a successful status information, when the result of the functional module 300 executing at least one command included in the command packet is a failure, the functional module 300 returns a status packet with a failed status information. After the interface module 200 receives the status packet from the functional module 300, it returns the status information of the status packet to the main controller 100.

[0094] like Figure 3 As shown, the command packet of the present invention includes one or more commands, and an exemplary command packet includes command 1, command 2, ..., command K.

[0095] In one embodiment, the function module 300 receives a command packet and executes one or more commands contained in the command packet. When the execution result of a command is failure, the function module 300 stops executing subsequent commands, and the function module 300 returns a status packet with failure status information to the interface module 200. In another embodiment, when the execution result of a command is failure, the function module 300 may choose to continue to execute subsequent commands, and the function module 300 returns a status packet with failure status information to the interface module 200.

[0096] like Figure 4 As shown, in an application embodiment of the present invention, the command packet includes one or more commands, at least one command is a write mask command, and the write mask command includes an address field, a data field, and a mask field.

[0097] In this embodiment, the specific structure of the write mask command is as follows: Figure 5 shown. Figure 5The lower 6 bits of byte 0 are the command category identification field, and "001000" indicates that the command is a write mask command. The write mask command also includes an 8-bit register base address field SEG[7:0], a 10-bit register offset address field ADDR[9:0], a 16-bit data field Data[15:0], and a 16-bit mask field MASK[15:0]. The 8-bit register base address field SEG[7:0] and the 10-bit register offset address field ADDR[9:0] are collectively referred to as the address field Address. In other embodiments, the position and bit width of the command category identification field, address field, data field, and mask field in the write mask command may be different from those in this embodiment, and there may be no command category identification field. The present invention does not limit the position and bit width of the address field, data field, and mask field in the write mask command.

[0098] After receiving the command packet, the function module 300 executes the command contained in the command packet, wherein executing the write mask command includes: writing the bits of the write mask command data field corresponding to the bits of the mask field 1 in the write mask command into the storage space pointed to by the write mask command address field. For example, if the mask field MASK is a 16-bit binary sequence "0001000100010001", the 0th, 4th, 8th, and 12th bits of the data field Data from the low bit to the high bit should be written into the 0th, 4th, 8th, and 12th bits in the storage space pointed to by the address field Address, and the remaining bits in the storage space remain unchanged.

[0099] In some application embodiments, the storage space itself supports a write mask function (for example, an SRAM that supports a write mask function), and the function module 300 can directly send the address field Address, the data field Data, and the mask field MASK to the storage space, and the storage space completes the write mask function. In other application embodiments, the storage space itself does not support a write mask function, and the function module 300 can read the data in the storage space pointed to by the address field Address as the read data rdata, perform a bit-wise logical AND operation on the mask field MASK and the data field Data, perform a bit-wise logical AND operation on the opposite number of the bit-wise inversion of the mask field MASK and the read data rdata, and then perform a bit-wise logical OR operation on the results of the two logical AND operations as the data to be written wdata, and then write the data to be written wdata into the storage space pointed to by the address field Address.

[0100] like Figure 6 As shown, in another application embodiment of the present invention, the command packet includes one or more commands, at least one command is a write mask command, and at least one command is a write command, the write mask command includes an address field, a data field, and a mask field, and the write command includes an address field and a data field.

[0101] In this embodiment, the specific structure of the write mask command is as follows: Figure 5 As shown, the specific structure of the write command is as follows Figure 7 shown. Figure 7 The lower 6 bits of byte 0 are the command category identification field, and "000000" indicates that the command is a write command. The write command also includes an 8-bit register base address field SEG[7:0], a 10-bit register offset address field ADDR[9:0], and a 16-bit data field Data[15:0]. The 8-bit register base address field SEG[7:0] and the 10-bit register offset address field ADDR[9:0] are collectively referred to as the address field Address. In other embodiments, the position and bit width of the command category identification field, address field, and data field in the write command may be different from that in the present embodiment, or there may be no command category identification field. The present invention does not limit the position and bit width of the address field and data field in the write command.

[0102] After receiving the command packet, the functional module 300 executes the command contained in the command packet, wherein executing the write command includes: writing the data field in the write command into the storage space pointed to by the address field of the write command.

[0103] like Figure 8 As shown, in another application embodiment of the present invention, the command packet includes one or more commands, at least one command is a write mask command, and at least one command is a read command, the write mask command includes an address field, a data field, and a mask field, and the read command includes an address field.

[0104] In this embodiment, the specific structure of the write mask command is as follows: Figure 5 As shown, the specific structure of the read command is as follows Fig. 9 shown. Fig. 9 The lower 6 bits of byte 0 are the command category identification field, "010000" indicates that the command is a read command, and the read command also includes an 8-bit register base address field SEG[7:0], a 10-bit register offset address field ADDR[9:0], and the 8-bit register base address field SEG[7:0] and the 10-bit register offset address field ADDR[9:0] are collectively referred to as the address field Address. In other embodiments, the position and bit width of the command category identification field and the address field in the read command may be different from that in this embodiment, and there may be no command category identification field. The present invention does not limit the position and bit width of the address field in the read command.

[0105] After receiving the command packet, the function module 300 executes the command contained in the command packet, wherein executing the read command includes: reading out the data in the storage space pointed to by the address field in the read command.

[0106] After executing the read command contained in the command packet, the function module 300 returns not only the status packet but also the read data to the interface module 200. After receiving the read data and status packet from the function module 300, the interface module 200 returns the status information of the read data and status packet to the main controller 100.

[0107] like Fig.10 As shown, in another application embodiment of the present invention, the command packet includes one or more commands, at least one command is a write mask command, at least one command is a write command, and at least one command is a read command, the write mask command includes an address field, a data field, and a mask field, the write command includes an address field and a data field, and the read command includes an address field.

[0108] In this embodiment, the specific structure of the write mask command is as follows: Figure 5 As shown, the specific structure of the write command is as follows Figure 7 As shown, the specific structure of the read command is as follows Fig. 9 shown.

[0109] like Fig.11 As shown, in one embodiment, the main controller 100 is an I2C main controller 100a, and the interface module 200 is an I2C interface module 200a.

[0110] The I2C master controller 100a is connected to the I2C interface module 200a via the I2C clock line (SCL) and the I2C data line (SDA). The I2C master controller 100a initiates an I2C write operation and sends a command packet to the I2C interface module 200a. After receiving the command packet, the I2C interface module 200a pulls down the I2C clock line (SCL) level and sends the command packet to the functional module 300.

[0111] After receiving the command packet, the function module 300 executes one or more commands contained in the command packet and returns the status packet to the I2C interface module 200a. The I2C interface module 200a receives the status packet from the function module 300 and returns the status information of the status packet to the I2C main controller 100a, including:

[0112] When the I2C interface module 200a receives the status packet from the functional module 300 and the status information of the status packet is success, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level and returns an I2C ACK to the I2C master controller 100a.

[0113] When the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level and returns an I2C NAK to the I2C master controller 100a.

[0114] like Fig.12 As shown, the I2C write operation includes a write address byte and one or more write operation data bytes (BYTE(1), ..., BYTE(N), shaded). The write address byte is the first byte sent. The write address byte includes an I2C address (ADR) and a write operation indicator bit (W). According to the standard I2C specification, the write operation indicator bit (W) is a low level.

[0115] In this embodiment, the write address byte and the write operation data byte are both 8 bits, wherein the write address byte includes a 7-bit I2C address (ADR) and a 1-bit write operation indicator bit (W). The present invention does not limit the number of bits of the write address byte and the write operation data byte. In other embodiments, the write address byte and the write operation data byte can be other numbers of bits.

[0116] When the I2C master controller 100a initiates an I2C write operation, the I2C master controller 100a first drives the I2C clock line (SCL) and the I2C data line (SDA) according to the standard I2C specification, generates an I2C START signal (S), and then sends a write address byte. After receiving the write address byte, the I2C interface module 200a drives the I2C data line (SDA) and generates an acknowledgement bit. According to the standard I2C specification, the acknowledgement bit can be an I2C ACK (the I2C data line level is low) or an I2C NAK (the I2C data line level is high).

[0117] When the response bit of the write address byte is I2C ACK, the I2C master controller 100a can send one or more write operation data bytes. The I2C interface module 200a drives the I2C data line (SDA) to generate an response bit after receiving each write operation data byte. The response bit of the write operation data byte can be I2CACK (the I2C data line level is low) or I2C NAK (the I2C data line level is high).

[0118] According to the standard I2C specification, when sending a write address byte and one or more write operation data bytes, the I2C master controller 100a sends the number of bits contained in the write address byte and the write operation data byte by driving the I2C data line (SDA), and for each bit contained in the write address byte and the write operation data byte, the I2C master controller 100a drives the I2C clock line (SCL) to generate a clock pulse.

[0119] According to the standard I2C specification, the I2C master controller 100a also drives the I2C clock line (SCL) to generate a clock pulse corresponding to the response bit of the write address byte and the response bit of the write operation data byte. The I2C master controller 100a ends the current write operation by sending an I2C STOP signal (P) or an I2C START signal (S) defined by the standard I2C specification.

[0120] like Fig.13 As shown, the I2C read operation includes a read address byte and one or more read operation data bytes (BYTE(1), ..., BYTE(N), no shading). The read address byte is the first byte and is sent by the I2C master controller 100a. The one or more read operation data bytes are sent by the I2C interface module 200a. The read address byte includes an I2C address (ADR) and a read operation indication bit (R). According to the standard I2C specification, the read operation indication bit (R) is a high level.

[0121] In this embodiment, the read address byte and the read operation data byte are both 8 bits, wherein the read address byte includes a 7-bit I2C address (ADR) and a 1-bit read operation indicator bit (R). The present invention does not limit the number of bits of the read address byte and the read operation data byte. In other embodiments, the read address byte and the read operation data byte can be other numbers of bits.

[0122] When the I2C master controller 100a initiates an I2C read operation, the I2C master controller 100a first drives the I2C clock line and the I2C data line according to the standard I2C specification to generate an I2C START signal (S), and then sends a read address byte. After receiving the read address byte, the I2C interface module 200a drives the I2C data line to generate an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be I2CACK (the I2C data line level is low) or I2C NAK (the I2C data line level is high).

[0123] When the response bit of the read address byte is I2C ACK, the I2C interface module 200a can return one or more read operation data bytes by driving the I2C data line. The I2C master controller 100a drives the I2C data line to generate an response bit after receiving each read operation data byte. The response bit of the read operation data byte can be I2C ACK (the I2C data line level is low) or I2CNAK (the I2C data line level is high).

[0124] According to the standard I2C specification, when the I2C master controller 100a sends a read address byte and the I2C interface module 200a returns one or more read operation data bytes, the I2C master controller 100a sends the number of bits contained in the read address byte by driving the I2C data line, and the I2C interface module 200a returns the bits contained in the read operation data byte by driving the I2C data line, and for each bit contained in the read address byte and the read operation data byte, the I2C master controller 100a drives the I2C clock line to generate a clock pulse.

[0125] According to the standard I2C specification, the I2C master controller 100a also drives the I2C clock line to generate a clock pulse corresponding to the response bit of the read address byte and the response bit of the read operation data byte. The I2C master controller 100a ends the current read operation by sending an I2C STOP signal (P) or an I2C START signal (S) defined in the standard I2C specification.

[0126] An I2C write operation or I2C read operation cycle is started by the I2C START signal (S), but there are two ways to end it. The first is to end it with the I2C STOP signal (P). The timing is as follows: Fig.13 shown.

[0127] The second is to generate a new I2C START signal (S) and enter the next I2C write operation or I2C read operation. The timing is as follows: Fig.14 shown. Fig.14 The dashed line between the acknowledge bit (A / N) and the I2C START signal (Sr) (such lines in other figures) is because the timing diagram is too long to be described in one row, so it is split into multiple rows to indicate that the two timing diagrams are connected.

[0128] Using any of the above-mentioned ending modes will not affect the method for writing mask data of the present invention. For the convenience of description, the end of an I2C operation (I2C write operation or I2C read operation) is described in this embodiment in a mode with an I2C STOP signal (P).

[0129] The command packet in the present invention is sent by writing operation data bytes (BYTE (1), ..., BYTE (N), shaded), such as Figure 3 As shown, two command packet embodiments are given:

[0130] The command packet may only include command 1, command 2, ..., command K.

[0131] The command packet may also include a command packet length field and command 1, command 2, ..., command K.

[0132] Among them, "BYTE(1), ..., BYTE(N)" indicates that there are one or more write operation data bytes, and "command 1, command 2, ..., command K" indicates that there are one or more commands.

[0133] Figure 3 The commands in can be write mask commands, write commands, or read commands. A command packet can contain one or more of the three types of commands: write mask commands, write commands, and read commands. Each type of command can have one or more commands, such as Figure 4 , Figure 6 , Figure 8 , Fig.10 shown.

[0134] It should be noted that the present invention does not limit the format of the command packet, that is, the command packet format in the present invention is not limited to Figure 3 In the two command packet embodiments shown, the I2C main controller 100a and the I2C interface module 200a may agree on other command packet formats, and the present invention does not limit the types of commands contained in the command packet and the number of commands of each type.

[0135] For example, when the I2C master controller 100a initiates a command packet, the I2C master controller 100a initiates an I2C write operation to send a write address byte and one or more write operation data bytes (BYTE(1), ..., BYTE(N), shaded) of the command packet to the I2C interface module 200a.

[0136] The I2C interface module 200a has a logic circuit of the I2C interface, and the I2C interface module 200a receives and responds to data from the I2C main controller 100a. The I2C interface module 200a is interconnected with the I2C main controller 100a through the I2C bus (I2C clock line and I2C data line), and one I2C main controller 100a is connected to one or more I2C interface modules 200a, and each I2C interface module 200a has a unique I2C address (ADR) on the I2C bus (I2C clock line and I2C data line) where it is located. According to the standard I2C specification, each I2C write operation or I2C read operation except the I2C write broadcast is only for one of the I2C addresses (ADR), and the I2C interface module 200a using other I2C addresses does not participate in the I2C write operation or I2C read operation.

[0137] like Fig.15As shown, in a specific embodiment, the I2C interface module 200a has an I2C address of 0x50 with a length of 7 bits (corresponding to the write address byte 0xA0 or the binary value 1010000), and the I2C master controller 100a initiates an I2C write operation to sequentially write 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, 0x61, a total of 7 bytes of write operation data to the I2C interface module 200a, and the 7 bytes of write operation data contain a command packet. The 0xA0 byte corresponds to the write address byte, and the upper 7 bits correspond to the I2C address (ADR) of the I2C interface module 200a, and the lower 1 bit is the write operation indicator bit (W). The value of the write operation indicator bit (W) is 0, indicating that the current operation is a write operation, and the value of the byte is the binary number 10100000, that is, the hexadecimal number 0xA0.

[0138] In this example, the command packet format can be as follows Figure 3 The two command packet embodiments shown may also be other command packet formats agreed upon between the I2C master controller 100a and the I2C interface module 200a.

[0139] In the present invention, the I2C interface module 200a receiving the command packet means that the write operation data received by the I2C interface module 200a includes a complete command packet. Fig.15 In the illustrated embodiment, the write operation data of 7 bytes in length, 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, comprise a complete command packet, and therefore the I2C interface module 200a receives the last bit of the 0x61 byte, i.e., the I2C interface module 200a receives the command packet.

[0140] like Figure 3 As shown, the command packet may include a command packet length field, and the I2C interface module 200a may determine whether the received write operation data includes a complete command packet based on the command packet length field (or part of the command packet length field) according to the agreement between the I2C main controller 100a and the I2C main controller 100a, such as Figure 3 As shown, the command packet may not include the command packet length field. In this case, the I2C interface module 200a can determine whether the received write operation data includes a complete command packet based on the agreement between it and the I2C main controller 100a (this agreement is not based on the command packet length field).

[0141] Fig.15In the illustrated embodiment, the I2C interface module 200a receives the last bit of the 0x61 byte, the I2C interface module 200a receives the command packet, and then the I2C interface module 200a pulls down the I2C clock line level, the I2C bus is in the HOLD state (continuous low level state), and the I2C interface module 200a sends the command packet to the functional module 300. The functional module 300 receives the command packet and executes one or more commands contained in the command packet, namely, command 1, command 2, ..., command K, and then returns a status packet to the I2C interface module 200a, including:

[0142] When the execution result of each command included in the command packet is successful, the function module 300 returns a status packet with status information of success to the I2C interface module 200a;

[0143] When the execution result of at least one command in the commands included in the command packet is failure, the function module 300 returns a status packet with failure status information to the I2C interface module 200a.

[0144] In the present invention, when the I2C interface module 200a sends a command packet to the functional module 300, the content in the command packet may be modified, added or deleted, and the present invention does not limit or stipulate this.

[0145] According to an embodiment of the present invention, when the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is success, the I2C interface module 200a stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller 100a.

[0146] When the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller 100a.

[0147] The subsequent I2C operation referred to in the present invention is relative to the previous I2C operation, and the I2C operation may be an I2C write operation or an I2C read operation.

[0148] like Fig.16 As shown, examples are given to describe the situation when the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is success, and the situation when the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is failure.

[0149] The I2C master controller 100a initiates an I2C operation (I2C write operation) with a sequence number of m (m is a natural number), and the I2C operation with a sequence number of m+1 initiated by the I2C master controller 100a is a subsequent I2C operation (relative to the I2C operation with a sequence number of m).

[0150] Fig.16 In one embodiment shown, the I2C master controller 100a sends a command packet through an I2C write operation with a sequence number of m, and the I2C interface module 200a pulls down the I2C clock line level after receiving the command packet (after receiving BYTE (N)).

[0151] At the first moment, the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is success. The I2C interface module 200a stops pulling down the I2C clock line level and terminates the HOLD state (terminates the continuous low level state).

[0152] At moment ②, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation with sequence number m (I2C write operation) and initiates the I2C operation with sequence number m+1 (subsequent I2C operation), and the subsequent I2C operation is an I2C write operation or an I2C read operation.

[0153] After the I2C interface module 200a returns I2C ACK in the I2C operation with sequence number m, it continues to receive the subsequent I2C operation initiated by the I2C master controller 100a (referring to returning I2C ACK after receiving the read address byte or the write address byte in the I2C operation with sequence number m+1 and continuing the I2C operation with sequence number m+1). If the subsequent I2C operation is an I2C write operation, the I2C interface module 200a returns I2C ACK after receiving the write address byte and continues to receive the write operation byte. If the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns I2C ACK after receiving the read address byte and continues to return the status information (STATUS) of the status packet (in this example, the part of the subsequent I2C operation after the read address byte or the write address byte is not in the Fig.16 If the command packet sent by the I2C write operation with sequence number m includes a read command, the subsequent I2C operation should be an I2C read operation. After receiving the read address byte, the I2C interface module 200a returns an I2C ACK and continues to return the status information (STATUS) and read data of the status packet.

[0154] Fig.16 In another embodiment shown, the I2C master controller 100a sends a command packet through an I2C write operation with a sequence number of m, and the I2C interface module 200a pulls down the I2C clock line level after receiving the command packet (after receiving BYTE (N)).

[0155] At time ①, the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is failure. The I2C interface module 200a stops pulling down the I2C clock line level and terminates the HOLD state (terminates the continuous low level state).

[0156] At time ②, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation (I2C write operation) with sequence number m.

[0157] After the I2C interface module 200a returns I2C NAK in the I2C operation with sequence number m, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C write operation, after the I2C interface module 200a receives the write address byte, the I2C interface module 200a returns I2C NAK to the I2C master controller 100a, so that the subsequent I2C operation (I2C write operation) is terminated. After the I2C interface module 200a returns an I2C NAK in the I2C operation with sequence number m, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C read operation, after the I2C interface module 200a receives the read address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a and continues to return the status information (STATUS) of the status packet. After completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a can continue to receive subsequent I2C operations initiated by the I2C master controller 100a (the subsequent I2C operation part in this example is not included in the ACK). Fig.16 (displayed in the figure).

[0158] In the present invention, the status information (STATUS) may be the success or failure information contained in the status packet, or may include other information contained in the status packet. In one embodiment, the status information (STATUS) may include the execution result information of each command in the command packet executed by the functional module 300. After receiving the status information, the I2C master controller 100a may learn the execution status of each command in the command packet by the functional module 300 according to the status information, and may then perform subsequent processing according to the execution status. Fig.16In the illustrated embodiment, when the I2C interface module 200a receives a status packet from the functional module 300, the I2C interface module 200a stops pulling down the I2C clock line level, and returns an I2CACK (when the status information of the status packet is success) or an I2C NAK (when the status information of the status packet is failure) to the I2C master controller 100a. If the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C read operation, after the I2C interface module 200a receives the read address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a and continues to return the status information (STATUS) of the status packet.

[0159] like Fig.17 In the illustrated embodiment, the I2C master controller 100a sends a command packet through an I2C write operation with a sequence number of m. At the first moment, the I2C interface module 200a pulls down the I2C clock line level after receiving the command packet (after receiving BYTE (N)). At the second moment, when the I2C interface module 200a receives the status packet from the functional module 300, it stops pulling down the I2C clock line level and returns an I2C ACK or I2C NAK to the I2C master controller 100a. In this example, the I2C master controller 100a and the I2C interface module 200a can agree on the specific meaning of I2C ACK or I2C NAK. After the I2C interface module 200a stops pulling down the I2C clock line level and returns I2CACK or I2C NAK to the I2C master controller 100a, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C write operation, after the I2C interface module 200a receives the write address byte, the I2C interface module 200a returns I2C NAK to the I2C master controller 100a, so that the subsequent I2C operation (I2C write operation) is terminated. If the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C read operation, after the I2C interface module 200a receives the read address byte, the I2C interface module 200a returns I2C NAK to the I2C master controller 100a. ACK and continue to return the status information (STATUS) of the status packet. If the command packet sent by the I2C write operation with sequence number m includes a read command, the I2C interface module 200a should also return the read data to the I2C master controller 100a. After completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a can continue to receive the subsequent I2C operation initiated by the I2C master controller 100a (the subsequent I2C operation is the I2C write operation in this example, which is not in the Fig.17 (displayed in the figure).

[0160] According to an embodiment of the present invention, the I2C master controller 100a is connected to the I2C interface module 200a via the I2C clock line and the I2C data line. The I2C master controller 100a initiates an I2C write operation to send a command packet to the I2C interface module 200a. After receiving the command packet, the I2C interface module 200a sends the command packet to the functional module 300.

[0161] After receiving the command packet, the functional module 300 executes one or more commands contained in the command packet, namely command 1, command 2, ..., command K, and then returns a status packet to the I2C interface module 200a, including:

[0162] When the execution result of each command included in the command packet is successful, the function module 300 returns a status packet with status information of success to the I2C interface module 200a;

[0163] When the execution result of at least one command in the commands included in the command packet is failure, the function module 300 returns a status packet with failure status information to the I2C interface module 200a.

[0164] In the present invention, when the I2C interface module 200a sends a command packet to the functional module 300, the content in the command packet may be modified, added or deleted, and the present invention does not limit or stipulate this.

[0165] The function module 300 returns the status packet to the I2C interface module 200a, and the I2C interface module 200a returns the status information of the status packet to the I2C main controller 100a, including:

[0166] After the I2C interface module 200a receives the command packet, if the subsequent I2C operation initiated by the I2C master controller 100a is an I2C read operation and the I2C interface module 200a receives a status packet from the functional module 300, the I2C interface module 200a returns status information of the status packet to the I2C master controller 100a.

[0167] If the subsequent I2C operation initiated by the I2C master controller 100a is an I2C write operation, and the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is success, the I2C interface module 200a receives the subsequent I2C write operation initiated by the I2C master controller 100a;

[0168] If the subsequent I2C operation initiated by the I2C master controller 100a is an I2C write operation, and the I2C interface module 200a receives a status packet from the functional module 300 and the status information of the status packet is failure, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a.

[0169] like Fig.18 As shown, the I2C operation with sequence number m initiated by the I2C master controller 100a is an I2C write operation, and the command packet is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a.

[0170] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)) (i.e., after the I2C interface module 200a receives the complete command packet), the I2C interface module 200a may return an I2C ACK or an I2C NAK to the I2C master controller 100a, which is specifically selected by the agreement between the I2C master controller 100a and the I2C interface module 200a. The I2C master controller 100a and the I2C interface module 200a may agree that after the Nth write operation data byte (BYTE(N)), whether I2C ACK or I2C NAK indicates the successful reception of the Nth write operation data byte (i.e., the complete command packet). It may also be agreed that the I2C NAK indicates that the Nth write operation data byte (BYTE(N)) has not been successfully received (i.e., the complete command packet has not been successfully received). In the following description of the present invention, after the Nth write operation data byte (BYTE(N)), whether the I2C interface module 200a returns I2CACK or I2C NAK to the I2C master controller 100a, it indicates the successful reception of the Nth write operation data byte (i.e., the complete command packet).

[0171] After the I2C master controller 100a completes sending the Nth write operation data byte (BYTE(N)), regardless of whether the I2C interface module 200a returns an I2C ACK or an I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation with sequence number m (I2C write operation) and may choose to initiate an I2C operation with sequence number m+1 (subsequent I2C operation).

[0172] When the I2C operation with sequence number m+1 (subsequent I2C operation) is an I2C read operation, if the I2C interface module 200a receives a status packet (the status packet corresponding to the I2C operation process with sequence number m) from the functional module 300, then after the I2C master controller 100a sends the read address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a and returns the status information (STATUS) of the status packet. If the command packet sent by the I2C write operation with sequence number m includes a read command, the I2C interface module 200a should also return the read data to the I2C master controller 100a.

[0173] like Fig.19 and Fig. 20 As shown, the I2C operation with sequence number m initiated by the I2C master controller 100a is an I2C write operation, and the command packet is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a.

[0174] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)) (ie, after the I2C interface module 200a receives the complete command packet), the I2C interface module 200a may return an I2C ACK or an I2C NAK to the I2C master controller 100a.

[0175] After the I2C master controller 100a completes sending the Nth write operation data byte (BYTE(N)), regardless of whether the I2C interface module 200a returns I2C ACK or I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation with sequence number m (I2C write operation) and may choose to initiate an I2C operation with sequence number m+1 (subsequent I2C operation).

[0176] When the I2C operation with sequence number m+1 (subsequent I2C operation) is an I2C write operation, if the I2C interface module 200a receives a status packet (the status packet corresponding to the I2C operation process with sequence number m) from the functional module 300 and the status information of the status packet is successful, then after the I2C master controller 100a sends the write address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a, and the I2C interface module 200a receives the write operation data byte sent by the I2C operation with sequence number m+1 (subsequent I2C operation / I2C write operation) initiated by the I2C master controller 100a, such as Fig.19 shown.

[0177] When the I2C operation with sequence number m+1 (subsequent I2C operation) is an I2C write operation, if the I2C interface module 200a receives a status packet (the status packet corresponding to the I2C operation with sequence number m) from the functional module 300 and the status information of the status packet is failure, then after the I2C main controller 100a sends the write address byte, the I2C interface module 200a returns an I2C NAK to the I2C main controller 100a, and the main controller 100a terminates the initiation of the I2C operation with sequence number m+1 (subsequent I2C operation / I2C write operation), such as Fig. 20 shown.

[0178] like Fig.11As shown, in another embodiment, the main controller 100 is an I2C main controller 100a, and the interface module 200 is an I2C interface module 200a. The I2C main controller 100a initiates an I2C write operation to send a command packet to the I2C interface module 200a, and then the I2C main controller 100a initiates a subsequent I2C read operation to read the status information.

[0179] In this example, after the I2C master controller 100a initiates an I2C write operation to send a command packet to the I2C interface module 200a, it initiates a subsequent I2C read operation to read the status information.

[0180] After receiving the address byte of the subsequent I2C read operation, the I2C interface module 200a pulls down the I2C clock line level and sends the received command packet to the functional module 300.

[0181] After receiving the command packet, the functional module 300 executes one or more commands contained in the command packet and returns a status packet to the I2C interface module 200a, including:

[0182] When the execution result of each command included in the command packet is successful, the functional module 300 returns a status packet with status information indicating success to the I2C interface module 200a.

[0183] When the execution result of at least one command in the command packet is failed, the function module 300 returns a status packet with status information of failure to the I2C interface module 200a.

[0184] After the I2C interface module 200a receives the status packet from the functional module 300, the I2C interface module 200a stops pulling down the level of the I2C clock line, and returns the status information of the status packet to the I2C master controller 100a.

[0185] like Fig.21 As shown, in one embodiment, the main controller 100 is a SPI main controller 100b, the interface module 200 is a SPI interface module 200b, and the SPI main controller 100b is connected to the SPI interface module 200b through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line.

[0186] The SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b via the SPI_MOSI signal line. The command packet starts with a first identification field. After receiving the command packet from SPI_MOSI, the SPI interface module 200b sends the command packet to the functional module 300.

[0187] After receiving the command packet, the function module 300 executes one or more commands contained in the command packet, namely, command 1, command 2, ..., command K, and then returns a status packet to the SPI interface module 200b, including:

[0188] When the execution result of each command included in the command packet is successful, the function module 300 returns a status packet with status information of success to the SPI interface module 200b;

[0189] When the execution result of at least one command in the commands included in the command packet is failure, the function module 300 returns a status packet with failure status information to the SPI interface module 200b.

[0190] In the present invention, when the SPI interface module 200b sends the command packet to the functional module 300, the content in the command packet may be modified, added or deleted, and the present invention does not impose any limitation or regulation on this.

[0191] The function module 300 returns the status packet to the SPI interface module 200b, and the SPI interface module 200b receives the status packet from the function module 300 and returns the status information of the status packet to the SPI master controller 100b, including:

[0192] After the SPI interface module 200b receives the status packet from the functional module 300, when the SPI master controller 100b generates a clock edge on SPI_CK, the SPI interface module 200b sends a feedback packet to the SPI master controller 100b through the SPI_MISO signal line. The feedback packet starts with the second identification field and contains the status information contained in the status packet.

[0193] like Fig. 22 The illustrated embodiment is a data structure of a command packet when the main controller 100 is an SPI main controller 100b and the interface module 200 is an SPI interface module 200b. Two command packet embodiments are exemplarily given in the embodiment:

[0194] The command packet may include a first identification field and command 1, command 2, ..., command K, and start with the first identification field.

[0195] The command packet may also include a first identification field, a command packet length field, and command 1, command 2, ..., command K, and start with the first identification field.

[0196] The first identification field, command packet length field (if any), command 1, command 2, ..., command K contained in the command packet are composed of a binary bit sequence. The present invention does not limit the length of the binary bit sequence of the first identification field, command packet length field (if any), command 1, command 2, ..., command K.

[0197] Fig. 22The commands in can be write mask commands, write commands, or read commands. A command packet can contain one or more of the three types of commands: write mask commands, write commands, and read commands. Each type of command can have one or more commands, such as Figure 4 , Figure 6 , Figure 8 , Fig.10 shown.

[0198] It should be noted that the present invention does not limit the format of the command packet, that is, the command packet format in the present invention is not limited to Fig. 22 The SPI master controller 100b and the SPI interface module 200b may agree on other command packet formats, and the present invention does not limit the types of commands contained in the command packet and the number of each type of commands.

[0199] In the present invention, the SPI interface module 200b receiving the command packet means that the data received by the SPI interface module 200b from the SPI_MOSI signal line contains a complete command packet, such as Fig. 22 As shown, the command packet may include a command packet length field, and the SPI interface module 200b may determine whether the received data includes a complete command packet based on the command packet length field (or part of the command packet length field) according to the agreement between the SPI master controller 100b and the SPI master controller 100b, such as Fig. 22 As shown, the command packet may not include the command packet length field. In this case, the SPI interface module 200b determines whether the received data includes a complete command packet based on the agreement between the SPI master controller 100b (this agreement is not based on the command packet length field).

[0200] The SPI master controller 100b drives the SPI_CK signal line, and the SPI master controller 100b generates a clock edge on the SPI_CK signal line. The SPI master controller 100b samples the data on the SPI_MISO signal line by the rising edge or falling edge of the clock on the SPI_CK signal line, and the SPI interface module 200b samples the data on the SPI_MOSI signal line by the rising edge or falling edge of the clock on the SPI_CK signal line, so as to realize bidirectional transmission of data between the SPI master controller 100b and the SPI interface module 200b.

[0201] The present invention is not limited to sampling the data on the SPI_MISO signal line and the SPI_MOSI signal line at the rising edge or falling edge of the clock on the SPI_CK signal line. In the embodiments of the present invention described below, the data on the SPI_MISO signal line and the SPI_MOSI signal line are sampled at the rising edge of the clock on the SPI_CK signal line, that is, in the embodiments of the present invention described below, the rising edge of the clock on the SPI_CK signal line is the sampling clock edge. In other embodiments of the present invention, the data on the SPI_MISO signal line and the SPI_MOSI signal line may also be sampled at the falling edge of the clock on the SPI_CK signal line, that is, in these embodiments, the falling edge of the clock on the SPI_CK signal line is the sampling clock edge.

[0202] like Fig.23 As shown, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line. The command packet includes N bytes, each byte is 8-bit binary data, the first byte is the first identification field, and the 8-bit binary data of the first byte is represented by C10, C11...C17. The Nth byte of the command packet is the last byte of the command packet, and the 8-bit binary data of the Nth byte of the command packet is represented by CN0, CN1...CN7.

[0203] The SPI interface module 200b samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line and receives a command packet from the SPI_MOSI signal line. After the SPI interface module 200b samples the CN7 bit, the data received from the SPI_MOSI signal line contains a complete command packet, and the SPI interface module 200b receives the command packet.

[0204] After receiving the command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the command packet to the functional module 300. In the present invention, when the SPI interface module 200b sends the command packet to the functional module 300, the content in the command packet can be modified, added or deleted, and the present invention does not limit or stipulate this.

[0205] After receiving the command packet, the function module 300 executes one or more commands contained in the command packet, namely command 1, command 2, ..., command K, and then returns a status packet to the SPI interface module 200b, including:

[0206] When the execution result of each command included in the command packet is successful, the function module 300 returns a status packet with status information of success to the SPI interface module 200b;

[0207] When the execution result of at least one command in the commands included in the command packet is failure, the function module 300 returns a status packet with failure status information to the SPI interface module 200b.

[0208] At the first moment, the SPI interface module 200b receives the status packet, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI interface module 200b drives the SPI_MISO signal line, and sends a feedback packet through the SPI_MISO signal line. The SPI master controller 100b samples the data on the SPI_MISO signal line at the rising edge of the clock on the SPI_CK signal line, and reads the feedback packet. The feedback packet starts with the second identification field, and the feedback packet contains the status information contained in the status packet. The status information contained in the status packet can be success and failure, or other status information. In one embodiment, the status information can include the execution result information of each command in the command packet executed by the function module 300. After receiving the feedback packet, the SPI master controller 100b can learn the execution status of each command in the command packet by the function module 300 according to the feedback packet, and then can perform subsequent processing according to the execution status.

[0209] The feedback packet contains M bytes, each byte is 8-bit binary data, the first byte is the second identification field, the 8-bit binary data of the first byte is represented by A10, A11...A17, the Mth byte of the feedback packet is the last byte of the feedback packet, and the 8-bit binary data of the Mth byte of the feedback packet is represented by AM0, AM1...AM7.

[0210] For ease of understanding, Fig.23 In the illustrated embodiment and the following description of the present invention, each byte is described as 8-bit binary data, but the present invention is not limited to the number of bits of each byte, and each byte may also be other numbers of bits.

[0211] Fig.23 In the illustrated embodiment, the length of the first identification field and the second identification field is one byte, and the length of the command packet and the feedback packet is an integer multiple of bytes. For easy understanding, in the following description of the present invention, the length of the first identification field and the second identification field is one byte, and the length of the command packet and the feedback packet (including a success feedback packet and a failure feedback packet) is an integer multiple of bytes, but the present invention does not limit the length of the first identification field and the second identification field to one byte, nor does it limit the length of the first identification field and the second identification field to an integer multiple of bytes. The present invention also does not limit the length of the command packet and the feedback packet (including a success feedback packet and a failure feedback packet) to an integer multiple of bytes.

[0212] In the interval marked as "no clock edge", the SPI master controller 100b does not generate a sampling clock edge on the SPI_CK signal line. Fig.23In the description of the subsequent embodiments of the present invention, the levels of the SPI_MOSI and SPI_MISO signal lines remain unchanged in the "no clock edge" interval. The present invention is not limited to the levels of the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval. The levels of the SPI_MOSI and SPI_MISO signal lines can also change in the "no clock edge" interval, but because the sampling of data on the SPI_MOSI and SPI_MISO signal lines is only performed on the sampling clock edge of the SPI_CK signal line ( Fig.23 In the embodiment shown, the sampling clock edge is the rising edge of the clock, and the level changes on the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval will not be sampled and received.

[0213] exist Fig.23 In the illustrated embodiment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time. When sending a command packet through the SPI_MOSI signal line, the SPI interface module 200b has no feedback packet to send. At this time, the SPI interface module 200b drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200b of the present invention can also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200b should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100b on the sampling clock edge of the SPI_CK signal line ( Fig.23 In the embodiment shown, the sampling clock edge is the rising edge of the clock), and is not recognized as the second identification field (that is, it is not recognized as a valid value of the second identification field, thereby avoiding being recognized as a feedback packet). Fig.23 Taking the illustrated embodiment as an example, since the SPI interface module 200b drives the SPI_MISO signal line to a high level (sampled as continuous binary bits 1) during this period, in order not to be identified as the second identification field, the value of the second identification field should not be 0xFF.

[0214] exist Fig.23In the illustrated embodiment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and the SPI interface module 200b drives the SPI_MISO signal line. When sending a feedback packet through the SPI_MISO signal line, the SPI master controller 100b has no command packet to send. At this time, the SPI master controller 100b drives the SPI_MOSI signal line to a high level. During this period, the SPI master controller 100b of the present invention can also drive the SPI_MOSI signal line to a low level or a changing level, but the SPI master controller 100b should ensure that the level value driven on the SPI_MOSI signal line or the changing level value, if it is sampled by the SPI interface module 200b on the sampling clock edge of the SPI_CK signal line ( Fig.23 In the embodiment shown, the sampling clock edge is the rising edge of the clock), and is not recognized as the first identification field (that is, it is not recognized as a valid value of the first identification field, thereby avoiding being recognized as a command packet). Fig.23 Taking the illustrated embodiment as an example, since the SPI master controller 100b drives the SPI_MOSI signal line to a high level (sampled as continuous binary bits 1) during this period, in order not to be recognized as the first identification field, the value of the first identification field should not be 0xFF.

[0215] In addition to the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line, the SPI interface module 200b can also be connected to the SPI master controller 100b through the SPI_CSN signal line. The SPI master controller 100b drives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line, and the SPI interface module 200b receives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line. The SPI interface module 200b drives the SPI_MISO signal line, and the SPI master controller 100b receives the SPI_MISO signal line. The SPI_CSN signal line is a selection signal. In the SPI protocol, data transmission is performed only when the SPI_CSN signal line is low. One SPI master controller 100b can be connected to multiple SPI interface modules 200b, wherein the SPI master controller 100b and multiple SPI interface modules 200b share the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line, but each SPI interface module 200b has an independent SPI_CSN signal line input, when the SPI_CSN signal line of one SPI interface module 200b is high, this SPI interface module 200b does not drive the SPI_MISO signal line (the driver output of this SPI interface module 200b connected to the SPI_MISO signal line is in Hi-Z state), and one SPI interface module 200b drives the SPI_MISO signal line only when its SPI_CSN signal line is low. When one SPI master controller 100b is connected to multiple SPI interface modules 200b, at any time, only one SPI interface module 200b has the SPI_CSN signal line low, thereby avoiding conflicts caused by multiple SPI interface modules 200b driving the SPI_MISO signal line at the same time.

[0216] When a SPI master controller 100b is connected to only one SPI interface module 200b, the SPI interface module 200b can drive the SPI_MISO signal line at any time without causing a conflict. In this case, there may be no SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b. That is, when a SPI master controller 100b is connected to only one SPI interface module 200b, the SPI master controller 100b and the SPI interface module 200b may be connected only through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. Fig.23 This is the case in the description of the illustrated embodiment.

[0217] The description of the present invention only describes the case where there is no SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b, but according to the description of the present invention, it is easy to expand to the case where there is a SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b, and the description of the present invention will not repeat the case where there is a SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b. Whether there is a SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b, it is within the protection scope of the present invention.

[0218] According to an embodiment of the present invention, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads a feedback packet through the SPI_MISO signal line,

[0219] When the SPI interface module 200 b does not receive the status packet, the SPI interface module 200 b sends data that cannot be identified as a feedback packet to the SPI master controller 100 b through the SPI_MISO signal line.

[0220] by Fig.24 As shown in the figure as an example, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line. After receiving the command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the command packet to the functional module 300. The functional module 300 executes one or more commands included in the command packet, and then returns a status packet to the SPI interface module 200b. At the third moment, the SPI interface module 200b receives the status packet from the functional module 300. Before the third moment when the SPI interface module 200b receives the status packet from the functional module 300, between the first moment and the second moment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line. Fig.24 In the embodiment shown, the SPI interface module 200b drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200b should ensure that the level value driven on the SPI_MISO signal line or the changing level value is sampled by the SPI master controller 100b at the sampling clock edge on the SPI_CK signal line ( Fig.24In the embodiment shown, the sampling clock edge is the rising edge of the clock), which is not recognized as the second identification field (i.e., it is not recognized as a valid value of the second identification field, thereby avoiding being recognized as a feedback packet), that is, when the SPI interface module 200b does not receive the status packet from the functional module 300, if the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI interface module 200b sends data that cannot be recognized as a feedback packet to the SPI master controller 100b through the SPI_MISO signal line. At the third moment, after the SPI interface module 200b receives the status packet from the functional module 300, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the feedback packet from the SPI interface module 200b through the SPI_MISO signal line.

[0221] exist Fig.25 In the illustrated embodiment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line. After receiving the command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the command packet to the functional module 300. The functional module 300 executes one or more commands included in the command packet, and then returns a status packet to the SPI interface module 200b. At time ①, the SPI interface module 200b receives the status packet from the functional module 300, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads a feedback packet from the SPI interface module 200b through the SPI_MISO signal line. At the second moment, the SPI master controller 100b completes reading the feedback packet, the SPI interface module 200b completes sending the feedback packet, and the SPI master controller 100b continues to generate a clock edge on the SPI_CK signal line. At this time, the SPI interface module 200b drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to a low level or a changing level, but the SPI interface module 200b should ensure that the level value driven or the changing level value on the SPI_MISO signal line is sampled by the SPI master controller 100b on the sampling clock edge of the SPI_CK signal line ( Fig.25 In the illustrated embodiment, the sampling clock edge is the rising edge of the clock), and is not identified as the second identification field (ie, is not identified as a valid value of the second identification field, thereby avoiding being identified as a feedback packet).

[0222] According to the embodiment of the present invention, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line.

[0223] Then the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the feedback packet through the SPI_MISO signal line, and after the SPI interface module 200b sends the feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets.

[0224] In the present invention, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line. After receiving the command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the command packet to the function module 300. The function module 300 that receives the command packet executes one or more commands contained in the command packet, and then returns a status packet to the SPI interface module 200b. Then the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads a feedback packet through the SPI_MISO signal line. Before the SPI master controller 100b reads the feedback packet, if the SPI master controller 100b drives the SPI_MOSI signal line to send a command packet, the SPI interface module 200b can choose not to receive the command packet sent before the SPI master controller 100b reads the feedback packet. After the SPI master controller 100b reads the feedback packet, that is, after the SPI interface module 200b sends the feedback packet through the SPI_MISO signal line, the SPI interface module 200b can continue to receive subsequent command packets.

[0225] According to an embodiment of the present invention, the feedback packet can be divided into a success feedback packet and a failure feedback packet;

[0226] The SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the feedback packet through the SPI_MISO signal line.

[0227] When the SPI interface module 200 b receives the status packet from the functional module 300 and the status information contained in the status packet is success, the SPI interface module 200 b sends a success feedback packet through the SPI_MISO signal line.

[0228] When the SPI interface module 200 b receives a status packet from the functional module 300 and the status information contained in the status packet is failure, the SPI interface module 200 b sends a failure feedback packet through the SPI_MISO signal line.

[0229] In the present invention, the second identification field of the success feedback packet is different from the second identification field of the failure feedback packet, including: the binary sequence contained in the second identification field of the success feedback packet is different from the binary sequence contained in the second identification field of the failure feedback packet. The second identification field of the success feedback packet and the second identification field of the failure feedback packet can use the same or different bit width lengths, and the present invention does not limit whether the second identification field is a fixed length.

[0230] like Fig.23 As shown, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line. After receiving the command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the command packet to the functional module 300. After receiving the command packet, the functional module 300 executes one or more commands included in the command packet, and then returns a status packet to the SPI interface module 200b. At time ①, the SPI interface module 200b receives the status packet from the functional module 300. If the status information contained in the status packet received by the SPI interface module 200b is success, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads a feedback packet from the SPI interface module 200b through the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a success feedback packet to the SPI master controller 100b through the SPI_MISO signal line; if the status information contained in the status packet received by the SPI interface module 200b is failure, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads a feedback packet from the SPI interface module 200b through the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a failure feedback packet to the SPI master controller 100b through the SPI_MISO signal line.

[0231] The second identification field of the success feedback packet in the present invention is different from the second identification field of the failure feedback packet. When the SPI master controller 100b reads the feedback packet, it can judge whether the read feedback packet is a success feedback packet or a failure feedback packet through the second identification field of the feedback packet. Therefore, the feedback packet can only include the second identification field, so that the SPI master controller 100b can distinguish whether the read feedback packet is a success feedback packet or a failure feedback packet.

[0232] In addition to being an I2C master controller 100a and an SPI master controller 100b, the main controller 100 in the present invention can also be a master controller that complies with other interface protocols (for example, a master controller that complies with serial port UART protocol, CAN protocol, LIN protocol, etc.). In addition to being an I2C interface module 200a and an SPI interface module 200b, the interface module 200 in the present invention can also be an interface module that complies with other interface protocols (for example, an interface module that complies with serial port UART protocol, CAN protocol, LIN protocol, etc.). The use of a main controller that complies with other interface protocols and an interface module that complies with other interface protocols are also within the protection scope of the present invention.

[0233] According to an embodiment of the present invention, the main controller 100 (I2C main controller 100a or SPI main controller 100b or main controller conforming to other interface protocols) sends a command packet to the interface module 200 (I2C interface module 200a or SPI interface module 200b or interface module conforming to other interface protocols). After the interface module 200 receives the command packet, it sends the command packet to the functional module 300. The command packet contains one or more commands, such as Figure 3 and Fig. 22 Each command can be a write mask command, a write command, or a read command. A command packet can contain one or more of the three types of commands: write mask command, write command, and read command. Each type of command can have one or more commands, such as Figure 4 , Figure 6 , Figure 8 , Fig.10 shown.

[0234] The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes, modifications, substitutions and variations made to the above embodiments by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for writing mask data, based on an interface system, the interface system comprising a main controller, an interface module, and a functional module, the main controller is connected to the interface module, the interface module is connected to the functional module, characterized in that: The main controller sends a command packet to the interface module, the command packet includes one or more commands, at least one command is a write mask command, and the write mask command includes an address field, a data field, and a mask field. After receiving the command packet, the interface module sends the command packet to the function module. After receiving the command packet, the functional module executes the command contained in the command packet. Executing the write mask command includes: writing the bits of the write mask command data field corresponding to the bits of the mask field 1 in the write mask command into the storage space pointed to by the write mask command address field.

2. A method for writing mask data according to claim 1, characterized in that: After the function module executes the command included in the command package, the function module returns the status package to the interface module, including: when the result of the function module executing each command included in the command package is successful, the function module returns the status package with success information, when the result of the function module executing at least one command included in the command package is failure, the function module returns the status package with failure information, After receiving the status packet from the functional module, the interface module returns the status information of the status packet to the main controller.

3. A method for writing mask data according to claim 1, characterized in that: The command packet includes one or more commands, at least one command is a write command, and the write command includes an address field and a data field. After receiving the command packet, the functional module executes the command contained in the command packet, and executing the write command includes: writing the data field in the write command into the storage space pointed to by the address field of the write command.

4. A method for writing mask data according to claim 2, characterized in that: The main controller is an I2C main controller, the interface module is an I2C interface module, and the I2C main controller is connected to the I2C interface module via an I2C clock line and an I2C data line.

5. A method for writing mask data according to claim 4, characterized in that: The I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module. After receiving the command packet, the I2C interface module pulls down the I2C clock line level and sends the command packet to the functional module.

6. A method for writing mask data according to claim 5, characterized in that: When the I2C interface module receives a status packet from the functional module and the status information of the status packet is successful, the I2C interface module stops pulling down the I2C clock line level and returns I2CACK to the I2C master controller. When the I2C interface module receives a status packet from the functional module and the status information of the status packet is failure, the I2C interface module stops pulling down the I2C clock line level and returns I2CNAK to the I2C master controller.

7. A method for writing mask data according to claim 5, characterized in that: When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK or I2C NAK to the I2C master controller. If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns status information of the status packet to the I2C master controller.

8. A method for writing mask data according to claim 4, characterized in that: After the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status packet to the I2C master controller after receiving the status packet from the functional module.

9. A method for writing mask data according to claim 4, characterized in that: After the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is successful, then the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller, After the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is failure, the I2C interface module returns an I2C NAK to the I2C master controller.

10. A method for writing mask data according to claim 4, characterized in that: The I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module, and then the I2C master controller initiates a subsequent I2C read operation to read the status information. After receiving the address byte of the subsequent I2C read operation, the I2C interface module pulls down the I2C clock line level and sends the received command packet to the functional module. After the function module executes the command contained in the command packet, it returns the status packet to the interface module. When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns the status information of the status packet to the I2C main controller.

11. A method for writing mask data according to claim 2, characterized in that: The main controller is an SPI main controller, the interface module is an SPI interface module, and the SPI main controller is connected to the SPI interface module via an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line.

12. A method for writing mask data according to claim 11, characterized in that: The SPI master controller generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module through the SPI_MOSI signal line, and the SPI interface module reads the command packet through the SPI_MOSI signal line, wherein the command packet starts with a first identification field. After the SPI interface module receives the status packet from the functional module, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sends a feedback packet to the SPI master controller through the SPI_MISO signal line, and the SPI master controller reads the feedback packet through the SPI_MISO signal line. The feedback packet starts with a second identification field, and the feedback packet includes the status information included in the status packet.

13. A method for writing mask data according to claim 12, characterized in that: When the SPI master controller generates a clock edge on SPI_CK, if the SPI interface module has not received status packets from all functional modules, the SPI interface module sends data that cannot be identified as the feedback packet to the SPI master controller via the SPI_MISO signal line.

14. A method for writing mask data according to claim 12, characterized in that: After the SPI interface module sends the feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets sent by the SPI master controller through the SPI_MOSI signal line.

15. The method for writing mask data according to claim 12, characterized in that: The feedback packets are divided into success feedback packets and failure feedback packets. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is successful, the SPI interface module sends a success feedback packet through the SPI_MISO signal line. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is failure, the SPI interface module sends a failure feedback packet through the SPI_MISO signal line. The second identification field of the success feedback packet is different from the second identification field of the failure feedback packet.

16. A write mask command, characterized in that: The write mask command includes an address field, a data field, and a mask field. The write mask command is included in a command packet, the command packet includes one or more commands, at least one command is a write mask command, the command packet is transmitted and executed based on an interface system, the interface system includes a main controller, an interface module, and a functional module, the main controller is connected to the interface module, and the interface module is connected to the functional module, The main controller sends the command packet to the interface module. After receiving the command packet, the interface module sends the command packet to the functional module. After receiving the command packet, the functional module executes the command contained in the command packet. Executing the write mask command includes: writing the bits of the write mask command data field corresponding to the bits of the mask field in the write mask command that are 1 into the storage space pointed to by the write mask command address field.

17. A write mask command according to claim 16, characterized in that: After the function module executes the command included in the command package, the function module returns the status package to the interface module, including: when the result of the function module executing each command included in the command package is successful, the function module returns the status package with success information, when the result of the function module executing at least one command included in the command package is failure, the function module returns the status package with failure information, After receiving the status packet from the functional module, the interface module returns the status information of the status packet to the main controller.

18. A write mask command according to claim 17, characterized in that: The main controller is an I2C main controller, the interface module is an I2C interface module, and the I2C main controller is connected to the I2C interface module via an I2C clock line and an I2C data line.

19. A write mask command according to claim 18, characterized in that: The I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module. After receiving the command packet, the I2C interface module pulls down the I2C clock line level and sends the command packet to the functional module.

20. A write mask command according to claim 19, characterized in that: When the I2C interface module receives a status packet from the functional module and the status information of the status packet is successful, the I2C interface module stops pulling down the I2C clock line level and returns I2CACK to the I2C master controller. When the I2C interface module receives a status packet from the functional module and the status information of the status packet is failure, the I2C interface module stops pulling down the I2C clock line level and returns I2CNAK to the I2C master controller.

21. A write mask command according to claim 19, characterized in that: When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK or I2C NAK to the I2C master controller. If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns status information of the status packet to the I2C master controller.

22. A write mask command according to claim 18, characterized in that: After the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status packet to the I2C master controller after receiving the status packet from the functional module.

23. A write mask command according to claim 18, characterized in that: After the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is successful, then the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller, After the I2C interface module receives the command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is failure, the I2C interface module returns an I2C NAK to the I2C master controller.

24. A write mask command according to claim 18, characterized in that: The I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module, and then the I2C master controller initiates a subsequent I2C read operation to read the status information. After receiving the address byte of the subsequent I2C read operation, the I2C interface module pulls down the I2C clock line level and sends the received command packet to the functional module. After the function module executes the command contained in the command packet, it returns the status packet to the interface module. When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line level and returns the status information of the status packet to the I2C main controller.

25. A write mask command according to claim 17, characterized in that: The main controller is an SPI main controller, the interface module is an SPI interface module, and the SPI main controller is connected to the SPI interface module via an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line.

26. A write mask command according to claim 25, characterized in that: The SPI master controller generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module through the SPI_MOSI signal line, and the SPI interface module reads the command packet through the SPI_MOSI signal line, wherein the command packet starts with a first identification field. After the SPI interface module receives the status packet from the functional module, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sends a feedback packet to the SPI master controller through the SPI_MISO signal line, and the SPI master controller reads the feedback packet through the SPI_MISO signal line. The feedback packet starts with a second identification field, and the feedback packet includes the status information included in the status packet.

27. A write mask command according to claim 26, characterized in that: When the SPI master controller generates a clock edge on SPI_CK, if the SPI interface module has not received status packets from all functional modules, the SPI interface module sends data that cannot be identified as the feedback packet to the SPI master controller via the SPI_MISO signal line.

28. A write mask command according to claim 26, characterized in that: After the SPI interface module sends the feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets sent by the SPI master controller through the SPI_MOSI signal line.

29. A write mask command according to claim 26, characterized in that: The feedback packets are divided into success feedback packets and failure feedback packets. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is successful, the SPI interface module sends a success feedback packet through the SPI_MISO signal line. When the SPI interface module receives a status packet from the functional module and the status information contained in the status packet is failure, the SPI interface module sends a failure feedback packet through the SPI_MISO signal line. The second identification field of the success feedback packet is different from the second identification field of the failure feedback packet.

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