Grid control field sequence circuit and method

Abstract

The invention discloses a grid control field sequence circuit and method, and the circuit comprises M rows of sub-circuits, each sub-circuit comprises a compensation unit, and each compensation unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a pre-storage capacitor. A first source-drain electrode of the first transistor is coupled to a positive power line, and a second source-drain electrode of the first transistor is coupled to a second source-drain electrode of the second transistor and a first source-drain electrode of the third transistor; a first source drain electrode of the second transistor is coupled to a grid electrode of the third transistor and one end of the pre-storage capacitor; the second source electrode of the third transistor of the sub-circuit of the Nth row is coupled to the first source drain electrode of a fourth transistor, and the second source drain electrode of the fourth transistor is coupled to a data signal line. The beneficial effects of the invention are that the threshold voltage is written in advance by using the conduction characteristic of the transistor, thereby avoiding the image abnormity phenomenon caused by the drift of the threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a field sequence circuit and method for gate control. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] Due to the influence of transistor manufacturing process, the threshold voltage of driving transistors at different spatial locations is likely to be different. For a-Si, the threshold voltage of hydrogenated amorphous silicon transistors changes over time. Changes or inconsistencies in the threshold voltage of the driving transistor will cause uneven display of the LCD. In fact, due to the deviation of the transistor manufacturing process, it is inevitable that the threshold voltage of each driving transistor is different and there is a certain deviation.

[0004] Therefore, the present invention proposes a field sequential circuit and method for gate control to eliminate the influence of threshold voltage, thereby avoiding the influence of abnormal picture display. Summary of the invention

[0005] The purpose of the present invention is to provide a field sequence circuit and method for gate control, which can eliminate the influence of threshold voltage.

[0006] The object of the present invention is to realize a gate-controlled field sequential circuit through the following technical solution, comprising M rows of sub-circuits, wherein the sub-circuits include a compensation unit and a driving unit; The compensation unit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a pre-storage capacitor; The gate of the first transistor of the sub-circuit of the Nth row is coupled to the row gate signal line of the N-2th row, the first source and drain of the first transistor are coupled to the positive power line, and the second source and drain of the first transistor are coupled to the second source and drain of the second transistor and the first source and drain of the third transistor; The gate of the second transistor of the sub-circuit of the Nth row is coupled to the gate signal line of the N-1th row, the first source and drain of the second transistor are coupled to the gate of the third transistor and one end of the pre-storage capacitor, one end of the pre-storage capacitor and the other end of the pre-storage capacitor are coupled to the common signal line; The second source of the third transistor of the sub-circuit of the Nth row is coupled to the first source and drain of the fourth transistor, the second source and drain of the fourth transistor is coupled to the data signal line, and the gate of the fourth transistor is coupled to the row gate signal line of the Nth row; The second source and drain of the third transistor of the sub-circuit of the Nth row is also coupled to the driving unit; The M and N are positive integers, 3≤N≤M.

[0007] Further, the driving unit includes a sixth transistor and a pixel electrode; The gate of the sixth transistor is coupled to the transfer signal line, the first source and drain of the sixth transistor are coupled to the second source and drain of the second transistor, the second source and drain of the sixth transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to the common signal line.

[0008] Furthermore, the driving unit further includes a storage capacitor, one end of the storage capacitor is coupled to the second source and drain of the sixth transistor, and the other end of the storage capacitor is coupled to the common signal line.

[0009] Furthermore, the sub-circuit further includes a reset unit, the reset unit includes a fifth transistor, a first source and a drain of the fifth transistor are coupled to the driving unit, and a second source and a drain of the fifth transistor are coupled to the ground line.

[0010] Furthermore, the compensation unit also includes a seventh transistor, a gate of the seventh transistor is coupled to the transfer signal line, a first source and drain of the seventh transistor is coupled to the positive power line, and a second source and drain of the seventh transistor is coupled to the first source and drain of the third transistor.

[0011] Furthermore, the compensation unit also includes a seventh transistor, a gate of the seventh transistor is coupled to the second reset signal line, a first source and drain of the seventh transistor is coupled to the positive power line, and a second source and drain of the seventh transistor is coupled to the first source and drain of the second transistor.

[0012] The present invention also provides a gate-controlled field sequence circuit control method, comprising: In the backlight-on phase of the sub-circuit in row N: The row gate signal line of the N-2th row, the row gate signal line of the N-1th row and the row gate signal line of the Nth row are sequentially switched to high level, and the first transistor, the second transistor and the fourth transistor are sequentially turned on; The positive power line makes the second node high level through the first transistor, and charges the pre-storage capacitor through the second transistor, so that the first node is maintained at a high level; The fourth transistor is turned on, and the data signal line passes through the fourth transistor so that the potential of the third node is the data signal voltage; The third transistor is turned on and reaches a saturation state, and the charge in the pre-storage capacitor and the potential of the first node are discharged to the sum of the data signal voltage and the threshold voltage; The row gate signal line of the N-2th row, the row gate signal line of the N-1th row and the row gate signal line of the Nth row are sequentially switched to low level, and the first transistor, the second transistor and the fourth transistor are sequentially turned off; In the backlight off phase of the sub-circuit in row N: The reset signal line jumps to a high level, the fifth transistor is turned on, and the ground line resets the pixel electrode through the fifth transistor; After the reset is completed, the reset signal line jumps to a low level, and the fifth transistor is turned off; The transfer signal line jumps to a high level, the seventh transistor and the sixth transistor are turned on, and the positive power line makes the second node a high potential through the seventh transistor. The third transistor is turned on to a saturation state, the potential difference between the third node and the first node is the threshold voltage of the third transistor, the potential of the third node is the data signal voltage, and the data signal voltage is written into the pixel electrode through the sixth transistor.

[0013] The present invention has the following advantages: The present invention sets a compensation unit, stores a high potential in advance through a pre-storage capacitor, so that the gate of the third transistor is at a high potential, and then continuously inputs a data signal voltage through the fourth transistor, maintains the potential of the third node as the data signal voltage, makes the potential difference between the first node and the third node as the threshold voltage of the third transistor, and pre-writes the potential of the pre-storage capacitor and the first node into the sum of the data signal voltage and the threshold voltage; when writing the pixel voltage to the pixel electrode, since the data signal voltage and the threshold voltage are pre-stored in the pre-storage capacitor, the third transistor is again saturated, so that the potential of the third node is the data signal voltage, and since the threshold voltage is pre-compensated in the pre-storage capacitor, the influence of the threshold voltage can be eliminated after the conduction, and the influence of the data signal writing into the pixel electrode is reduced, thereby avoiding the abnormal screen display caused by the uneven process in the surface and the threshold voltage drift of the transistor over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit diagram of Embodiment 1 of the present invention; Figure 2 is a timing diagram of the first embodiment of the present invention; Figure 3 is a circuit diagram of Embodiment 2 of the present invention; Figure 4 This is a timing diagram of the second embodiment of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0016] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0018] See also Figure 1 The present invention provides a gate-controlled field sequential circuit, which is Embodiment 1. Embodiment 1 includes M rows of sub-circuits, and the sub-circuits include a compensation unit and a driving unit; the compensation unit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a pre-storage capacitor Cst1 and a seventh transistor M7; M and N are positive integers, 3≤N≤M; The gate of the first transistor M1 of the sub-circuit of the Nth row is coupled to the row gate signal line ScanN-2 of the N-2th row, the first source and drain of the first transistor M1 are coupled to the positive power line Vdd, and the second source and drain of the first transistor M1 are coupled to the second source and drain of the second transistor M2 and the first source and drain of the third transistor M3; The gate of the second transistor M2 of the sub-circuit of the Nth row is coupled to the gate signal line ScanN-1 of the N-1th row, the first source and drain of the second transistor M2 are coupled to the gate of the third transistor M3 and one end of the pre-storage capacitor Cst1, one end of the pre-storage capacitor Cst1, and the other end of the pre-storage capacitor Cst1 is coupled to the common signal line Com; The second source of the third transistor M3 of the sub-circuit of the Nth row is coupled to the first source and drain of the fourth transistor M4, the second source and drain of the fourth transistor M4 is coupled to the data signal line Data, and the gate of the fourth transistor M4 is coupled to the row gate signal line ScanN of the Nth row; the second source and drain of the third transistor M3 of the sub-circuit of the Nth row is also coupled to the driving unit; A gate of the seventh transistor M7 is coupled to the transfer signal line Tran, a first source and drain of the seventh transistor M7 is coupled to the positive power line Vdd, and a second source and drain of the seventh transistor M7 is coupled to a first source and drain of the third transistor M3.

[0019] Further, the driving unit includes a sixth transistor M6, a pixel electrode Clc and a storage capacitor Cst2; the gate of the sixth transistor M6 is coupled to the transfer signal line Tran, the first source and drain of the sixth transistor M6 are coupled to the second source and drain of the second transistor M2, the second source and drain of the sixth transistor M6 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the sixth transistor M6, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0020] Furthermore, the sub-circuit further includes a reset unit, the reset unit includes a fifth transistor T5, a first source and a drain of the fifth transistor M5 are coupled to the driving unit, and a second source and a drain of the fifth transistor M5 are coupled to the ground line Vss.

[0021] In operation, the timing of the subcircuit is configured as follows Figure 2 As shown, in the backlight-on stage of the sub-circuit in row N: The row gate signal line ScanN-2 of the N-2th row, the row gate signal line ScanN-1 of the N-1th row, and the row gate signal line ScanN of the Nth row are sequentially switched to high level, and the first transistor M1, the second transistor M2, and the fourth transistor M4 are sequentially turned on; The positive power line Vdd makes the second node B high level through the first transistor M1, that is, VB=Vdd; At the same time, the positive power line Vdd charges the pre-storage capacitor Cst1 through the second transistor M2, so that the first node A is maintained at a high level; The pre-storage capacitor Cst1 maintains the first node A at a high potential, that is, VA=Vdd; The fourth transistor M4 is turned on, and the data signal line Data passes through the fourth transistor M4 so that the potential of the third node C is the data signal voltage Vdata, that is, VC=Vdata; At this time, the gate and the first source and drain of the third transistor M3 are both at the high potential Vdd, and the second source and drain of the third transistor M3 is the data signal voltage Vdata, so the third transistor M3 is turned on, and the third node C is continuously maintained at the data signal voltage Vdata. When the third transistor M3 is in the bottom saturation state, the first node A is discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the third transistor M3, that is, VA=Vdata+Vth, and the charge in the pre-storage capacitor Cst1 is Vdata+Vth; After the data signal voltages and threshold voltages of all rows are written into the pre-storage capacitors of the corresponding rows, the row gate signal line ScanN-2 of the N-2th row, the row gate signal line ScanN-1 of the N-1th row, and the row gate signal line ScanN of the Nth row are sequentially switched to low levels, and the first transistor M1, the second transistor M2, and the fourth transistor M4 are sequentially turned off; In the backlight on stage, the third transistor M3 is used to change the state of the transistor by turning on and off the first transistor M1, the second transistor M2 and the fourth transistor M4, so as to extract the threshold voltage Vth of the third transistor M3 and write it into the pre-storage capacitor Cst1, thereby pre-compensating the threshold voltage Vth.

[0022] In the backlight off phase of the sub-circuit in row N: The reset signal line Reset jumps to a high level, the fifth transistor M5 is turned on, and the ground line Vss resets the pixel electrode Clc through the fifth transistor M5; After the reset is completed, the reset signal line Reset jumps to a low level, and the fifth transistor M5 is turned off; The transfer signal line Tran jumps to a high level, and the seventh transistor M7 and the sixth transistor M6 are turned on; The positive power line Vdd makes the potential of the second node B high through the seventh transistor M7, at this time VB=Vdd; The pre-storage capacitor Cst1 is pre-written with the charge of the data signal voltage Vdata and the threshold voltage Vth in the backlight-on stage, so that the potential of the first node A is maintained at VA=Vdata+Vth, and the third transistor M3 reaches the saturation state again. At this time, the potential of the third node C is the data signal voltage Vdata when it is turned off, that is, VC=Vdata; The sixth transistor M6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor M6.

[0023] In this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor M3 and the sixth transistor M6, so that the pixel voltage Vpixel=Vdata; by utilizing the voltage difference characteristics of the gate and the source and drain when the third transistor M3 is in the saturation state, it is offset with the pre-compensated threshold voltage Vth, thereby avoiding the influence of the threshold voltage change.

[0024] The present invention sets a compensation unit and uses the law of charge conservation to stabilize the potential of the first node A at Vdd; the sum of the potential of the second node B is maintained at Vdata through the data signal line Data, and the saturation and cut-off voltage characteristics of the third transistor M3 are used to discharge the first node A when the third transistor M3 reaches saturation, so that the transistor is stabilized in a saturated state. At this time, VA=Vdata+Vth, and the threshold voltage of the third transistor M3 is pre-written into the first node A for storage, so as to offset the threshold voltage Vth when the voltage of the pixel electrode Clc is subsequently written; When writing, the saturation discharge characteristics of the transistor are used again. At this time, VB=Vdd, VA=Vdata+Vth, so VC=Vdata when stable. This eliminates the influence of the threshold voltage Vth on the writing of the data signal into the pixel electrode, thereby avoiding abnormal screen display caused by uneven in-plane process and drift of the threshold voltage Vth of the transistor over time. Example

[0025] like Figure 3 As shown, the second embodiment is a gate-controlled field sequential circuit, including M rows of sub-circuits, and the compensation unit includes a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, a pre-storage capacitor Cst1 and a seventh transistor M7; A gate of the seventh transistor M7 is coupled to the second reset signal line Reset2, a first source and drain of the seventh transistor M7 is coupled to the positive power line Vdd, and a second source and drain of the seventh transistor M7 is coupled to the first source and drain of the second transistor M2; The first source and drain of the first transistor M1 are coupled to the positive power supply line Vdd, the gate of the first transistor M1 is coupled to the transfer signal line Tran, and the second source and drain of the first transistor M1 are coupled to the second source and drain of the second transistor M2; the gate of the second transistor M2 is coupled to the gate signal line ScanN-1 of the N-1th row, the first source and drain of the second transistor M2 are also coupled to one end of the pre-storage capacitor Cst1, and the other end of the pre-storage capacitor Cst1 is coupled to the common signal line Com; the second source and drain of the first transistor M1 are also coupled to the first source and drain of the third transistor M3, the gate of the third transistor M3 is coupled to one end of the pre-storage capacitor Cst1, the second source and drain of the third transistor M3 are coupled to the first source and drain of the fourth transistor M4, the gate of the fourth transistor M4 is coupled to the row gate signal line ScanN of the Nth row, and the second source and drain of the fourth transistor M4 are coupled to the data signal line Data.

[0026] In operation, the timing of the subcircuit is configured as follows Figure 4 As shown, in the backlight-on stage of the sub-circuit in row N: The second reset signal line Reset2, the row gate signal line ScanN-1 of the N-1th row, and the row gate signal line ScanN of the Nth row are sequentially switched to high level, and the seventh transistor M7, the second transistor M2, and the fourth transistor M4 are sequentially turned on; The positive power line Vdd pre-writes a high potential into the pre-storage capacitor Cst1 through the seventh transistor M7, so that the first node A is at a high level, that is, VA=Vdd; At the same time, the positive power line Vdd maintains the second node B at a high level through the second transistor M2, that is, VB=Vdd; The fourth transistor M4 is turned on, and the data signal line Data passes through the fourth transistor M4 so that the potential of the third node C is the data signal voltage Vdata, that is, VC=Vdata; At this time, the gate and the first source and drain of the third transistor M3 are both at the high potential Vdd, and the second source and drain of the third transistor M3 is the data signal voltage Vdata, so the third transistor M3 is turned on, and the third node C is continuously maintained at the data signal voltage Vdata. When the third transistor M3 is in the bottom saturation state, the first node A is discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the third transistor M3, that is, VA=Vdata+Vth, and the charge in the pre-storage capacitor Cst1 is also Vdata+Vth; After the data signal voltages and threshold voltages of all rows are written into the pre-storage capacitors of the corresponding rows, the second reset signal line Reset2, the row gate signal line ScanN-1 of the N-1th row, and the row gate signal line ScanN of the Nth row are sequentially switched to low levels, and the seventh transistor M7, the second transistor M2, and the fourth transistor M4 are sequentially turned off; In the backlight-on stage, the third transistor M3 is used to extract the threshold voltage of the third transistor M3 and pre-write it into the pre-storage capacitor Cst1, thereby pre-compensating the threshold voltage Vth.

[0027] In the backlight off phase of the sub-circuit in row N: The reset signal line Reset jumps to a high level, the fifth transistor M5 is turned on, and the ground line Vss resets the pixel electrode Clc through the fifth transistor M5; After the reset is completed, the reset signal line Reset jumps to a low level, and the fifth transistor M5 is turned off; The transfer signal line Tran jumps to a high level, and the first transistor M1 and the sixth transistor M6 are turned on; The positive power line Vdd makes the potential of the second node B high through the first transistor M1, at this time VB=Vdd; The pre-storage capacitor Cst1 is pre-written with the charge of the data signal voltage Vdata and the threshold voltage Vth in the backlight-on stage, so that the potential of the first node A is maintained at VA=Vdata+Vth, and the third transistor M3 reaches the saturation state again. At this time, the potential of the third node C is the data signal voltage Vdata when it is turned off, that is, VC=Vdata; The sixth transistor M6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor M6.

[0028] In this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor M3 and the sixth transistor M6, so that the pixel voltage Vpixel=Vdata; by utilizing the voltage characteristics of the gate and the source and drain when the third transistor M3 is in the saturation state, it is offset with the pre-compensated threshold voltage Vth, thereby avoiding the influence of the change of the threshold voltage Vth.

[0029] This embodiment provides another circuit structure. Example

[0030] The third embodiment is a gate-controlled field sequence circuit control method.

[0031] In the backlight-on phase of the sub-circuit in row N: The row gate signal line ScanN-2 of the N-2th row, the row gate signal line ScanN-1 of the N-1th row, and the row gate signal line ScanN of the Nth row are sequentially switched to high level, and the first transistor M1, the second transistor M2, and the fourth transistor M4 are sequentially turned on; The positive power line Vdd makes the second node B high level through the first transistor M1, that is, VB=Vdd; At the same time, the positive power line Vdd charges the pre-storage capacitor Cst1 through the second transistor M2, so that the first node A is maintained at a high level; The pre-storage capacitor Cst1 maintains the first node A at a high potential, that is, VA=Vdd; The fourth transistor M4 is turned on, and the data signal line Data passes through the fourth transistor M4 so that the potential of the third node C is the data signal voltage Vdata, that is, VC=Vdata; At this time, the gate and the first source and drain of the third transistor M3 are both at the high potential Vdd, and the second source and drain of the third transistor M3 is the data signal voltage Vdata, so the third transistor M3 is turned on, and the third node C is continuously maintained at the data signal voltage Vdata. When the third transistor M3 is in the bottom saturation state, the first node A is discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the third transistor M3, that is, VA=Vdata+Vth, and the charge in the pre-storage capacitor Cst1 is also Vdata+Vth; After the data signal voltages and threshold voltages of all rows are written into the pre-storage capacitors of the corresponding rows, the row gate signal line ScanN-2 of the N-2th row, the row gate signal line ScanN-1 of the N-1th row, and the row gate signal line ScanN of the Nth row are sequentially switched to low levels, and the first transistor M1, the second transistor M2, and the fourth transistor M4 are sequentially turned off; In the backlight on stage, the third transistor M3 is used to change the state of the transistor by turning on and off the first transistor M1, the second transistor M2 and the fourth transistor M4, so as to extract the threshold voltage of the third transistor M3 and write it into the pre-storage capacitor Cst1, thereby pre-compensating the threshold voltage Vth.

[0032] In the backlight off phase of the sub-circuit in row N: The reset signal line Reset jumps to a high level, the fifth transistor M5 is turned on, and the ground line Vss resets the pixel electrode Clc through the fifth transistor M5; After the reset is completed, the reset signal line Reset jumps to a low level, and the fifth transistor M5 is turned off; The transfer signal line Tran jumps to a high level, and the seventh transistor M7 and the sixth transistor M6 are turned on; The positive power line Vdd makes the potential of the second node B high through the seventh transistor M7, at this time VB=Vdd; The pre-storage capacitor Cst1 is pre-written with the charge of the data signal voltage Vdata and the threshold voltage Vth in the backlight-on stage, so that the potential of the first node A is maintained at VA=Vdata+Vth, and the third transistor M3 reaches the saturation state again. At this time, the potential of the third node C is the data signal voltage Vdata when it is turned off, that is, VC=Vdata; The sixth transistor M6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor M6.

[0033] In this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor M3 and the sixth transistor M6, so that the pixel voltage Vpixel=Vdata; by utilizing the voltage characteristics of the gate and the source and drain when the third transistor M3 is in the saturation state, it is offset with the pre-compensated threshold voltage Vth, thereby avoiding the influence of the threshold voltage change.

[0034] This embodiment is used for the first embodiment and the deformation circuit of the first embodiment, and its beneficial effects are the same as those of the first embodiment.

[0035] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A gate-controlled field sequential circuit, characterized in that: comprising M rows of sub-circuits, wherein the sub-circuits include a compensation unit and a driving unit; The compensation unit includes a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4) and a pre-storage capacitor (Cst1); The gate of the first transistor (M1) of the sub-circuit of the Nth row is coupled to the row gate signal line (ScanN-2) of the N-2th row, the first source and drain of the first transistor (M1) are coupled to the positive power line (Vdd), and the second source and drain of the first transistor (M1) are coupled to the second source and drain of the second transistor (M2) and the first source and drain of the third transistor (M3); The gate of the second transistor (M2) of the sub-circuit of the Nth row is coupled to the gate signal line (ScanN-1) of the N-1th row, the first source and drain of the second transistor (M2) are coupled to the gate of the third transistor (M3) and one end of the pre-storage capacitor (Cst1), and the other end of the pre-storage capacitor (Cst1) is coupled to the common signal line (Com); The second source of the third transistor (M3) of the sub-circuit of the Nth row is coupled to the first source and drain of the fourth transistor (M4), the second source and drain of the fourth transistor (M4) is coupled to the data signal line (Data), and the gate of the fourth transistor (M4) is coupled to the row gate signal line (ScanN) of the Nth row; The second source and drain of the third transistor (M3) of the sub-circuit of the Nth row is also coupled to the driving unit; The M and N are positive integers, 3≤N≤M.

2. A gate-controlled field sequential circuit according to claim 1, characterized in that: The driving unit includes a sixth transistor (M6) and a pixel electrode (Clc); The gate of the sixth transistor (M6) is coupled to the transfer signal line (Tran), the first source and drain of the sixth transistor (M6) are coupled to the second source and drain of the second transistor (M2), the second source and drain of the sixth transistor (M6) are coupled to the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

3. A gate-controlled field sequential circuit according to claim 2, characterized in that: The driving unit further includes a storage capacitor (Cst2), one end of the storage capacitor (Cst2) is coupled to the second source and drain of the sixth transistor (M6), and the other end of the storage capacitor (Cst2) is coupled to the common signal line (Com).

4. The gate-controlled field sequential circuit according to claim 1, characterized in that: The sub-circuit further includes a reset unit, which includes a fifth transistor (M5), a first source and a drain of the fifth transistor (M5) coupled to the driving unit, and a second source and a drain of the fifth transistor (M5) coupled to a ground line (Vss).

5. A gate-controlled field sequential circuit according to any one of claims 1 or 2 or 3 or 4, characterized in that: The compensation unit also includes a seventh transistor (M7), a gate of the seventh transistor (M7) is coupled to a transfer signal line (Tran), a first source and drain of the seventh transistor (M7) is coupled to a positive power line (Vdd), and a second source and drain of the seventh transistor (M7) is coupled to a first source and drain of the third transistor (M3).

6. A gate-controlled field sequential circuit according to any one of claims 1 or 2 or 3 or 4, characterized in that: The compensation unit also includes a seventh transistor (M7), a gate of the seventh transistor (M7) is coupled to a second reset signal line (Reset2), a first source and drain of the seventh transistor (M7) is coupled to a positive power line (Vdd), and a second source and drain of the seventh transistor (M7) is coupled to a first source and drain of the second transistor (M2).

7. A gate-controlled field sequence circuit control method, applied to any field sequence circuit according to claim 1 to claim 5, characterized in that: include: In the backlight-on phase of the sub-circuit in row N: The row gate signal line (ScanN-2) of the N-2th row, the row gate signal line (ScanN-1) of the N-1th row, and the row gate signal line (ScanN) of the Nth row are sequentially switched to high level, and the first transistor (M1), the second transistor (M2), and the fourth transistor (M4) are sequentially turned on; The positive power line (Vdd) makes the second node (B) high level through the first transistor (M1), and charges the pre-storage capacitor (Cst1) through the second transistor (M2), so that the first node (A) is maintained at a high level; The data signal line (Data) makes the potential of the third node (C) the data signal voltage through the fourth transistor (M4); The third transistor (M3) is turned on and reaches a saturation state, and the charge in the pre-storage capacitor (Cst1) and the potential of the first node (A) are discharged to the sum of the data signal voltage and the threshold voltage of the third transistor (M3); The row gate signal line (ScanN-2) of the N-2th row, the row gate signal line (ScanN-1) of the N-1th row, and the row gate signal line (ScanN) of the Nth row are sequentially switched to low level, and the first transistor (M1), the second transistor (M2), and the fourth transistor (M4) are sequentially turned off; In the backlight off phase of the sub-circuit in row N: The reset signal line (Reset) jumps to a high level, the fifth transistor (M5) is turned on, and the ground line (Vss) resets the pixel electrode (Clc) through the fifth transistor (M5); After the reset is completed, the reset signal line (Reset) jumps to a low level, and the fifth transistor (M5) is turned off; The transfer signal line (Tran) jumps to a high level, the seventh transistor (M7) and the sixth transistor (M6) are turned on, and the positive power line (Vdd) makes the second node (B) a high potential through the seventh transistor (M7). The third transistor (M3) is turned on to a saturation state, the potential difference between the third node (C) and the first node (A) is the threshold voltage of the third transistor (M3), the potential of the third node (C) is the data signal voltage, and the data signal voltage is written into the pixel electrode (Clc) through the sixth transistor (M6).

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