Method and system for measuring pulse width

Abstract

The invention provides a method and a system for measuring pulse width. The method comprises the following steps of: inputting a pulse to be measured into a delay chain; if the pulse to be measured is a negative pulse, directly inputting the pulse to be measured into the delay chain; if the to-be-measured pulse is a positive pulse, inverting the to-be-measured pulse and inputting the to-be-measured pulse into the delay chain; a pulse to be measured is output in a delay chain through a plurality of taps in sequence in a delay manner, and an output signal of each tap of the delay chain is input to the corresponding two-stage D flip-flop; if the to-be-detected pulse output by a certain tap has a negative pulse signal, the corresponding two-stage D trigger outputs a high level; otherwise, outputting a low level; counting the number M of the two stages of D triggers outputting high level, and taking the sum of the reduced widths of negative pulses caused by the delay time of the first M taps on the delay chain propagation path as the width of the negative pulses; wherein M is a positive integer. The pulse compression technology is adopted, the dead time is short, and the resolution ratio is high.

Description

Technical Field

[0001] The invention belongs to the technical field of time-to-digital converters, and in particular relates to a pulse width measurement method and system. Background Art

[0002] Pulse width measurement is a technique for converting the width of a pulse into visual data. It is widely used in high-energy physics experiments, laser radar and other technical fields. In addition, pulse width measurement can be used as part of the design of a time-to-digital converter (TDC) in the field of time measurement.

[0003] In the early days, time-to-digital converters (TDCs) were usually designed based on ASICs, which had the problems of high development costs, long development cycles, and inflexible designs. In recent years, FPGA-based TDCs have gradually become the focus due to their short development cycles, low development costs, and easy updates. FPGA-based TDCs are usually composed of coarse counters and fine counters. The coarse counters are usually implemented by counters and can calculate the time intervals that are integer multiples of the clock cycle, while the fine counters can calculate the time intervals that are less than the clock cycle.

[0004] There are many ways to implement a fine counter, among which converting the time interval shorter than the clock period into a pulse of a certain width for measurement is an extremely important method.

[0005] Due to the limitations of FPGA structure and process, the existing technology has limitations in terms of accuracy and efficiency for pulse width measurement, which leads to poor time measurement accuracy of time-to-digital converter (TDC). Therefore, developing a low dead time and high resolution pulse measurement method is an important design direction for FPGA-based TDC. Summary of the invention

[0006] The purpose of the present invention is to solve the deficiencies of the above-mentioned background technology and to provide a pulse width measurement method and system, which adopts pulse compression technology, has less dead time and high resolution.

[0007] The technical solution adopted by the present invention is: a method for measuring pulse width, comprising the following steps:

[0008] Input the pulse to be tested into the delay chain; if the pulse to be tested is a negative pulse, it is directly input into the delay chain; if the pulse to be tested is a positive pulse, it is inverted and then input into the delay chain;

[0009] The pulse to be tested is outputted in the delay chain in sequence through multiple taps with delayed output, and the output signal of each tap of the delay chain is inputted into the corresponding two-stage D flip-flop; if the pulse to be tested outputted by a tap has a negative pulse signal, the corresponding two-stage D flip-flop outputs a high level; otherwise, it outputs a low level;

[0010] The number M of two-stage D flip-flops that output high level is counted, and the sum of the widths of the negative pulses reduced by the delay times of the first M taps on the delay chain propagation path is taken as the width of the negative pulse; wherein M is a positive integer.

[0011] The above technical solution also includes the following steps: if the number of two-stage D flip-flops outputting high level is the same as the number of taps in the delay chain, it is determined that the range is exceeded and a measurement failure is output.

[0012] In the above technical solution, the two-stage D flip-flop includes a first-stage flip-flop and a second-stage flip-flop;

[0013] After the rising edge of the negative pulse is triggered, the first-stage trigger transmits the continuously input high level to the second-stage trigger; the second-stage trigger outputs a high level under the sampling of the sampling clock;

[0014] When the first-stage trigger is not triggered, the first-stage trigger does not output a high level to the second-stage trigger, and the second-stage trigger outputs a low level.

[0015] In the above technical solution, before the pulse to be tested is input into the delay chain, the width of the negative pulse reduction caused by each tap delay time is first obtained:

[0016] The test pulses are continuously input into the delay chain at a fixed period and a set number; the test pulses are negative pulses with randomly and evenly distributed pulse widths;

[0017] Count the number N of two-stage D flip-flops that output high level in each cycle;

[0018] Count the number of times each high level quantity appears;

[0019] Each tap is numbered in order from small to large according to the propagation path of the delay chain; the value range of the tap number is [1, N], where N is the number of taps;

[0020] For any tap, the ratio of the number of high levels with the same tap number to the set number of negative pulse inputs multiplied by the upper limit of the ideal width of the negative pulse is taken as the reduced width of the negative pulse caused by the delay time of the tap.

[0021] In the above technical solution, the test pulse generation process includes: inputting a set first period signal to the SET terminal of a D flip-flop, inputting a set clock signal to the CLK terminal of the D flip-flop, and inputting a set second period signal to the D terminal of the D flip-flop; the Q terminal of the D flip-flop outputs a negative pulse with a randomly uniformly distributed pulse width;

[0022] The first periodic signal has the same period as the clock signal; the pulse width of the first periodic signal is smaller than the pulse width of the clock signal, and the difference between the two is greater than the estimated upper limit of the width measurement of the pulse to be measured;

[0023] The second period signal is used to set the period of the negative pulse.

[0024] The present invention also provides a pulse width measurement system, comprising an inverter, a delay chain, a two-stage D flip-flop and a signal processing module; each tap of the delay chain is respectively connected to a corresponding two-stage D flip-flop,

[0025] If the pulse to be measured is a negative pulse, it is directly input into the delay chain; if the pulse to be measured is a positive pulse, it is inverted by the inverter and then input into the delay chain;

[0026] The delay chain is used to receive the pulse to be tested. The pulse to be tested is outputted in the delay chain in sequence through multiple taps with delayed output. The output signal of each tap of the delay chain is inputted into the corresponding two-stage D flip-flop. If the pulse to be tested outputted by a tap has a negative pulse signal, the corresponding two-stage D flip-flop outputs a high level; otherwise, it outputs a low level.

[0027] The signal processing module is used to count the number M of two-stage D flip-flops that output high levels, and output the sum of the reduced widths of negative pulses caused by the delay times of the first M taps on the delay chain propagation path as the width of the negative pulse; where M is a positive integer.

[0028] In the above technical solution, if the signal processing module determines that the number of two-stage D flip-flops outputting high level is the same as the number of taps in the delay chain, it determines that the measurement range is exceeded and outputs a conclusion of measurement failure.

[0029] In the above technical solution, the two-stage D flip-flop includes a first-stage flip-flop and a second-stage flip-flop; the clock end of the first-stage flip-flop is connected to the corresponding tap, and the D end of the first-stage flip-flop is connected to a continuous high level; the Q end of the first-stage flip-flop is connected to the D end of the second-stage flip-flop; the clock end of the second-stage flip-flop is connected to the sampling clock; the Q end output of the second-stage flip-flop is used as the output of the two-stage D flip-flop.

[0030] In the above technical solution, the delay chain is composed of a plurality of programmable logic unit structures cascaded.

[0031] In the above technical solution, each programmable logic unit structure includes four pairs of Dual LUTs and one Lookahead8; in each pair of Dual LUTs, the output of the O6 signal terminal of the upper LUT is used as the input of the lower LUT, and the output of the O5 and O6 signal terminals of the upper LUT is used as the input of Lookahead8; except for the last pair of Dual LUTs, the last level output of Lookahead8 corresponding to any pair of Dual LUTs is used as the input of the upper LUT in the next pair of Dual LUTs; the input of the programmable logic unit structure is used as the input of the upper LUT and the Lookahead8 in the first pair of Dual LUTs; the last level output of Lookahead8 is used as the input of the next programmable logic unit structure; each output of Lookahead8 is used as a separate tap output.

[0032] The beneficial effects of the present invention are as follows: the present invention adopts the calculation pulse compression technology, has less dead time and high resolution, and utilizes the different propagation speeds of the rising edge and the falling edge of the negative pulse in the delay chain to reversely infer the pulse width. The present invention accurately determines the disappearance time of the pulse by observing the characteristic that the negative pulse gradually narrows as it propagates in the delay chain, reverses the original width of the negative pulse, and realizes the accurate measurement of the signal width. The present invention has a wide range of applications, and can not only directly measure the width of the negative pulse, but also use the system to measure the pulse width of the positive pulse by adding an inverter. The present invention can calculate the width of the negative pulse based on the number distribution of high levels and the reduced width of the negative pulse caused by each tap delay time. The calculation method is simple and efficient, and the calculation cost is saved while ensuring the calculation accuracy of the negative pulse.

[0033] Furthermore, the present invention takes into account that when all two-stage D flip-flops output high levels, it is difficult to distinguish whether the width of the pulse to be measured exceeds the measuring range. Therefore, if the number of two-stage D flip-flops outputting high levels is the same as the number of taps in the delay chain, it is determined that the measuring range is exceeded and the measurement failure is output, thereby effectively ensuring the measurement accuracy.

[0034] Furthermore, the present invention realizes that the output high and low levels of the two-stage D flip-flops reflect different pulse signal inputs through a reasonable connection method of the two-stage D flip-flops, and then the initial pulse of the negative pulse can be known by simply observing the output values ​​of the Q terminals of several second-stage flip-flops, which effectively simplifies the process of pulse width measurement.

[0035] Furthermore, the present invention cascades the small delay chains in multiple programmable logic unit structures CLB to eventually form a long chain that can be continuously expanded. This long chain can support different widths of negative pulses to be measured in a wide range, meeting the needs of high-precision time measurement.

[0036] Furthermore, the programmable logic unit structure of the present invention includes four pairs of Dual LUTs and one Lookahead8, which utilize the unique logic units and structures of the Versal series FPGA to form a small delay chain with 16 delays and taps, and then achieve high-precision negative pulse width measurement through cascading. The time measurement range of the system design can reach 10ns, and the resolution is close to 1.5ps, which is suitable for various application scenarios that require high-precision time measurement.

[0037] Furthermore, the present invention proposes a method for measuring the width of a negative pulse reduced by the delay time of a delay chain tap. Based on the variation law of a negative pulse with randomly and uniformly distributed pulse width in the delay chain, the width of the negative pulse reduced by the delay time of a single tap is accurately calculated by observing the output law of a two-stage D trigger corresponding to each tap, thereby effectively improving the calculation accuracy of the negative pulse width.

[0038] Furthermore, the present invention proposes a method and system for generating negative pulses with randomly and evenly distributed pulse widths, which is simple and efficient, while ensuring that the generated negative pulses meet set requirements.

[0039] Furthermore, the present invention can effectively measure the negative pulse directly input from the outside, and the time required for one measurement is short. The system provided by the present invention can also perform continuous measurement, and the system can also be applied to the design of TDC (time to digital converter). BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of the principle of the present invention;

[0041] Figure 2 It is a schematic diagram of the cascade of the delay chain in a specific embodiment;

[0042] Figure 3 It is a schematic diagram of the principle of the delay chain in a specific embodiment;

[0043] Figure 4 It is a schematic diagram of negative pulse boundary processing in a specific embodiment;

[0044] Figure 5 It is a schematic diagram of generating negative pulses with randomly and evenly distributed pulse widths in a specific embodiment;

[0045] Figure 6 Schematic diagram for testing the reduced width of a negative pulse caused by the delay time of a single tap in the delay chain. DETAILED DESCRIPTION

[0046] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments to facilitate a clear understanding of the present invention, but they do not constitute a limitation on the present invention.

[0047] Example 1

[0048] like Figure 1-4 As shown, the present invention provides a method for measuring pulse width, comprising the following steps:

[0049] Input the pulse to be tested into the delay chain; if the pulse to be tested is a negative pulse, it is directly input into the delay chain; if the pulse to be tested is a positive pulse, it is inverted and then input into the delay chain;

[0050] The pulse to be tested is outputted in the delay chain in sequence through multiple taps with delayed output, and the output signal of each tap of the delay chain is inputted into the corresponding two-stage D flip-flop; if the pulse to be tested outputted by a tap has a negative pulse signal, the corresponding two-stage D flip-flop outputs a high level; otherwise, it outputs a low level;

[0051] Count the number of two-stage D flip-flops M that output high level, and take the sum of the widths of the negative pulses reduced by the delay times of the first M taps on the delay chain propagation path as the width of the negative pulse; wherein M is a positive integer;

[0052] If the number of two-stage D flip-flops that output high levels is the same as the number of taps in the delay chain, it is determined that the range is exceeded and the measurement failure is output.

[0053] Specifically, when all two-stage D flip-flops output high levels, it is difficult to tell whether the width of the pulse to be measured exceeds the measurement range. Therefore, if the number of two-stage D flip-flops outputting high levels is the same as the number of taps in the delay chain, it is determined to be out of range and the measurement failure is output.

[0054] like Figure 1 As shown in the figure, the pulse width measurement system block diagram based on the Versal series FPGA proposed by the present invention is composed of a delay chain with a tap and a two-stage D flip-flop. All modules in the figure are implemented in the form of firmware inside the FPGA. The present invention only inputs one pulse signal to be measured at a time within a set period. If the pulse signal to be measured is a positive pulse, it is converted into a negative pulse to ensure that the delay chain receives only negative pulse signals.

[0055] A delay chain is a specific circuit design that provides a uniform delay path. When a signal enters the delay chain, an output signal is generated at each tap (i.e., output point). The delay chain inputs a negative pulse signal, and in theory, the signal output by each tap of the delay chain should also be a negative pulse, but the output of each tap will have a certain delay compared to the previous one.

[0056] However, the actual situation is that when the negative pulse propagates in the delay chain, its pulse width will gradually narrow and may eventually disappear, leaving only a high level. The present invention takes advantage of this phenomenon and creates a method and system for measuring the width of a negative pulse. In this specific embodiment, due to the use of the Versal series FPGA, the average delay of each delay unit in the delay chain is approximately 30 picoseconds (ps), but by monitoring the width change of the negative pulse, the accuracy of the negative pulse width measurement can be improved to about 1.5 picoseconds. In other words, after a 30 picosecond delay of a single delay unit, the width of the negative pulse will be reduced by approximately 1.5 picoseconds.

[0057] The core idea of ​​the present invention is to utilize the characteristic that the pulse width gradually decreases when the negative pulse propagates in the delay chain, and use a two-stage D trigger to determine at which tap position in the chain the negative pulse disappears, and finally reversely infer based on the position of the tap to determine the initial width of the negative pulse entering the delay chain.

[0058] In this specific embodiment, the delay link must wait 400ns after receiving the input signal before receiving the negative pulse again. The 400ns takes into account that if the negative pulse to be tested is very long (the longest that can be measured here is 10ns), it will take a certain amount of time to get the test result. The 400ns is a manually set parameter. The Versal series FPGA used in this specific embodiment is sufficient to ensure that the measured negative pulse width range is 0-10ns.

[0059] The two-stage D flip-flop includes a first-stage flip-flop and a second-stage flip-flop; the clock end of the first-stage flip-flop is connected to the corresponding tap, and the D end of the first-stage flip-flop is connected to a continuous high level; the Q end of the first-stage flip-flop is connected to the D end of the second-stage flip-flop; the clock end of the second-stage flip-flop is connected to a sampling clock; the Q end output of the second-stage flip-flop is used as the output of the two-stage D flip-flop.

[0060] like Figure 1 As shown, after the rising edge of the negative pulse is triggered, the first-stage trigger transmits the continuously input high level to the second-stage trigger; the second-stage trigger outputs a high level under the sampling of the sampling clock;

[0061] When the first-stage trigger is not triggered, the first-stage trigger does not output a high level to the second-stage trigger, and the second-stage trigger outputs a low level.

[0062] Preferably, when the negative pulse signal to be measured enters the delay chain, its pulse width decreases continuously until it disappears. If there is still a negative pulse signal at a certain tap, the rising edge of the negative pulse will trigger the CLK terminal of the first-stage trigger, and then the '1' at the D terminal of the first-stage trigger is transmitted to the Q terminal of the first-stage trigger, and then transmitted to the D terminal of the second-stage trigger via the Q terminal of the first-stage trigger.

[0063] Next, the D terminal of the second-stage trigger will receive the '1' signal from the first-stage trigger, and the CLK terminal of the second-stage trigger is connected to the sampling clock. Under the sampling of the sampling clock (Clock), the Q terminal value of the second-stage trigger is the output and will also become '1'.

[0064] However, if the negative pulse disappears at a certain tap, the tap will have no output signal, but will remain at a high level. At this time, the first-stage flip-flop is not triggered, and the first-stage flip-flop outputs 0 to the second-stage flip-flop, and the '1' signal at its D end will not be transmitted to the second-stage flip-flop, causing the Q end of the second-stage flip-flop to remain at '0'.

[0065] By observing the output value of the Q terminal of the second-stage trigger, for example, 1111100, it can be known that the negative pulse disappears after 5 taps. Therefore, the width of the negative pulse is the sum of the width reduction of the negative pulse caused by the delay time of the first 5 taps.

[0066] In this specific embodiment, the negative pulse widths reduced due to the delay in the first 1-5 taps are:

[0067] X1=1.5ps, X2=1.3ps, X3=1.35ps, X4=1.52ps, X5=1.6ps.

[0068] Therefore, the initial pulse width of the negative pulse can be deduced as:

[0069]

[0070] like Figure 4 As shown, if the output value of the Q terminal of the second-stage trigger is 1111100101000, it is found by observation that the number of 1s is 7, so the width of the negative pulse is the sum of the widths of the negative pulses reduced by the first 7 tap delays.

[0071] In this specific embodiment, the negative pulse widths reduced due to the delay of the first 1-7 taps are:

[0072] X1=1.5ps, X2=1.3ps, X3=1.35ps, X4=1.52ps, X5=1.6ps, X6=1.6ps, X7=1.5ps.

[0073] Therefore, the initial pulse width of the negative pulse can be deduced as:

[0074]

[0075] like Figure 2As shown, the delay chain is composed of multiple cascaded programmable logic unit structures. In order to build a longer delay chain, this specific embodiment cascades the small delay chains in multiple programmable logic unit structures CLB, and finally forms a long chain that can be extended to 6400 taps. This long chain can support the width range of the negative pulse to be measured from 0 to 10 nanoseconds (ns), meeting the needs of high-precision time measurement.

[0076] like Figure 2-3 As shown, each programmable logic unit structure includes four pairs of Dual LUTs and one Lookahead8, which together form a small delay chain with 16 delays and taps. In each pair of Dual LUTs, the output of the O6 signal terminal of the upper level LUT is used as the input of the lower level LUT, and the output of the O5 and O6 signal terminals of the upper level LUT is used as the input of Lookahead8; except for the last pair of Dual LUTs, the last level output of Lookahead8 corresponding to any pair of Dual LUTs is used as the input of the upper level LUT in the next pair of Dual LUTs; the input of the programmable logic unit structure is used as the input of the upper level LUT and Lookahead8 in the first pair of Dual LUTs; the last level output of Lookahead8 is used as the input of the next programmable logic unit structure; each output of Lookahead8 is used as a separate tap output.

[0077] Specifically, before the pulse to be tested is input into the delay chain, the width of the negative pulse reduced by each tap delay time is obtained:

[0078] The test pulses are continuously input into the delay chain at a fixed period and a set number; the test pulses are negative pulses with randomly and evenly distributed pulse widths;

[0079] Count the number N of two-stage D flip-flops that output high level in each cycle;

[0080] Count the number of times each high level quantity appears;

[0081] Each tap is numbered in order from small to large according to the propagation path of the delay chain; the value range of the tap number is [1, N], where N is a positive integer;

[0082] For any tap, the ratio of the number of high levels with the same tap number to the set number of negative pulse inputs multiplied by the ideal upper limit of the negative pulse width is taken as the width of the negative pulse reduced due to the delay time of the tap.

[0083] Specifically, the test pulse generation process includes: inputting a set first period signal to the SET terminal of a D flip-flop, inputting a set clock signal to the CLK terminal of the D flip-flop, and inputting a set second period signal to the D terminal of the D flip-flop; the Q terminal of the D flip-flop outputs a negative pulse with a randomly uniformly distributed pulse width;

[0084] The first periodic signal has the same period as the clock signal; the pulse width of the first periodic signal is smaller than the pulse width of the clock signal, and the difference between the two is larger than the estimated upper limit of the width of the pulse to be measured that can be measured by the delay chain;

[0085] The second period signal is used to set the period of the negative pulse.

[0086] Since the Versal series FPGA used in this specific embodiment can be estimated to have a negative pulse width range of 0-10ns according to the product manual, this specific embodiment generates a random and uniform negative pulse with a pulse width of 0-14ns as a test pulse to measure the width of the negative pulse caused by the delay time of each delay unit (i.e., tap) in the delay chain, ensuring that the pulse width of the test pulse can cover the range of this specific embodiment, that is, the presence of several pulse widths in the test pulse can make all taps output negative pulse signals.

[0087] like Figure 5 As shown in the figure, the random negative pulse signal is generated using two clocks CLK_1 (500MHz) and CLK_2 (62.5MHz) from different sources. Specific implementation:

[0088] 1. Use 500MHz CLK_1 and a D flip-flop D1. The value of the D terminal of D flip-flop D1 is synchronously controlled by CLK_1. The value of the D terminal changes from 1000000010000000… in sequence. The periodic signal of CLK_3 can be generated at the Q terminal of D flip-flop D1, and the period is 16ns.

[0089] 2. Set the CLK_2 and generated CLK_3 signals according to Figure 5 The D flip-flop D2 shown in the figure is connected. The D terminal of the D flip-flop D2 is connected to 0, and CLK_3 is connected to the asynchronous set SET terminal. The rising edge of CLK_2 triggers the Q terminal of the D flip-flop D2 to output 0; but the rising edge of CLK_3 triggers the Q terminal of the D flip-flop D2 to output 1, so the Q terminal of the D flip-flop D2 is generated. Figure 5 Negative pulse shown.

[0090] Since CLK_1 and CLK_2 are clocks from different sources, CLK_3 and CLK_2 generated by CLK_1 are also from different sources, so the phases of CLK_2 and CLK_3 are not fixed. As the phases of these two clocks are constantly changing, the width of the generated negative pulse is changing. Ideally, the width of the negative pulse varies from the difference between the rising edges of CLK2 and CLK3, that is, 0-16ns, and its upper limit is the period of CLK_2.

[0091] However, since CLK_3 has a certain pulse width and CLK3 is connected to the SET asynchronous setting terminal of the D flip-flop, there will be a 2ns width (i.e. 14-16ns) without a negative pulse. That is, the connection method of CLK3 will cause the output negative pulse width to be reduced by 2ns, so the actual range of the negative pulse width is 0-14ns.

[0092] 3. In order to ensure that the negative pulse sent into the delay chain has enough time to propagate and disappear in the delay chain, and the result is read by the second-level trigger after the tap, and finally the first-level trigger is reset. It is necessary to ensure that after a negative pulse is sent in, wait for a period of time before sending the next negative pulse, so the value 0 of the D terminal at the D trigger D2 is replaced by the D value 0111 (24 1s)...110111 (24 1s)...11 at the D trigger D3 that changes synchronously with CLK_2: when the value of D is 0, Q outputs 0, and when the value of D is 1, Q outputs 1. One 0 is connected to 24 1s, so that after a negative pulse is output, it will wait for 24 clock cycles before outputting another negative pulse. The period of the negative pulse is 16*25=400ns, that is, a negative pulse is sent in every 400ns.

[0093] 4. The final output period is 400ns, and the negative pulse width is a negative pulse with a randomly evenly distributed pulse width of 0-14ns.

[0094] like Figure 6 As shown, since the periods of clocks CLK_2 and CLK_3 from different sources are not exactly the same, the two clocks will increase a phase difference x every other period, as shown in FIG. Figure 6 x, 2x, etc. The phase difference is calculated according to Figure 5 The method can be used to convert it into a negative pulse of corresponding width.

[0095] After n cycles, the two rising edges of CLK_2 will be in one cycle of CLK_3, which will cause the negative pulse width to be shortened instantly. At this time, the width of the negative pulse can be expressed as nx-T2. Since CLK_3 will have one more cycle than CLK_2 after every n T2, the width of the negative pulse will slowly fill the cycle of CLK_2 evenly after enough cycles, that is, the width of the negative pulse is evenly distributed within the cycle T2 of CLK_2. The uniform distribution of the negative pulse width means that the width value of the negative pulse signal appears with the same probability within a given interval (0-14ns), which ensures the diversity and randomness of the pulse width, and there is no bias towards a specific width value.

[0096] In this specific embodiment, 640,000 negative pulses with a period of 400 ns and a pulse width of 0-14 ns are randomly and evenly distributed and continuously input into the delay chain. The delay chain has 6400 taps. When actually conducting experiments, this total number must be large enough to ensure that negative pulses of different widths are evenly distributed. This specific embodiment uses 640,000 times as an example.

[0097] Each time a pulse is input, the number of high levels in the output values ​​of all the two-stage D flip-flops corresponding to the delay chain is counted, and the numbers are 1, 2, 3, .., 6400 respectively; the total number of statistics is 640,000 times.

[0098] Count the number of times each high-level number appears; for example, 1 appears 100 times and 2 appears 120 times.

[0099] Each tap is numbered in order from small to large according to the propagation path of the delay chain; the value range of the tap number is [1, N], where N is a positive integer;

[0100] Then, the width of the negative pulse reduced by the delay time of the first tap is: 100 / 640000*16ns=2.5ps;

[0101] The width of the negative pulse reduced due to the delay time of the second tap is: 120 / 640000*16ns=3ps.

[0102] The average value of the width of the negative pulse reduced due to all tap delay times is calculated as the measurement accuracy of the negative pulse width. In this specific embodiment, the measurement accuracy is 1.5 ps.

[0103] Example 2

[0104] The present invention also provides a pulse width measurement system, comprising an inverter, a delay chain, a two-stage D flip-flop and a signal processing module; each tap of the delay chain is respectively connected to a corresponding two-stage D flip-flop,

[0105] If the pulse to be measured is a negative pulse, it is directly input into the delay chain; if the pulse to be measured is a positive pulse, it is inverted by the inverter and then input into the delay chain;

[0106] The delay chain is used to receive the pulse to be tested. The pulse to be tested is outputted in the delay chain in sequence through multiple taps with delayed output. The output signal of each tap of the delay chain is inputted into the corresponding two-stage D flip-flop. If the pulse to be tested outputted by a tap has a negative pulse signal, the corresponding two-stage D flip-flop outputs a high level; otherwise, it outputs a low level.

[0107] The signal processing module is used to count the number M of two-stage D flip-flops that output high levels, and output the sum of the reduced widths of negative pulses caused by the delay times of the first M taps on the delay chain propagation path as the width of the negative pulse; where M is a positive integer.

[0108] Specifically, if the signal processing module determines that the number of two-stage D flip-flops outputting high level is the same as the number of taps in the delay chain, it determines that the measurement range is exceeded and outputs a conclusion of measurement failure.

[0109] Specifically, the two-stage D flip-flop includes a first-stage flip-flop and a second-stage flip-flop; the clock end of the first-stage flip-flop is connected to the corresponding tap, and the D end of the first-stage flip-flop is connected to a continuous high level; the Q end of the first-stage flip-flop is connected to the D end of the second-stage flip-flop; the clock end of the second-stage flip-flop is connected to a sampling clock; the Q end output of the second-stage flip-flop is used as the output of the two-stage D flip-flop.

[0110] Specifically, the delay chain is composed of a plurality of programmable logic unit structures cascaded.

[0111] Specifically, each programmable logic unit structure includes four pairs of Dual LUTs and one Lookahead8; in each pair of Dual LUTs, the output of the O6 signal terminal of the upper LUT is used as the input of the lower LUT, and the outputs of the O5 and O6 signal terminals of the upper LUT are used as the input of Lookahead8; except for the last pair of Dual LUTs, the last level output of Lookahead8 corresponding to any pair of Dual LUTs is used as the input of the upper LUT in the next pair of Dual LUTs; the input of the programmable logic unit structure is used as the input of the upper LUT and the Lookahead8 in the first pair of Dual LUTs; the last level output of Lookahead8 is used as the input of the next programmable logic unit structure; each output of Lookahead8 is output as a separate tap.

[0112] The present invention uses the unique CLB architecture of the Versal series FPGA to build a new delay chain and uses the matching FPGA firmware to implement a high-precision TDC. The time measurement range of the TDC can reach 10 nanoseconds and the resolution can be close to 1.5 picoseconds.

[0113] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

Claims

1. A method for measuring pulse width, characterized in that: The following steps are involved: Input the pulse to be measured into the delay chain; If the pulse to be measured is a negative pulse, it is directly input into the delay chain; If the pulse to be measured is a positive pulse, it will be inverted and then input into the delay chain; The pulse to be tested is outputted in the delay chain in sequence through multiple taps with delayed output, and the output signal of each tap of the delay chain is inputted into the corresponding two-stage D flip-flop; if the pulse to be tested outputted by a tap has a negative pulse signal, the corresponding two-stage D flip-flop outputs a high level; otherwise, it outputs a low level; The number M of two-stage D flip-flops that output high level is counted, and the sum of the widths of the negative pulses reduced by the delay times of the first M taps on the delay chain propagation path is taken as the width of the negative pulse; wherein M is a positive integer.

2. The method for measuring pulse width according to claim 1, characterized in that: The following steps are also included: If the number of two-stage D flip-flops that output high levels is the same as the number of taps in the delay chain, it is determined that the range is exceeded and the measurement failure is output.

3. The method for measuring pulse width according to claim 1, characterized in that: The two-stage D flip-flop includes a first-stage flip-flop and a second-stage flip-flop; After the rising edge of the negative pulse is triggered, the first-stage trigger transmits the continuously input high level to the second-stage trigger; the second-stage trigger outputs a high level under the sampling of the sampling clock; When the first-stage trigger is not triggered, the first-stage trigger does not output a high level to the second-stage trigger, and the second-stage trigger outputs a low level.

4. The method for measuring pulse width according to claim 1, characterized in that: Before inputting the pulse to be measured into the delay chain, first obtain the reduced width of the negative pulse caused by each tap delay time: Continuously input the test pulses into the delay chain at a fixed period and set number; The test pulse is a negative pulse with a pulse width randomly and evenly distributed; Count the number N of two-stage D flip-flops that output high level in each cycle; Count the number of times each high level quantity appears; Each tap is numbered in order from small to large according to the propagation path of the delay chain; the value range of the tap number is [1, N], where N is the number of taps; For any tap, the ratio of the number of high levels with the same tap number to the set number of negative pulse inputs multiplied by the upper limit of the ideal width of the negative pulse is taken as the reduced width of the negative pulse caused by the delay time of the tap.

5. A pulse width measurement system according to claim 4, characterized in that: The test pulse generation process includes: inputting a set first period signal to the SET terminal of a D flip-flop, inputting a set clock signal to the CLK terminal of the D flip-flop, and inputting a set second period signal to the D terminal of the D flip-flop; the Q terminal of the D flip-flop outputs a negative pulse with a randomly evenly distributed pulse width; The first periodic signal has the same period as the clock signal; the pulse width of the first periodic signal is smaller than the pulse width of the clock signal, and the difference between the two is greater than the estimated upper limit of the width measurement of the pulse to be measured; The second period signal is used to set the period of the negative pulse.

6. A pulse width measurement system, characterized in that: It includes an inverter, a delay chain, a two-stage D flip-flop and a signal processing module; each tap of the delay chain is connected to the corresponding two-stage D flip-flop. If the pulse to be measured is a negative pulse, it is directly input into the delay chain; if the pulse to be measured is a positive pulse, it is inverted by the inverter and then input into the delay chain; The delay chain is used to receive the pulse to be tested. The pulse to be tested is outputted in the delay chain in sequence through multiple taps with delayed output. The output signal of each tap of the delay chain is inputted into the corresponding two-stage D flip-flop. If the pulse to be tested outputted by a tap has a negative pulse signal, the corresponding two-stage D flip-flop outputs a high level; otherwise, it outputs a low level. The signal processing module is used to count the number M of two-stage D flip-flops that output high levels, and output the sum of the reduced widths of negative pulses caused by the delay times of the first M taps on the delay chain propagation path as the width of the negative pulse; where M is a positive integer.

7. A pulse width measurement system according to claim 6, characterized in that: If the signal processing module determines that the number of two-stage D flip-flops outputting high levels is the same as the number of taps in the delay chain, it determines that the measurement range is exceeded and outputs a conclusion of measurement failure.

8. A pulse width measurement system according to claim 6, characterized in that: The two-stage D flip-flop includes a first-stage flip-flop and a second-stage flip-flop; the clock end of the first-stage flip-flop is connected to the corresponding tap, and the D end of the first-stage flip-flop is connected to a continuous high level; the Q end of the first-stage flip-flop is connected to the D end of the second-stage flip-flop; the clock end of the second-stage flip-flop is connected to a sampling clock; the Q end output of the second-stage flip-flop is used as the output of the two-stage D flip-flop.

9. A pulse width measurement system according to claim 6, characterized in that: The delay chain is composed of a plurality of programmable logic unit structures cascaded.

10. A pulse width measurement system according to claim 9, characterized in that: Each programmable logic unit structure includes four pairs of Dual LUTs and one Lookahead8; in each pair of Dual LUTs, the output of the O6 signal terminal of the upper LUT serves as the input of the lower LUT, and the output of the O5 and O6 signal terminals of the upper LUT serves as the input of Lookahead8; except for the last pair of Dual LUTs, the last level output of Lookahead8 corresponding to any pair of Dual LUTs serves as the input of the upper LUT in the next pair of Dual LUTs; the input of the programmable logic unit structure serves as the input of the upper LUT and the Lookahead8 in the first pair of Dual LUTs; the last level output of Lookahead8 serves as the input of the next programmable logic unit structure; each output of Lookahead8 serves as a separate tap output.

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