Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module. The solar cell comprises a silicon substrate. And the first doped polycrystalline silicon layer is arranged on one side of the silicon substrate. Wherein the silicon substrate comprises a first edge and a second edge which are oppositely arranged along a second direction, and a center line which is positioned between the first edge and the second edge and extends along the first direction. The first doped polycrystalline silicon layer comprises a plurality of strip-shaped regions which extend in the first direction and are distributed at intervals in the second direction, the first doped polycrystalline silicon layer strip-shaped regions arranged corresponding to the center line are second strip-shaped regions, and the other first doped polycrystalline silicon layer strip-shaped regions are first strip-shaped regions; the width of the second strip-shaped area in the second direction is larger than that of the first strip-shaped area in the second direction. The first direction intersects the second direction. According to the solar cell disclosed by the invention, the area ratio of the electron collection region to the hole collection region is optimized, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Back contact solar cells, or BC cells, are an important branch of current solar cell technology. The main feature of this type of battery is that both the positive and negative electrodes are placed on the back of the battery, thus achieving a structural design with no obstruction on the front.

[0003] When the battery is exposed to light, the battery substrate absorbs photons to generate electron-hole pairs, which are separated by the built-in electric field of the PN junction. The negative electrode of the battery collects electrons, and the positive electrode collects holes, which are then collected and transmitted to the outside.

[0004] However, due to the different diffusion lengths of holes and electrons, how to adjust the area ratio of the junction area and the field area to maximize the generation and collection of electrons and holes in order to improve battery efficiency is a key issue that needs to be overcome. Currently, this is mainly adjusted by changing the screen printing screen, but this method is labor-intensive and costly. Summary of the invention

[0005] In view of the above problems, embodiments of the present disclosure provide a solar cell and a photovoltaic module.

[0006] One aspect of the present disclosure provides a solar cell, comprising: a silicon substrate. A first doped polysilicon layer disposed on one side of the silicon substrate. The silicon substrate comprises a first edge and a second edge disposed opposite to each other along a second direction, and a center line extending along the first direction between the first edge and the second edge. The first doped polysilicon layer comprises a plurality of strip regions extending along the first direction and spaced apart along the second direction, the strip regions of the first doped polysilicon layer disposed corresponding to the center line are second strip regions, the remaining strip regions of the first doped polysilicon layer are first strip regions, and the width of the second strip regions along the second direction is greater than the width of the first strip regions along the second direction. The first direction intersects the second direction. Usually, the area near the center line of the cell has fewer defects than the surrounding areas and is not restricted by electrode matching, so the second strip area feature setting is freer than the first strip area. By widening the second strip area, on the one hand, the doping area area is increased, and the carrier collection area is increased, and on the other hand, the electrode setting density will not be affected by the change in the width of the strip area, thereby affecting the carrier collection. If the strip area is widened as a whole, although the junction area increases, the electrode setting density will decrease, which will lead to a weakening of the carrier collection ability and affect the overall efficiency of the battery. In addition, if the battery needs to be sliced, passivation optimization around the cut can be achieved by covering the cut part (usually near the center line) with doped polysilicon.

[0007] According to an embodiment of the present disclosure, the solar cell further includes: a collector electrode disposed on the side of the first doped polysilicon layer away from the silicon substrate. The second strip region includes a first electrode region disposed between the collector electrode and the silicon substrate, and a first non-electrode region disposed at a position corresponding to the center line, the first electrode region is at least two, and the first non-electrode region connects the first electrode region to form an integral structure. The first non-electrode region realizes connectivity with the first electrode region, improves lateral carrier transport, and promotes carrier collection.

[0008] According to an embodiment of the present disclosure, two ends of the second strip region along the first direction are provided with slice alignment regions.

[0009] According to an embodiment of the present disclosure, the first doped polysilicon strip region adjacent to the first edge of the first strip region is the first edge strip region, and the first doped polysilicon strip region adjacent to the second edge of the first strip region is the second edge strip region. The width of the first edge strip region and / or the second edge strip region along the second direction is greater than the width of any strip region in the first strip region except the first edge strip region and the second edge strip region along the second direction.

[0010] According to an embodiment of the present disclosure, the solar cell further includes: a collector electrode disposed on a side of the first doped polysilicon layer away from the silicon substrate. The first edge strip region includes a second electrode region disposed between the collector electrode and the silicon substrate, and a second non-electrode region disposed between the first edge and the second electrode region, the second electrode region is at least two, and the second non-electrode region connects the second electrode region to form an integral structure. And / or the second edge strip region includes a third electrode region disposed between the collector electrode and the silicon substrate, and a third non-electrode region disposed between the second edge and the third electrode region, the third electrode region is at least two, and the third non-electrode region connects the third electrode region to form an integral structure. The second electrode region is connected through the second non-electrode region, and the third non-electrode region is connected to the third electrode region, thereby improving lateral carrier transport and promoting carrier collection.

[0011] According to an embodiment of the present disclosure, the first doped polysilicon strip region adjacent to the first edge of the first strip region is a first edge strip region, and the width of the first edge strip region along the second direction is less than the width of the second strip region along the second direction. And / or the first doped polysilicon strip region adjacent to the second edge of the first strip region is a second edge strip region, and the width of the second edge strip region along the second direction is less than the width of the second strip region along the second direction. The edge of the cell has more defects than the middle, and the width of the first edge strip region and the second edge strip region along the second direction is less than the width of the second strip region along the second direction, which can increase the junction area and avoid covering too much edge area, resulting in increased defects and edge overlap short circuits.

[0012] According to an embodiment of the present disclosure, the silicon substrate further includes a third edge and a fourth edge arranged opposite to each other along a first direction, and the solar cell further includes: a collector electrode arranged on a side of the first doped polysilicon layer away from the silicon substrate. The second strip region includes a first electrode region arranged between the collector electrode and the silicon substrate and a first non-electrode region arranged at a position corresponding to the center line. The distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first strip region to the adjacent third edge; and / or, the distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first electrode region to the adjacent third edge; and / or, the distance from the end of the first strip region to the adjacent third edge is less than or equal to the distance from the end of the first electrode region to the adjacent third edge. The distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first strip region to the adjacent third edge, and the distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first electrode region to the adjacent third edge. Meeting any one of these conditions can ensure that a certain cutting alignment area is retained at the end of the second strip region for easy slicing.

[0013] According to an embodiment of the present disclosure, the distance from the end of the first non-electrode area to the adjacent fourth edge is greater than the distance from the end of the first strip area to the adjacent fourth edge; and / or, the distance from the end of the first non-electrode area to the adjacent fourth edge is greater than the distance from the end of the first electrode area to the adjacent fourth edge; and / or, the distance from the end of the first strip area to the adjacent fourth edge is less than or equal to the distance from the end of the first electrode area to the adjacent fourth edge. The distance from the end of the first non-electrode area to the adjacent fourth edge is greater than the distance from the end of the first strip area to the adjacent fourth edge, and the distance from the end of the first non-electrode area to the adjacent fourth edge is greater than the distance from the end of the first electrode area to the adjacent fourth edge. Meeting any one of these conditions can ensure that a certain cutting alignment area is retained at the end of the second strip area, further improving the accuracy of slicing.

[0014] According to the embodiments of the present disclosure, the first doped polysilicon layer has a conductivity type opposite to that of the silicon substrate, and the first doped polysilicon layer is an inversion region. The area other than the inversion region on one side of the solar cell provided with the inversion region is a homotype region, and the area ratio of the homotype region to the inversion region ranges from 0.3 to 1.5. By adjusting the area ratio of the P region and the N region, the generation and collection of electrons and holes are maximized to achieve the purpose of improving the battery efficiency.

[0015] Another aspect of the present disclosure provides a solar cell, comprising: a silicon substrate. A first doped polysilicon layer disposed on one side of the silicon substrate. The silicon substrate comprises a first edge and a second edge disposed opposite to each other along a second direction, and a third edge and a fourth edge disposed opposite to each other along the first direction. The first doped polysilicon layer comprises a plurality of strip regions extending along the first direction and spaced apart along the second direction, the first doped polysilicon strip region adjacent to the first edge is a first edge strip region, and the first doped polysilicon strip region adjacent to the second edge is a second edge strip region. The width of the first edge strip region and / or the second edge strip region along the second direction is greater than the width of any one of the first doped polysilicon strip regions except the first edge strip region and the second edge strip region along the second direction.

[0016] According to an embodiment of the present disclosure, the distance from the side of the first edge strip region adjacent to the first edge to the first edge is greater than the distance from the side of the second edge strip region adjacent to the second edge to the second edge. Alternatively, the distance from the side of the second edge strip region adjacent to the second edge to the second edge is greater than the distance from the side of the first edge strip region adjacent to the first edge to the first edge. The two edges of the cell are usually damaged to different degrees, so in actual application, better passivation of severely damaged areas can be achieved by adjusting the doped polysilicon coverage of the two edges.

[0017] According to an embodiment of the present disclosure, the solar cell further includes: a collector electrode disposed on the side of the first doped polysilicon layer away from the silicon substrate. The first edge strip region includes a second electrode region disposed between the collector electrode and the silicon substrate, and a second non-electrode region disposed between the first edge and the second electrode region, the number of the second electrode region being at least two, and the second non-electrode region connecting the second electrode region to form an integral structure. And / or the second edge strip region includes a third electrode region disposed between the collector electrode and the silicon substrate, and a third non-electrode region disposed between the second edge and the third electrode region, the number of the third electrode region being at least two, and the third non-electrode region connecting the third electrode region to form an integral structure.

[0018] Another aspect of the present disclosure provides a photovoltaic module, comprising: a plurality of solar cells according to any embodiment of the present disclosure, a packaging layer for covering the surfaces of the plurality of solar cells, and a cover plate for covering the surface of the packaging layer away from the plurality of solar cells.

[0019] According to the embodiments of the present disclosure, by providing a doped polysilicon layer at a position corresponding to a relatively wide center line, the area ratio of the current collection region in the solar cell is increased. Based on the diffusion length characteristics of holes and electrons, the area ratio of the electron collection region to the hole collection region is optimized, thereby improving the current collection efficiency and achieving an improvement in the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram showing a layout of a back electrode of a back contact solar cell according to the related art;

[0022] Figure 2 Schematically shows a distribution diagram of a first doped polysilicon layer corresponding to a center line of a back side of a back contact solar cell according to an embodiment of the present disclosure;

[0023] Figure 3A Schematically shows a distribution diagram of a collector electrode on a first doped polysilicon layer corresponding to a center line of a back side of a back contact solar cell according to an embodiment of the present disclosure; Figure 3B Schematically shows a distribution diagram of collector electrodes on a first doped polysilicon layer corresponding to a center line of a back side of a back contact solar cell according to another embodiment of the present disclosure;

[0024] Figure 4 Schematically shows a distribution diagram of a doped polysilicon layer at the back edge of a back contact solar cell according to an embodiment of the present disclosure;

[0025] Figure 5A Schematically shows a distribution diagram of a collector electrode on a doped polysilicon layer at the back edge of a back contact solar cell according to an embodiment of the present disclosure; Figure 5B Schematically shows a distribution diagram of a doped polysilicon layer at the back edge of a back contact solar cell according to an embodiment of the present disclosure; Figure 5C Schematically shows a distribution diagram of a doped polysilicon layer at the back edge of a back contact solar cell according to another embodiment of the present disclosure; Figure 5D Schematically shows a distribution diagram of a doped polysilicon layer at the back edge of a back contact solar cell according to another embodiment of the present disclosure;

[0026] Figure 6 Schematically shows a distribution diagram of a first doped polysilicon layer and a collector electrode thereon corresponding to a center line of a back side of a back contact solar cell according to an embodiment of the present disclosure;

[0027] Figure 7 Schematically shows a distribution diagram of a first doped polysilicon layer corresponding to a center line of a back side of a back contact solar cell according to another embodiment of the present disclosure;

[0028] Figure 8 The diagram schematically shows the distribution of the collector electrode on the doped polysilicon layer at the back edge of a back-contact solar cell according to another embodiment of the present disclosure.

[0029] [Description of Reference Numerals]

[0030] 1-silicon substrate; 2-second strip region; 3-first strip region; 31-first edge strip region; 32-second edge strip region; 4-collecting electrode. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0032] It should be noted that in the drawings or descriptions, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form a new solution without conflict. In addition, each claim can be used as an embodiment alone or the technical features in each claim can be combined as a new embodiment. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are in a form known to a person of ordinary skill in the art. In addition, although demonstrations of parameters containing specific values ​​may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0033] Unless there are technical obstacles or contradictions, the various embodiments of the present disclosure can be freely combined to form additional embodiments, and these additional embodiments are all within the protection scope of the present disclosure.

[0034] Although the present disclosure is described in conjunction with the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to exemplify the preferred embodiments of the present disclosure and should not be construed as limiting the present disclosure. The dimensional ratios in the accompanying drawings are merely illustrative and should not be construed as limiting the present disclosure.

[0035] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

[0036] Figure 1 The diagram schematically shows a layout of a back electrode of a back-contact solar cell according to the related art.

[0037] In the relevant preparation process, such as Figure 1As shown in the figure, after the phosphorus-doped polysilicon layer is prepared on one side of the P-type silicon wafer, it needs to undergo the first patterning. Laser can be used to irradiate the PSG (Phospho Silicate Glass) in the P region on the back of the silicon wafer to make it loose from dense. The density difference of PSG in the P / N region is used to make the SiO2 in the P region loose in the wet etching. 2 / poly-Si is removed to separate the P / N regions. Finally, a metal gate is printed on the back of the silicon wafer through a screen printing process as a current transmission channel.

[0038] It should be noted that, in the embodiments of the present disclosure, the substrate conductivity type is taken as an example of P-type, so the N region refers to the junction region, and the P region refers to the field region.

[0039] In some other embodiments, the silicon substrate may be an N-type silicon substrate as the main light-absorbing layer of the battery.

[0040] The electrode pattern and the first patterned doped polysilicon layer pattern design must match. Adjusting the P / N area ratio requires adjusting the first patterned pattern design simultaneously, and also requires a matching electrode pattern (such as Figure 1 ).For example Figure 1 The figure mainly shows the bus electrode, the collector electrode, and the positions of some pads, and the center dividing line (not shown in the figure) divides it into two parts from the middle.

[0041] It should be noted that Figure 1 The electrode layout shown is only exemplary. The battery of the technical solution of the present application can adopt a design with a main grid (with a busbar electrode) or a design without a main grid (without a busbar electrode). The relevant technical solutions disclosed in the present application can be implemented with or without a main grid, and the corresponding technical effects can be achieved. When the battery of the technical solution of the present application adopts a design with a main grid, the doped polysilicon layer can be correspondingly arranged between the collector electrode, the busbar electrode and the silicon substrate, and the arrangement direction and extension direction are the same as the corresponding electrodes; when the battery of the technical solution of the present application adopts a design without a main grid, the doped polysilicon layer can be correspondingly arranged between the collector electrode and the silicon substrate, and the arrangement direction and extension direction are the same as the corresponding electrodes.

[0042] In some cases, a doped polysilicon layer may be provided in a direction perpendicular to the extension direction of the collector electrode to laterally connect the collector electrode and the doped polysilicon layer between the silicon substrate to achieve optimized carrier transmission and collection.

[0043] The embodiments of the present disclosure take back-contact solar cells as an example, but the technical solution of the present disclosure is not limited to back-contact solar cells, and can also be used for other types of solar cells.

[0044] Figure 2The diagram schematically shows a distribution diagram of a first doped polysilicon layer corresponding to a center line of a back surface of a back-contact solar cell according to an embodiment of the present disclosure.

[0045] According to the embodiments of the present disclosure, Figure 2 As shown, the present disclosure provides a back-contact solar cell, comprising: a silicon substrate 1, and a first doped polysilicon layer arranged on one side of the silicon substrate. The silicon substrate 1 comprises a first edge and a second edge arranged opposite to each other along a second direction y, and a center line extending along a first direction x between the first edge and the second edge. The first doped polysilicon layer comprises a plurality of strip regions extending along the first direction x and spaced apart along the second direction y, the first doped polysilicon layer strip regions arranged corresponding to the center line are second strip regions 2, and the remaining first doped polysilicon layer strip regions are first strip regions 3, and the width of the second strip region 2 along the second direction y is greater than the width of the first strip region 3 along the second direction y. The first direction x intersects with the second direction y.

[0046] It should be noted that in this embodiment, the first doped polysilicon layer has an opposite conductivity type to the silicon substrate 1, which can not only achieve passivation optimization of the cell, but also increase the junction area and increase carrier generation. In other embodiments, the first doped polysilicon layer can also have the same conductivity type as the silicon substrate 1, which is mainly used to achieve passivation optimization in the middle of the cell, especially for the cell to be sliced. Such a setting can ensure that the silicon near the cut is covered by the doped polysilicon layer after slicing, and still ensure better passivation. At the same time, it also increases the area for carrier generation and collection, which not only avoids the influence of cutting defects, but also improves carrier generation and collection, and improves cell performance.

[0047] The first doped polysilicon layer is precisely designed to include a plurality of strip regions, which extend along a first direction (eg, direction x in the drawing) and are spaced apart in a second direction (eg, direction y in the drawing), and the first direction and the second direction intersect.

[0048] Among them, a first doped polysilicon layer strip area corresponding to the center line of the silicon substrate (which can also be understood as the center line of the cell extending along the first direction, and the cell is divided into two halves by the center line) is defined as the second strip area, which can be understood as the projection area of ​​the silicon substrate center line passing through the second strip area on the silicon substrate. The width of the second strip area along the y direction is designed to be 1.8mm to enhance the current collection efficiency.

[0049] The remaining first doped polysilicon layer strip regions are used as first strip regions, and the width along the y direction is designed to be 0.66 mm to optimize the balance between the photoelectric conversion efficiency and the current distribution.

[0050] Optionally, the width of the first doped polysilicon layer in the second strip region is in the range of 1.2 to 2.2 mm (may be 1.2 mm, 1.4 mm, 1.6 mm, 1.8 mm, 2.0 mm, 2.2 mm). The width of the first doped polysilicon layer in the first strip region is in the range of 0.5 to 0.72 mm (may be 0.5 mm, 0.54 mm, 0.60 mm, 0.68 mm, 0.70 mm, 0.72 mm).

[0051] On the surface of the first doped polysilicon layer away from the silicon substrate, collector electrodes are formed, which are in conductive contact with the first strip region and the second strip region respectively, and extend along the x direction to collect current. The design of the second strip region being wider than the first strip region helps to reduce series resistance, increase the junction area, and improve current output capacity and battery efficiency.

[0052] All electrodes are connected through an interconnection structure to collect and conduct current. The interconnection structure can be a welding strip or an integrated backplane.

[0053] Figure 3A The diagram schematically shows the distribution of the collector electrodes on the first doped polysilicon layer corresponding to the center line of the back side of the back contact solar cell according to an embodiment of the present disclosure. Figure 3B The diagram schematically shows the distribution of collector electrodes on the first doped polysilicon layer corresponding to the center line of the back side of a back-contact solar cell according to another embodiment of the present disclosure.

[0054] According to an embodiment of the present disclosure, the back contact solar cell further includes: a collector electrode 4 disposed on the side of the first doped polysilicon layer away from the silicon substrate. The second strip region includes a first electrode region disposed between the collector electrode and the silicon substrate, and a first non-electrode region disposed at a position corresponding to the center line, the first electrode region is at least two, and the first non-electrode region is connected to the first electrode region to form an integral structure.

[0055] In some embodiments, Figure 3A As shown, the collector electrode 4 can be a continuous electrode, and insulation treatment is performed at the position required during component packaging. Figure 3B As shown, the collector electrodes 4 of the first electrode region may also be arranged at intervals along the first direction. In this case, the width of the collector electrodes along the second direction is the width of the second strip region.

[0056] The position exactly corresponding to the center line of the cell, i.e., the first non-electrode area, does not have an electrode, so the design of the present application does not need to change the electrode arrangement, saving labor costs. When the cell needs to be sliced, the first non-electrode area also provides a cutting position.

[0057] The second strip region includes a plurality of (such as two, or eight, or sixteen, or eighteen, according to actual needs) first electrode regions that are spaced apart and distributed. The number of the first electrode regions can be determined according to the number of collector electrodes arranged in the first electrode regions, such as Figure 3A The schematic diagram shows two collector electrodes in the first electrode region. In this case, there are two first electrode regions, which are spaced apart and distributed along the y direction. Figure 3B The schematic diagram shows twelve collector electrodes in the first electrode region. At this time, there are twelve first electrode regions. The twelve collector electrodes and twelve first electrode regions include six groups of collector electrodes and first electrode regions spaced apart along the x direction, and each group includes two collector electrodes and first electrode regions spaced apart along the y direction. These electrode regions are connected to an external circuit through the collector electrodes for collecting current. One collector electrode corresponds to one electrode region.

[0058] At the position corresponding to the center line, a wider first non-electrode area is set. This area is not directly connected to the collector electrode, but serves as a buffer zone for current distribution, which helps to balance the current density of the entire strip area and reduce thermal effects and resistance losses.

[0059] The first non-electrode region is indirectly connected to the collector electrode through the first electrode regions on both sides thereof to form an integral structure, which not only ensures the effective collection of current, but also optimizes the current path and improves the battery performance.

[0060] This embodiment significantly improves the performance of the cell by further optimizing the structural design of the back contact solar cell, especially the layout of the collector electrode and the strip area on the doped polysilicon layer. At the same time, by doping polysilicon in the non-electrode area, lateral carrier transmission in different electrode areas is achieved, improving carrier transmission and collection.

[0061] According to an embodiment of the present disclosure, two ends of the second strip region along the first direction are provided with slice alignment regions.

[0062] On the doped polysilicon layer, according to the cell slice cutting requirements, a slice alignment area is usually provided at the end of the second strip area, and the slice alignment area can be surrounded by the ends of the first electrode area and the first non-electrode area. These alignment areas are usually located at the boundary of the strip area or a specific position to provide accurate reference points in the subsequent slice cutting process. The non-doped polysilicon on the substrate corresponding to the slice alignment area is used for alignment during slice cutting.

[0063] The slice alignment area can be realized by etching specific marks, patterns or grooves on the doped polysilicon layer. These marks can be simple lines, crosses, circles, concave shapes or other easily identifiable shapes to ensure accurate alignment during the cutting process.

[0064] In order to improve the alignment accuracy and cutting efficiency, the design of the slice alignment area should take into account the accuracy limitations of the cutting equipment and the optimization of the cutting path. For example, multiple alignment points or alignment lines can be designed to ensure accuracy in different cutting directions.

[0065] For example, after the cell is manufactured and tested, the cell is sliced ​​using a laser cutter or diamond wire cutter. During the cutting process, the cutting equipment will be precisely aligned according to the markings in the slice alignment area and cut according to the predetermined cutting path.

[0066] After slicing, each cell will maintain its original electrical performance and structural integrity while meeting the requirements of subsequent packaging and applications.

[0067] This embodiment further improves the design and manufacturing process of back-contact solar cells by introducing the concept of slice alignment area. The slice alignment area not only improves the slice cutting accuracy and efficiency of the cell, but also ensures that the cut cell has consistent performance and appearance. This design makes back-contact solar cells more advantageous in large-scale production and automated processing. At the same time, the flexibility and customizability of the slice alignment area also provides more possibilities for cell cutting in different application scenarios.

[0068] Figure 4 The diagram schematically shows the distribution of the doped polysilicon layer at the back edge of a back-contact solar cell according to an embodiment of the present disclosure.

[0069] According to the embodiments of the present disclosure, Figure 4 As shown, the first doped polysilicon strip region adjacent to the first edge of the first strip region is the first edge strip region 31, and the first doped polysilicon strip region adjacent to the second edge of the first strip region is the second edge strip region 32. The width of the first edge strip region 31 and / or the second edge strip region 32 along the second direction is greater than the width of any strip region in the first strip region 3 except the first edge strip region 31 and the second edge strip region 32 along the second direction.

[0070] The first strip region includes a plurality of strip regions extending along the x direction, wherein the strip region adjacent to the first edge of the silicon substrate is defined as a first edge strip region, and the strip region adjacent to the second edge is defined as a second edge strip region.

[0071] In order to optimize current collection and distribution, the width of the first edge strip region and / or the second edge strip region along the y direction is designed to be greater than the width of any other strip region in the first strip region. For example, the width of the first edge strip region and the second edge strip region is 0.8 mm, while the width of the first strip region in the middle is 0.66 mm.

[0072] It should be noted that the edge spots of the silicon wafers of the solar cell are engraved with frame lines for isolating the front and back sides, which specifically prevents the front and back sides from being turned on and leaking electricity.

[0073] The increase in the junction area can be achieved by increasing the length of at least one side of the rectangle enclosed by the frame line. For example, the frame line extending in the x direction adjacent to the first edge and the second edge is moved outward in the y direction by 50-100μm (can be 50μm, 60μm, 70μm, 80μm, 90μm, 100μm), reducing the area of ​​the frame line laser engraved on the silicon wafer, that is, reducing the area of ​​the engraving converted into the P region and increasing the area of ​​the N region. The silicon substrate 1 includes a first edge and a second edge arranged relatively along the second direction y, and a third edge and a fourth edge arranged relatively along the first direction x. Usually, after adjustment, the distance from the frame line extending in the x direction adjacent to the first edge and the second edge to the edge of the battery in the y direction will be less than the distance from the frame line extending in the y direction adjacent to the third edge and the fourth edge to the edge of the battery in the x direction. Therefore, the outward movement of the frame line extending in the x direction adjacent to the first edge and the second edge can more effectively increase the junction area.

[0074] Optionally, the width of the doped polysilicon layer at the edge of the solar cell is in the range of 0.75 to 0.85 mm (may be 0.75 mm, 0.76 mm, 0.78 mm, 0.80 mm, 0.82 mm, 0.85 mm).

[0075] This design enables more efficient current collection in the edge areas of the cell, namely the first edge strip area and the second edge strip area. Since these areas are usually close to the edge of the cell, the current may encounter more resistance and loss during transmission. By increasing the width of these areas, the current density can be reduced, the resistance loss can be reduced, and the overall current collection efficiency can be improved.

[0076] This embodiment significantly improves the current collection efficiency and overall performance of the cell by specially designing the first strip region in the back contact solar cell, especially widening the first edge strip region and the second edge strip region. This design not only reduces the resistance loss in the edge region and the energy dissipation in the current transmission process, but also maintains the efficient photoelectric conversion capability of the middle region.

[0077] Figure 5A The diagram schematically shows the distribution of the collector electrode on the doped polysilicon layer at the back edge of a back-contact solar cell according to an embodiment of the present disclosure. Figure 5B The diagram schematically shows the distribution of the doped polysilicon layer at the back edge of a back-contact solar cell according to an embodiment of the present disclosure. Figure 5C The diagram schematically shows a distribution diagram of a doped polysilicon layer at the back edge of a back-contact solar cell according to another embodiment of the present disclosure. Figure 5DThe diagram schematically shows a distribution diagram of a doped polysilicon layer at the back edge of a back-contact solar cell according to yet another embodiment of the present disclosure.

[0078] According to the embodiments of the present disclosure, Figure 5A As shown, the back contact solar cell also includes, for example: a collector electrode 4 arranged on the side of the first doped polysilicon layer away from the silicon substrate. The first edge strip region 31 includes a second electrode region arranged between the collector electrode 4 and the silicon substrate 1, and a second non-electrode region arranged between the first edge and the second electrode region, the second electrode region is at least two, and the second non-electrode region connects the second electrode region to form an integral structure. And / or the second edge strip region 32 includes a third electrode region arranged between the collector electrode 4 and the silicon substrate, and a third non-electrode region arranged between the second edge and the third electrode region, the third electrode region is at least two, and the third non-electrode region connects the third electrode region to form an integral structure. The number of the second electrode regions can be determined according to the number of collector electrodes arranged in the second electrode region, and one collector electrode corresponds to one electrode region. The number of the third electrode regions can be determined according to the number of collector electrodes arranged in the third electrode region, and one collector electrode corresponds to one electrode region.

[0079] In some embodiments, the collector electrodes corresponding to the first edge strip region 31 and the second edge strip region 32 may be continuous electrodes or discontinuous electrodes.

[0080] like Figure 5B As shown, the at least two second electrode regions may refer to at least two second electrode regions distributed along the second direction y, that is, at least a second electrode region-a second non-electrode region-a second electrode region are sequentially formed along the second direction y.

[0081] like Figure 5C As shown, the at least two second electrode regions may also mean that at least two second electrode regions can be formed along the first direction x, the second non-electrode region is located on one side of the second electrode region, or the second non-electrode region is located on one side of the second electrode region and between adjacent second electrode regions.

[0082] like Figure 5D As shown, the number of at least two second electrode regions may also refer to at least two second electrode regions formed along the first direction x and at least two second electrode regions distributed along the second direction y.

[0083] Similarly, the configuration of at least two third electrode regions can refer to the second electrode region.

[0084] It should be noted that the selection of the actual solution needs to consider the balance of parasitic absorption, passivation, and carrier generation and collection of the doped polysilicon layer, so the edge doped polysilicon layer is usually set to the first two forms. The third is more suitable for application on the back side of the cell, not on the edge.

[0085] In some embodiments, the battery includes a silicon substrate, one side of which is covered with a doped polysilicon layer. A tunneling layer, such as a silicon dioxide layer, may also be provided between the doped polysilicon layer and the silicon substrate. In order to more effectively collect current and reduce resistance loss, the battery is also designed with a collector electrode, which is located on the side of the doped polysilicon layer away from the silicon substrate.

[0086] In the first strip region, the portion close to the first edge of the silicon substrate is defined as the first edge strip region. In this region, at least two second electrode regions are arranged between the collector electrode and the silicon substrate, and these electrode regions are used to collect photocurrent from the silicon substrate.

[0087] Between the first edge and the second electrode area, a second non-electrode area is provided. These non-electrode areas are not in direct contact with the electrodes, but they physically connect the adjacent second electrode areas to form a stable overall structure. This design helps to enhance the mechanical strength of the electrode area, improve the lateral transmission of current, and reduce the thermal effect caused by current concentration.

[0088] Similarly, a third electrode region and a third non-electrode region may also be designed in the portion of the first strip region adjacent to the second edge of the silicon substrate. The third electrode region is also used to collect current, while the third non-electrode region connects the adjacent third electrode region to form an overall structure similar to the first edge strip region.

[0089] The collector electrode is electrically connected to the second electrode region and (if applicable) the third electrode region, respectively, to ensure that the photocurrent can be smoothly transmitted from the silicon substrate to the collector electrode and finally output to the external circuit.

[0090] This embodiment further optimizes the current collection structure of the battery by arranging multiple electrode regions and non-electrode regions in the first edge strip region and (if applicable) the second edge strip region of the back contact solar cell. This design promotes the lateral transport of carriers in different electrode regions and improves carrier collection.

[0091] According to the embodiments of the present disclosure, Figure 4 As shown, the first doped polysilicon strip region adjacent to the first edge of the first strip region 3 is a first edge strip region 31, and the width of the first edge strip region 31 along the second direction y is less than the width of the second strip region 2 along the second direction y. And / or the first doped polysilicon strip region adjacent to the second edge of the first strip region 3 is a second edge strip region 32, and the width of the second edge strip region 32 along the second direction y is less than the width of the second strip region 2 along the second direction y.

[0092] In some embodiments, the structure of the back contact solar cell is further optimized, especially in the width design of the stripe region, which is intended to improve the photoelectric conversion efficiency of the cell while maintaining or improving the current collection performance.

[0093] The silicon substrate can be made of single crystal silicon material or polycrystalline silicon material, and the conductivity type can be P type or N type. The material, conductivity type, size and thickness are determined according to specific needs.

[0094] A doped polysilicon layer is formed on one side of the silicon substrate. The layer is divided into a plurality of strip regions along a first direction (such as a horizontal direction), including a first strip region and a second strip region, etc. The strip-shaped doped polysilicon layer may be obtained by patterning, may be obtained by locally in-situ doping an intrinsic layer, or may be obtained by using a mask layer.

[0095] The first strip region is adjacent to the first edge of the silicon substrate, and the region is defined as the first edge strip region. In order to optimize the photoelectric conversion efficiency, the width of the first edge strip region along the second direction (such as the vertical direction) is designed to be smaller than the width of the second strip region along the same direction. For example, the width of the other parts of the first strip region except the first edge strip region is 2 mm, while the width of the first edge strip region is reduced to 1.5 mm.

[0096] If the battery design includes a second edge strip region adjacent to the second edge, the width of the region along the second direction can also be designed to be smaller than the second strip region. This design helps to reduce the impact of edge effects on battery performance and further improve photoelectric conversion efficiency.

[0097] By reducing the width of the first edge strip region and (if applicable) the second edge strip region, the light shielding of these regions can be reduced, thereby increasing the effective illumination area of ​​the cell, which helps to improve the photoelectric conversion efficiency, so that more photons can be converted into electrical energy.

[0098] At the same time, as the width of these edge strip regions decreases, their resistance losses will also decrease accordingly, helping to maintain or improve the current collection performance of the battery.

[0099] This embodiment achieves improved photoelectric conversion efficiency and current collection performance by optimizing the width design of the first strip region (including the first edge strip region) and (if applicable) the second edge strip region in the back contact solar cell. The second strip region is wider along the second direction, which provides space for cutting. On the other hand, there are fewer defects in the middle of the cell, and the second strip region is wider than the edge to better collect carriers. There are more defects at the edge of the cell, and the width of the edge strip region cannot be set too wide, otherwise the area affected by defects will be larger.

[0100] Figure 6The diagram schematically shows the distribution of the first doped polysilicon layer and the collector electrode thereon corresponding to the center line of the back side of the back contact solar cell according to an embodiment of the present disclosure.

[0101] According to the embodiments of the present disclosure, Figure 6 As shown, the silicon substrate also includes a third edge and a fourth edge arranged opposite to each other along the first direction x, and the solar cell also includes, for example: a collector electrode 4 arranged on the side of the first doped polysilicon layer away from the silicon substrate. The second strip region 2 includes a first electrode region arranged between the collector electrode 4 and the silicon substrate 1 and a first non-electrode region arranged at a position corresponding to the center line. The distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first strip region 3 to the adjacent third edge; and / or the distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first electrode region to the adjacent third edge; and / or the distance from the end of the first strip region 3 to the adjacent third edge is less than or equal to the distance from the end of the first electrode region to the adjacent third edge. An area without the first doped polysilicon layer is formed by enclosing the end of the first strip region 3, the end of the first non-electrode region, and the adjacent third edge as a cutting alignment area, which is convenient for slicing and improves the cutting accuracy.

[0102] According to an embodiment of the present disclosure, the distance from the end of the first non-electrode region to the adjacent fourth edge is greater than the distance from the end of the first strip region to the adjacent fourth edge; and / or, the distance from the end of the first non-electrode region to the adjacent fourth edge is greater than the distance from the end of the first electrode region to the adjacent fourth edge; and / or, the distance from the end of the first strip region to the adjacent fourth edge is less than or equal to the distance from the end of the first electrode region to the adjacent fourth edge. The relevant dimension design of the fourth edge on the opposite side of the cell to the third edge can refer to the layout of the third edge in the above embodiment to achieve more accurate slice alignment from both sides.

[0103] It should be noted that the corresponding sizes of the third edge and the fourth edge may be equal or unequal. For example, the distance from the end of the first non-electrode region to the adjacent third edge may be equal or unequal to the distance from the end of the first non-electrode region to the adjacent fourth edge.

[0104] In other embodiments, the minimum distance from the end of the first non-electrode area to the adjacent third edge or fourth edge is greater than 0.2 cm (for example, it can be 0.25 cm, 0.3 cm, 0.35 cm, 0.5 cm, 0.7 cm, 0.8 cm, 0.9 cm, 1 cm, 1.1 cm, or 1.5 cm, etc.). And / or the distance from the end of the first strip area 3 to the adjacent third edge or fourth edge ranges from 0.5 to 2 mm (for example, it can be 0.9 to 1.5 mm, or 1.1 to 1.3 mm, or 1.2 to 1.8 mm, etc.). The minimum distance from the end of the first non-electrode area to the adjacent third edge is greater than 0.2 cm, which can ensure that there is enough alignment distance for slicing in this area. The distance from the end of the first strip area to the adjacent third edge ranges from 0.5 to 2 mm, which can ensure that there is enough distance from the doped polysilicon layer to the edge of the battery to avoid short circuit.

[0105] In some embodiments, the silicon substrate has a third edge and a fourth edge that are oppositely disposed along a first direction x (assumed to be a horizontal direction).

[0106] On one side of the silicon substrate, a doped polysilicon layer is formed by LPCVD process, and the layer is divided into a plurality of strip regions along a first direction, including a second strip region and other strip regions that may exist.

[0107] On the side of the doped polysilicon layer away from the silicon substrate, collector electrodes are set. These electrodes are responsible for collecting the current generated by light, and can collect the current through the bus electrode and transmit it to the bus structure such as the welding ribbon or the conductive backplane to export it to the external circuit.

[0108] In other embodiments, the current collected by the collector electrode may also be conducted to an external circuit through a connection point between the battery cell and a bus structure such as a welding ribbon or a conductive back plate.

[0109] The second strip region is specially designed to include a first electrode region and a first non-electrode region. The first electrode region is directly arranged between the collector electrode and the silicon substrate to ensure good electrical contact and current transmission.

[0110] The first non-electrode area is located at the corresponding position of the center line, and its design is to reduce light blocking and optimize current distribution. It is important that the minimum distance from the end of the first non-electrode area to the adjacent third edge or fourth edge is strictly controlled, for example, greater than 0.3 cm. This design reduces the edge effect and improves the photoelectric conversion efficiency.

[0111] For example, at the center line, 1 cm is reserved at each end, and the middle position is not engraved, that is, 1 cm length at each end is laser engraved to show the P zone, and the middle position is not engraved to show the N zone, increasing the area of ​​the N zone. The component process performs 3mm grooves at both ends of the center line for easy cutting, so the engraving range of the P zone at both ends is greater than 3mm.

[0112] Optionally, the minimum distance from the end of the first non-electrode area to the adjacent third edge or fourth edge is greater than the minimum distance from the end of the first electrode area to the adjacent third edge or fourth edge. This can not only reduce light shielding and optimize current distribution, but also avoid edge defect areas, achieve regional optimization, and form an alignment area that is convenient for cell slices, thereby facilitating slices.

[0113] The distance from the end of the first strip region (including the first edge strip region and other parts that may exist) to the adjacent third edge or fourth edge is precisely controlled within the range of 1.1-1.3 mm. This design not only ensures sufficient edge space to reduce mechanical damage, but also optimizes the current path and improves the current collection efficiency.

[0114] This embodiment further improves the performance of the back-contact solar cell through the fine silicon substrate edge design, the electrode layout of the doped polysilicon layer, and the control of the edge distance of the first strip area. The design of the first non-electrode area in the second strip area effectively reduces light shielding and optimizes current distribution; while the precise distance control from the first strip area to the edge ensures the stability and efficiency of current collection. The combined effect of these design elements improves the photoelectric conversion efficiency, current collection performance, and overall stability of the back-contact solar cell.

[0115] In addition to adjusting the N region proportion by the above method, the N region area can also be increased by narrowing the edge main grid. The edge main grid is, for example, a main grid near the border of the P-side pattern.

[0116] For example, the original graphic design of the edge main grid width is 1.2966mm. After adjustment, the edge main grid width is narrowed by 0.15mm to 1.1466mm. The edge main grid can be narrowed by 0.15mm, and the width of the middle main grid is not adjusted. According to the overlap between the edge main grid and the fine grid after moving outward, the starting point offset is adjusted and the length of the fine grid is fine-tuned to achieve the overlap effect and increase the area of ​​the N zone.

[0117] According to the embodiment of the present disclosure, the area ratio of the first doped polysilicon layer in the back contact solar cell is in the range of 50% to 75%. In practice, 50% to 55%, 60% to 65%, 71% to 72%, and 74% to 75% can be selected according to actual needs.

[0118] In some embodiments, the core components of a back-contact solar cell include a silicon substrate and a doped polysilicon layer. The silicon substrate serves as the basis for photoelectric conversion, and its surface is specially treated to prepare for the deposition of the doped polysilicon layer.

[0119] The doped polysilicon layer is a key layer in the back contact solar cell, which is responsible for collecting the photocurrent generated by the silicon substrate and transmitting it to the collector electrode. In order to optimize the performance of the cell, this embodiment pays special attention to the proportion of the doped polysilicon layer in the total cell area.

[0120] After precise calculation and experimental verification, the area ratio of the doped polysilicon layer was set within the range of 71% to 72%, which not only ensures sufficient current collection area, but also avoids excessive material waste and light blocking.

[0121] For example, by changing the size and position of the center line, border line and edge main grid of the graphics, the N area is appropriately increased, the area ratio of the P / N area is optimized, and the collection of electrons and holes is maximized to achieve the purpose of improving battery efficiency. Before optimization, the N area accounted for 71.30%, and after optimization, the N area accounted for 71.70%, an increase of 0.4%.

[0122] When the area ratio of the doped polysilicon layer is between 71% and 72%, the cell can collect photocurrent more effectively, thereby improving the photoelectric conversion efficiency. At the same time, the appropriate area ratio also helps to reduce light shielding, allowing more photons to reach the silicon substrate and be converted into electrical energy.

[0123] In addition, this area ratio also takes into account the cost-effectiveness of the cell and the feasibility of the manufacturing process, ensuring the competitiveness and reliability of back-contact solar cells in practical applications.

[0124] This embodiment achieves a dual improvement in photoelectric conversion efficiency and cost-effectiveness by optimizing the area ratio of the doped polysilicon layer in the back contact solar cell. Controlling the area ratio of the doped polysilicon layer within the range of 71% to 72% not only improves the current collection capacity and photoelectric conversion efficiency of the cell, but also reduces light blocking and material waste.

[0125] According to the embodiments of the present disclosure, the first doped polysilicon layer is an inversion region, which is a region with a conductivity type opposite to that of the substrate. The region other than the inversion region on one side of the solar cell provided with the inversion region is a homotype region, which is a region with the same conductivity type as that of the substrate. The area ratio of the homotype region to the inversion region ranges from 0.3 to 1.5. In practice, 0.39 to 0.40, 0.40 to 0.42, 0.45 to 0.48, 0.49 to 0.51, 0.55 to 0.58, 0.56 to 0.6, 0.65 to 0.8, 0.8 to 1.3, 0.9 to 1.4 or 1.0 to 1.5 can be selected according to actual needs. And the preferred range of the area ratio of the homotype region to the inversion region of different types of batteries is different, such as HPBC batteries prefer to choose a range below 0.5, such as 0.39 to 0.40; TBC batteries and hybrid batteries prefer to choose a range of about 1.0, such as 0.9 to 1.4.

[0126] In some embodiments, the structure of the back contact solar cell is further refined. The silicon substrate serves as the basis of the cell, on which is covered a layer of doped polysilicon layer of two conductivity types. The doped polysilicon layer, for example, includes a first doped polysilicon layer of opposite conductivity type to that of the silicon substrate and a second doped polysilicon layer of the same conductivity type as that of the silicon substrate, which is divided into an inversion region and an isotype region to optimize the photoelectric conversion efficiency. The first doped polysilicon layer and the second doped polysilicon layer can be isolated by an insulating material or an insulating structure. This design helps to more effectively collect photogenerated carriers and improve the photoelectric conversion efficiency. The first doped polysilicon layer and the second doped polysilicon layer can be turned on in a local area and isolated in most areas to reduce the risk of hot spots.

[0127] It should be noted that the first doped polysilicon layer and the second doped polysilicon layer in the embodiment of the present disclosure are used to distinguish the structures of the doped polysilicon layers of different types of back contact solar cells. For example, for a back contact cell (HPBC), the back of the cell of the P-type silicon substrate is provided with only one type of N-type doped polysilicon layer connected to the negative electrode, and the P region is formed by aluminum paste to form a field region. For another back contact cell (TBC), taking the cell of the N-type silicon substrate as an example, in addition to the N-type doped polysilicon layer connected to the negative electrode, the back of the cell is also provided with a P-type doped polysilicon layer connected to the positive electrode. For another back contact cell (hybrid cell), one area is provided with a doped polysilicon layer, and one area is provided with an intrinsic layer and a doped amorphous silicon layer. The first doped polysilicon layer of these cells can refer to the features described above.

[0128] The area outside the inversion region is the isotype region, whose doping type is the same as the conductivity type of the silicon substrate. The isotype region mainly plays a connecting and supporting role in the battery, and also has a certain impact on the photoelectric conversion process. Because the isotype region is the region with the same conductivity type as the substrate, for the back contact battery with trench isolation, the isotype region also includes the substrate area of ​​the isolation trench.

[0129] For example, for a TBC battery with trench isolation, the silicon substrate doping type is N, then the isotype region includes the N-type doped polysilicon covering region and the isolation trench, and the inversion region includes the P-type doped polysilicon covering region.

[0130] In order to balance the photoelectric conversion efficiency and manufacturing cost, this embodiment pays special attention to the area ratio of the inversion region to the homotype region. After a large number of experiments and data analysis, an optimal range is determined: the area ratio of the homotype region to the inversion region is between 0.3 and 1.5.

[0131] The selection of this ratio is based on comprehensive consideration of the photoelectric conversion mechanism, material properties and manufacturing process. The appropriate area ratio can ensure that the inversion region has enough area to collect photogenerated carriers, while the isotype region can also provide sufficient support and connection functions without excessively increasing manufacturing costs or affecting photoelectric conversion efficiency.

[0132] By optimizing the area ratio of the inversion region to the isotype region, the back contact solar cell in this embodiment has been significantly improved in terms of photoelectric conversion efficiency. The inversion region can more effectively collect photogenerated carriers and transmit them to the external circuit, thereby improving the overall performance of the cell.

[0133] At the same time, the appropriate area ratio also ensures the manufacturing cost and reliability of the battery. Although the isotype region does not directly participate in the photoelectric conversion process, it is crucial to the stability and durability of the battery.

[0134] This embodiment achieves dual optimization of photoelectric conversion efficiency and manufacturing cost by optimizing the area ratio of the inversion region to the isotype region in the back contact solar cell. Controlling the area ratio of the isotype region to the inversion region within the range of 0.3 to 1.5 not only improves the photoelectric conversion efficiency of the cell, but also ensures the stability and reliability of the cell.

[0135] Figure 7 The diagram schematically shows a distribution diagram of a first doped polysilicon layer corresponding to a center line of a back surface of a back-contact solar cell according to another embodiment of the present disclosure.

[0136] Another aspect of the present disclosure provides a back contact solar cell, such as Figure 7 As shown, for example, it includes: a silicon substrate 1. A first doped polysilicon layer arranged on one side of the silicon substrate. The silicon substrate 1 includes a first edge and a second edge arranged opposite to each other along the second direction y, and a third edge and a fourth edge arranged opposite to each other along the first direction x. The first doped polysilicon layer includes a plurality of strip regions extending along the first direction and spaced apart along the second direction, the first doped polysilicon strip region adjacent to the first edge is a first edge strip region 31, and the first doped polysilicon strip region adjacent to the second edge is a second edge strip region 32. The width of the first edge strip region 31 and / or the second edge strip region 32 along the second direction is greater than the width of any one of the first doped polysilicon strip regions except the first edge strip region 31 and the second edge strip region 32 along the second direction.

[0137] It should be noted that in this embodiment, the conductivity type of the first doped polysilicon layer is opposite to that of the silicon substrate 1. In other embodiments, the conductivity type of the first doped polysilicon layer can also be the same as that of the silicon substrate 1, and the effect is referred to above and will not be described in detail.

[0138] According to an embodiment of the present disclosure, the distance from the side of the first edge strip region 31 of the solar cell adjacent to the first edge to the first edge is greater than the distance from the side of the second edge strip region 32 adjacent to the second edge to the second edge. Alternatively, the distance from the side of the second edge strip region 32 adjacent to the second edge to the second edge is greater than the distance from the side of the first edge strip region 31 adjacent to the first edge to the first edge. The two edges of the cell are usually damaged to different degrees, so in actual application, better passivation of severely damaged areas can be achieved by adjusting the coverage of doped polysilicon at the two edges.

[0139] For example, a half-cell formed by cutting a whole cell has one edge formed by squaring the silicon ingot and one edge formed by laser cutting. The damage degree and type of the two edges are different, so the distances between the doped polysilicon at the two edges and the edge of the silicon substrate are different. Usually, laser cutting causes greater damage, so the doped polysilicon at the cut edge formed later is closer to the edge to ensure the passivation effect.

[0140] In some embodiments, for example, a piece of P-type single crystal silicon is selected as the silicon substrate, and its surface is cleaned and textured to increase light absorption efficiency. The four edges of the silicon substrate are respectively defined as a first edge (long edge), a second edge (long edge opposite to the first edge), a third edge (short edge) and a fourth edge (short edge opposite to the third edge).

[0141] On one side of the silicon substrate (such as the non-illuminated side), a layer of N-type doped polysilicon layer is deposited by chemical vapor deposition (CVD). This layer is designed as a plurality of strip regions extending along the length direction (i.e., the first direction) of the silicon substrate and spaced apart along the width direction (i.e., the second direction). The width of each strip region is about 1 mm, but the first edge strip region adjacent to the first edge and the second edge strip region adjacent to the second edge are designed to be doubled in width, i.e., 2 mm, to enhance the current collection efficiency of the edge region.

[0142] Metallized electrodes are further fabricated on the doped polysilicon layer, such as bus electrodes and collector electrodes, which form good ohmic contacts with the doped polysilicon layer to ensure effective current collection. Subsequently, passivation layer deposition and opening of holes in the P-region passivation layer are performed to complete the fabrication of the back-contact solar cell.

[0143] For example, N-type polysilicon can also be used as the substrate material, and the surface cleaning and texturing treatment are also performed. The edge definition is the same as the above embodiment.

[0144] On one side of the N-type silicon substrate, an intrinsic polysilicon layer is deposited and P-type doped to form a doped polysilicon layer. This layer is also designed as multiple strips, but in this embodiment, only the second edge strip is widened to 1.5 mm, while the first edge strip and other intermediate strips maintain a standard width of 1 mm. This design is intended to optimize current collection at a specific edge while controlling costs.

[0145] Make metallized electrodes, perform packaging, and complete component production.

[0146] The above two embodiments demonstrate different design schemes for doping the polysilicon layer in the back contact solar cell. By adjusting the width distribution of the strip area, especially widening the edge strip area, the current collection efficiency can be effectively improved and the battery performance can be optimized.

[0147] Figure 8 The diagram schematically shows the distribution of the collector electrode on the doped polysilicon layer at the back edge of a back-contact solar cell according to another embodiment of the present disclosure.

[0148] According to the embodiments of the present disclosure, Figure 8 As shown, the back contact solar cell also includes, for example: a collector electrode 4 arranged on the side of the first doped polysilicon layer away from the silicon substrate. The first edge strip region 31 includes a second electrode region arranged between the collector electrode 4 and the silicon substrate 1, and a second non-electrode region arranged between the first edge and the second electrode region, the second electrode region is at least two, and the second non-electrode region connects the second electrode region to form an integral structure. And / or the second edge strip region 32 includes a third electrode region arranged between the collector electrode 4 and the silicon substrate 1 and a third non-electrode region arranged between the second edge and the third electrode region, the third electrode region is at least two, and the third non-electrode region connects the third electrode region to form an integral structure.

[0149] In some embodiments, for example, P-type single crystal silicon is selected as the silicon substrate, and conventional cleaning and texturing processes are performed.

[0150] On one side of the silicon substrate, an intrinsic polysilicon layer is deposited by chemical vapor deposition and doped to form an N-type doped polysilicon layer. The layer is precisely divided into a plurality of strip regions, including a first edge strip region and a second edge strip region arranged along the edge, and an intermediate strip region located between the two.

[0151] On the side of the doped polysilicon layer away from the silicon substrate, collector electrodes are made by photolithography and metal deposition technology. These electrodes form a good ohmic contact with the doped polysilicon layer to collect and conduct current.

[0152] At least two second electrode regions are designed in the first edge strip region, and these electrode regions are directly connected to the collector electrode for collecting current.

[0153] A second non-electrode region is provided between the first edge and the second electrode region. These non-electrode regions are not directly involved in the collection of current, but they play a role in connecting and supporting the second electrode region to form an overall strip structure. The presence of the second non-electrode region can also reduce light shielding and improve photoelectric conversion efficiency.

[0154] Similar to the first edge strip region, the second edge strip region also includes at least two third electrode regions and a third non-electrode region located between the second edge and the third electrode regions. The third electrode region is connected to the collector electrode, and the third non-electrode region connects these electrode regions to form a continuous overall structure.

[0155] After the electrode layout is completed, the passivation layer is deposited and the hole opening process is carried out to protect the silicon substrate and expose the necessary electrode contact points.

[0156] By optimizing the thickness of the doped polysilicon layer, the doping concentration and the geometry of the electrode, the photoelectric conversion efficiency and stability of the back-contact solar cell can be further improved.

[0157] This embodiment demonstrates a complex electrode layout design in a back-contact solar cell. By arranging multiple electrode regions and non-electrode regions in the first edge strip region and the second edge strip region, and connecting these regions into an overall structure in a specific manner, the current collection efficiency is improved and the photoelectric conversion performance is optimized. This design not only enhances the current collection capability of the edge region, but also improves the overall performance of the cell by reducing light shielding and optimizing the current path.

[0158] Understandably, Figure 7 and Figure 8 The back contact solar cell shown is a Figure 2 A back-contact solar cell is shown cut in half along the center line. Figure 2 The above-mentioned other solutions related to the back-contact solar cell shown can be referred to and expanded, and will not be repeated here.

[0159] The electrical performance data of the solar cell after adjustment according to the solution of the embodiment of the present disclosure is shown in Table 1.

[0160] Table 1 Comparative experimental electrical performance data

[0161]

[0162] As can be seen from Table 1, the P-region and N-region area ratio optimization process of the embodiment of the present disclosure, the obtained battery cell tracking silk screen test is about 0.023% higher in efficiency than the battery cell of the control group that has not undergone process optimization.

[0163] It can be understood that the back contact solar cell disclosed in the present invention can be a HPBC (Heterojunction Passivated Back Contact) cell, a TBC (Tunnel Oxide Passivated Contact) cell, a hybrid cell, and the like.

[0164] For example, HPBC cells combine heterojunction and passive back contact technologies. The silicon substrate can be P-type or N-type single crystal silicon, and the surface is cleaned and textured.

[0165] The back side adopts a back contact design, that is, the conductivity type of the doped polysilicon layer is opposite to that of the silicon substrate, and is divided into multiple strip areas, including an electrode area with widened edges and a non-electrode area in the middle.

[0166] The front electrode is usually designed as a current collecting electrode to reduce light obstruction while ensuring good current collection.

[0167] A collector electrode is arranged on the back side to form an ohmic contact with the strip area of ​​the doped polysilicon layer to realize the collection and conduction of current.

[0168] For example, high-quality packaging materials (such as EVA or POE) can be used to cover the battery surface to protect the battery from environmental erosion. The cover can be made of low-iron tempered glass to improve light transmittance and mechanical strength.

[0169] TBC cells use tunnel oxide passivation contact technology to achieve efficient carrier transport and interface passivation by introducing an ultra-thin tunnel oxide layer between the silicon substrate and the metal electrode.

[0170] The silicon substrate can also be P-type or N-type single crystal silicon, with a doped polysilicon layer designed on the back, but the electrode layout and contact method may be different from HPBC.

[0171] The back electrode forms a low-resistance contact with the silicon substrate through a tunnel oxide layer, reducing contact resistance and recombination loss.

[0172] The electrode layout may be more complex to optimize current collection and distribution.

[0173] TBC cells have higher open circuit voltage and fill factor, which improves the photoelectric conversion efficiency. The tunnel oxide layer also provides a good interface passivation effect, reducing the recombination loss of carriers.

[0174] The design of the package and cover is similar to that of HPBC and TBC batteries, and the back package layer and cover can also be replaced by an integrated conductive back sheet.

[0175] Another aspect of the present disclosure provides a photovoltaic module, comprising: a plurality of back-contact solar cells according to any embodiment of the present disclosure; an encapsulation layer for covering surfaces of the plurality of back-contact solar cells; and a cover plate for covering surfaces of the encapsulation layer away from the plurality of back-contact solar cells.

[0176] In some embodiments, a high-efficiency back-contact photovoltaic module is introduced, which combines the design advantages of the above-mentioned back-contact solar cells and ensures high performance and long-term stability of the module through a carefully designed encapsulation layer and cover structure.

[0177] Using the back-contact solar cells described in the above embodiments as basic units, these cells have an optimized doped polysilicon layer, a complex electrode layout, and a highly efficient current collection mechanism.

[0178] Multiple back-contact solar cells are connected in series or parallel to form a solar cell array. Each cell is connected to each other through the collector electrode on its back to ensure smooth current transmission.

[0179] For example, high-quality transparent packaging materials such as ethylene-vinyl acetate copolymer (EVA) or polyolefin (POE) are selected and evenly covered on the surface of the solar cell array through a vacuum lamination process.

[0180] The encapsulation layer not only protects the solar cells from environmental erosion (such as moisture, dust and ultraviolet rays), but also has good light transmittance to ensure that sunlight can fully irradiate the solar cells.

[0181] For example, low-iron tempered glass is used as the cover material, which has high light transmittance, high strength and good weather resistance.

[0182] The cover plate is tightly fixed to the encapsulation layer through a frame (such as an aluminum alloy frame) to form a sealed photovoltaic module unit. The cover plate not only further enhances the mechanical strength of the module, but also prevents direct impact and damage from external objects.

[0183] Due to the use of back-contact solar cells, the photovoltaic module has higher photoelectric conversion efficiency and better thermal stability. The back-contact structure reduces the electrode shading on the front surface and improves the light absorption efficiency; at the same time, the electrode layout on the back optimizes the current path and reduces resistance loss.

[0184] The photovoltaic module can be widely used in rooftop installation, ground power stations, photovoltaic building integration (BIPV) and other fields, providing efficient and reliable solutions for the utilization of renewable energy.

[0185] In order to further improve the power generation efficiency of the components, a reflective film or heat dissipation structure can be installed on the back of the components to effectively manage scattered light and heat.

[0186] The edges of the components can also be sealed for waterproofing, ensuring they remain in good working condition even in adverse weather conditions.

[0187] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.

[0188] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.

[0189] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the attached claims, the disclosure is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the attached claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the disclosure.

[0190] In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", as explained in terms of "including," used as a transitional word in the claims. Any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0191] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; A first doped polysilicon layer disposed on one side of the silicon substrate; Wherein, the silicon substrate comprises a first edge and a second edge arranged opposite to each other along a second direction, and a center line extending along the first direction and located between the first edge and the second edge; The first doped polysilicon layer includes a plurality of strip regions extending along the first direction and spaced apart along the second direction, the strip region of the first doped polysilicon layer arranged corresponding to the center line is the second strip region, the remaining strip regions of the first doped polysilicon layer are the first strip regions, and the width of the second strip region along the second direction is greater than the width of the first strip region along the second direction; The first direction intersects with the second direction.

2. The solar cell according to claim 1, characterized in that Also includes: A collector electrode disposed on a side of the first doped polysilicon layer away from the silicon substrate; The second strip region includes a first electrode region arranged between the collector electrode and the silicon substrate, and a first non-electrode region arranged at a position corresponding to the center line. There are at least two first electrode regions, and the first non-electrode regions connect the first electrode regions to form an integral structure.

3. The solar cell according to claim 1, characterized in that Slice alignment areas are provided at two ends of the second strip area along the first direction.

4. The solar cell according to claim 1, characterized in that The first doped polysilicon strip region where the first strip region is adjacent to the first edge is a first edge strip region, and the first doped polysilicon strip region where the first strip region is adjacent to the second edge is a second edge strip region; A width of the first edge strip region and / or the second edge strip region along the second direction is greater than a width of any strip region of the first strip regions except the first edge strip region and the second edge strip region along the second direction.

5. The solar cell according to claim 4, characterized in that: Also includes: A collector electrode disposed on a side of the first doped polysilicon layer away from the silicon substrate; The first edge strip region includes a second electrode region arranged between the collector electrode and the silicon substrate, and a second non-electrode region arranged between the first edge and the second electrode region, the number of the second electrode regions is at least two, and the second non-electrode region is connected to the second electrode region to form an integral structure; and / or The second edge strip region includes a third electrode region arranged between the collector electrode and the silicon substrate, and a third non-electrode region arranged between the second edge and the third electrode region. There are at least two third electrode regions, and the third non-electrode regions connect the third electrode regions to form an integral structure.

6. The solar cell according to claim 1, characterized in that The first doped polysilicon strip region adjacent to the first edge of the first strip region is a first edge strip region, and a width of the first edge strip region along the second direction is smaller than a width of the second strip region along the second direction; and / or The first doped polysilicon strip region of the first strip region adjacent to the second edge is a second edge strip region, and a width of the second edge strip region along the second direction is smaller than a width of the second strip region along the second direction.

7. The solar cell according to claim 1, characterized in that The silicon substrate further includes a third edge and a fourth edge disposed opposite to each other along the first direction, and the solar cell further includes: A collector electrode disposed on a side of the first doped polysilicon layer away from the silicon substrate; The second strip region includes a first electrode region disposed between the collector electrode and the silicon substrate and a first non-electrode region disposed at a position corresponding to the center line; The distance from the end of the first non-electrode region to the adjacent third edge is greater than the distance from the end of the first strip region to the adjacent third edge; And / or, the distance from the end of the first non-electrode area to the adjacent third edge is greater than the distance from the end of the first electrode area to the adjacent third edge; And / or, the distance from the end of the first strip region to the adjacent third edge is less than or equal to the distance from the end of the first electrode region to the adjacent third edge.

8. The solar cell according to claim 7, characterized in that: The distance from the end of the first non-electrode region to the adjacent fourth edge is greater than the distance from the end of the first strip region to the adjacent fourth edge; And / or, the distance from the end of the first non-electrode area to the adjacent fourth edge is greater than the distance from the end of the first electrode area to the adjacent fourth edge; And / or, the distance from the end of the first strip region to the adjacent fourth edge is less than or equal to the distance from the end of the first electrode region to the adjacent fourth edge.

9. The solar cell according to claim 1, characterized in that: The conductivity type of the first doped polysilicon layer is opposite to that of the silicon substrate, the first doped polysilicon layer is an inversion zone, and the area other than the inversion zone on one side of the solar cell provided with the inversion zone is a homotype zone, and the area ratio of the homotype zone to the inversion zone ranges from 0.3 to 1.

5.

10. A solar cell, characterized in that: include: Silicon substrate; A first doped polysilicon layer disposed on one side of the silicon substrate; Wherein, the silicon substrate comprises a first edge and a second edge arranged opposite to each other along the second direction, and a third edge and a fourth edge arranged opposite to each other along the first direction; The first doped polysilicon layer includes a plurality of strip regions extending along the first direction and spaced apart along the second direction, wherein the first doped polysilicon strip region adjacent to the first edge is a first edge strip region, and the first doped polysilicon strip region adjacent to the second edge is a second edge strip region; The width of the first edge strip region and / or the second edge strip region along the second direction is greater than the width of any strip region of the first doped polysilicon strip region except the first edge strip region and the second edge strip region along the second direction.

11. The solar cell according to claim 10, characterized in that The distance from the side of the first edge strip region adjacent to the first edge to the first edge is greater than the distance from the side of the second edge strip region adjacent to the second edge to the second edge; or, A distance from a side of the second edge strip region adjacent to the second edge to the second edge is greater than a distance from a side of the first edge strip region adjacent to the first edge to the first edge.

12. The solar cell according to claim 10, characterized in that: Also includes: A collector electrode disposed on a side of the first doped polysilicon layer away from the silicon substrate; The first edge strip region includes a second electrode region arranged between the collector electrode and the silicon substrate, and a second non-electrode region arranged between the first edge and the second electrode region, the number of the second electrode regions is at least two, and the second non-electrode region is connected to the second electrode region to form an integral structure; and / or The second edge strip region includes a third electrode region arranged between the collector electrode and the silicon substrate and a third non-electrode region arranged between the second edge and the third electrode region. There are at least two third electrode regions, and the third non-electrode regions connect the third electrode regions to form an integral structure.

13. A photovoltaic module, characterized in that: include: A plurality of solar cells according to any one of claims 1 to 12; An encapsulation layer, used to cover the surface of the plurality of solar cells; A cover plate is used to cover the surface of the encapsulation layer facing away from the plurality of solar cells.

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