Semiconductor power device and electronic device

Abstract

The invention discloses a semiconductor power device and an electronic device. The semiconductor power device comprises a substrate, a drift region, a base region, an active gate, two virtual gates and a carrier storage region, the base body is provided with a first surface and a second surface which are opposite; the drift region is arranged in the substrate and is positioned between the first surface and the second surface; the base region is arranged on one side of the drift region facing the first surface; an emitter region, a contact region and a preset injection region are arranged in the base region; the active gate and the virtual gate penetrate through the base region and extend to the drift region; the active gate is located between the two virtual gates; the carrier storage region is arranged on one side, facing the base region, in the drift region, and is positioned on two sides of the active gate and the virtual gate; the drift region comprises a first drift region which penetrates through the carrier storage region to be in contact with the base region, and the first drift region and the preset injection region are located on the same side, away from the active gate, of the virtual gate. The turn-off loss of the semiconductor power device is reduced while the conduction voltage drop of the semiconductor power device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and an electronic device. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is used in various electronic devices such as but not limited to terminal equipment and inverters due to its advantages such as high efficiency, high voltage resistance, large current handling capability and fast switching speed.

[0003] As a commonly used power electronic device, the performance of IGBT is affected by multiple factors, among which the on-state voltage drop and turn-off loss are two important indicators.

[0004] However, current IGBTs cannot simultaneously achieve low on-state voltage drop and low turn-off loss. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] The present application aims to address the deficiencies in the prior art, and its main purpose is to provide a semiconductor power device that reduces the turn-off loss of the semiconductor power device while reducing the on-state voltage drop of the semiconductor power device.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In view of the existing problems, an embodiment of the present invention provides a semiconductor power device on the one hand, which includes: a substrate, a drift region of a first conductivity type, a base region of a second conductivity type, an active gate, two virtual gates, and a carrier storage region of the first conductivity type; the substrate has a first surface and a second surface opposite to each other; the drift region is arranged in the substrate and is located between the first surface and the second surface; the base region is arranged on the side of the drift region facing the first surface; an emitter region of the first conductivity type, and a contact region and a preset injection region of the second conductivity type are arranged in the base region; the active gate penetrates the base region and extends to the drift region; the emitter region and the contact region are located on both sides of the active gate; the virtual gate penetrates the base region and extends to the drift region; the active gate and the two virtual gates are distributed at intervals, and the active gate is located between the two virtual gates; the carrier storage region is arranged in the drift region on the side facing the base region, and is located on both sides of the active gate and the virtual gate; the drift region includes a first drift region that penetrates the carrier storage region to contact the base region, and the first drift region and the preset injection region are both located on the same side of the virtual gate away from the active gate.

[0009] The above technical solution has the following beneficial effects: by setting a preset injection region in the base region on the side of the virtual gate away from the active gate, and also setting a first drift region that penetrates the carrier storage region to contact the base region on the same side of the virtual gate away from the active gate, the semiconductor power device can extract carriers by using the carrier extraction channel based on the preset injection region in addition to the carrier extraction channel based on the contact region when it is turned off, so that the carriers in the drift region can be extracted to the base region faster, and the turn-off tailing effect of the semiconductor power device can be reduced, thereby reducing the turn-off loss of the semiconductor power device. It is also possible to enhance the conductivity modulation effect in the drift region when the semiconductor power device is turned on through the carrier storage region to reduce the conduction voltage drop of the semiconductor power device. Thereby, while reducing the conduction voltage drop of the semiconductor power device, the turn-off loss of the semiconductor power device is reduced, and the conduction voltage drop and low turn-off loss of the semiconductor power device are better balanced. Furthermore, the virtual gate can help increase the capacitance between the emitter and the collector when the semiconductor power device is turned off, thereby reducing the leakage current when the semiconductor power device is turned off.

[0010] In some embodiments, another semiconductor power device is provided, wherein the doping concentration of the preset injection region is greater than the doping concentration of the base region, and at least a portion of the preset injection region is located opposite to the first drift region.

[0011] The above technical solution has the following beneficial effects: by making the doping concentration of the preset injection region greater than the doping concentration of the base region, and the first drift region and the preset injection region at least partially opposite to each other, the distance between the preset injection region and the first drift region can be shortened, and the length of the extraction channel for the preset injection region to extract carriers from the drift region can be shortened, thereby improving the carrier extraction efficiency, further reducing the turn-off tailing effect of the semiconductor power device, and further reducing the turn-off loss of the semiconductor power device.

[0012] In some embodiments, another semiconductor power device is provided, wherein an extension direction of a preset implantation region is parallel to an extension direction of a dummy gate.

[0013] The above technical solution has the following beneficial effects: by setting a preset injection region extending parallel to the virtual gate, the area characteristics of the region where the preset injection region is relative to the first drift region can be increased, and the cross-sectional area of ​​the extraction channel for extracting carriers from the drift region by the preset injection region can be increased, thereby improving the carrier extraction efficiency, further reducing the turn-off tailing effect of the semiconductor power device, and further reducing the turn-off loss of the semiconductor power device.

[0014] In some embodiments, another semiconductor power device is provided, wherein a preset implantation region is spaced apart from an adjacent dummy gate.

[0015] The above technical solution has the following beneficial effects: by spacing the preset injection region and the adjacent virtual gate, no carrier channel can be formed between the preset injection region and the virtual gate, thereby reducing the influence of the additional preset injection region on the virtual gate function.

[0016] In some embodiments, another semiconductor power device is provided, wherein an extension direction of the first drift region is parallel to an extension direction of the preset injection region, and a width of the first drift region is equal to a width of the preset injection region.

[0017] The above technical solution has the following beneficial effects: by utilizing the first drift region and the preset injection region to be arranged in parallel and with equal widths, the area of ​​the relative position of the first drift region and the preset injection region can be increased while making the distribution area of ​​the carrier storage region on the side of the virtual gate away from the active gate as large as possible, thereby reducing the turn-off tailing effect of the semiconductor power device to reduce the turn-off loss of the semiconductor power device, while also reducing the conduction voltage drop of the semiconductor power device, achieving a balance between the turn-off loss and the conduction voltage drop.

[0018] In some embodiments, another semiconductor power device is provided, wherein a preset injection region and a first drift region are disposed on a side of each of the two virtual gates facing away from the active gate.

[0019] The above technical solution has the following beneficial effects: by providing a preset injection region and a corresponding first drift region on the side of each of the two virtual gates away from the active gate, the area of ​​the preset injection region and the first drift region can be expanded, thereby improving the effect of reducing the turn-off tailing effect of the semiconductor power device, thereby improving the effect of reducing the turn-off loss of the semiconductor power device.

[0020] In some embodiments, another semiconductor power device is provided, wherein the doping concentration of the contact region is greater than the doping concentration of the base region; the drift region also includes a second drift region that penetrates the carrier storage region to contact the base region, and the second drift region is located on both sides of the active gate.

[0021] The above technical solution has the following beneficial effects: by setting a second drift region between two virtual gates so that the second drift region is in contact with the base region, another carrier extraction channel is added when the semiconductor power device is turned off, so that the carriers in the drift region can be extracted to the base region more quickly, thereby reducing the turn-off tailing effect of the semiconductor power device, thereby reducing the turn-off loss of the semiconductor power device.

[0022] In some embodiments, another semiconductor power device is provided, wherein a predetermined implantation region is used to electrically connect an emitter metal layer of the semiconductor power device.

[0023] The above technical solution has the following beneficial effects: by electrically connecting the preset injection region to the emitter metal layer of the semiconductor power device, the emitter metal layer emits carriers of the first conductivity type and carriers of the second conductivity type, and can also enable the semiconductor power device to extract carriers in the drift region to the base region through multiple carrier extraction channels when it is turned off, thereby improving the effect of reducing the turn-off tailing effect of the semiconductor power device, thereby improving the effect of reducing the turn-off loss of the semiconductor power device.

[0024] In some embodiments, another semiconductor power device is provided, wherein the first conductivity type is an N conductivity type, and the second conductivity type is a P conductivity type.

[0025] The above technical solution has the following beneficial effects: by setting an N-conductivity type drift region, an emission region and a carrier storage region, and a P-conductivity type base region, a contact region and a preset injection region, the characteristic that the mobility of electrons is higher than that of holes is utilized, thereby improving the voltage resistance of the semiconductor power device and reducing the on-resistance of the semiconductor power device.

[0026] In some embodiments, another semiconductor power device is provided, wherein the doping concentrations of the emission region and the carrier storage region are both greater than the doping concentration of the drift region.

[0027] The above technical solution has the following beneficial effects: by making the doping concentration of the emission region and the carrier storage region greater than the doping concentration of the drift region, the conductivity modulation effect in the drift region when the semiconductor power device is turned on can be enhanced, thereby reducing the on-state voltage drop of the semiconductor power device.

[0028] A second aspect of an embodiment of the present invention provides an electronic device, which includes the semiconductor power device as described above.

[0029] The above technical solution has the following beneficial effects: by setting a preset injection region in the base region on the side of the virtual gate away from the active gate, and also setting a first drift region that penetrates the carrier storage region to contact the base region on the same side of the virtual gate away from the active gate, the semiconductor power device can extract carriers by using the carrier extraction channel based on the preset injection region in addition to the carrier extraction channel based on the contact region when it is turned off, so that the carriers in the drift region can be extracted to the base region faster, and the turn-off tailing effect of the semiconductor power device can be reduced, thereby reducing the turn-off loss of the semiconductor power device. It is also possible to enhance the conductivity modulation effect in the drift region when the semiconductor power device is turned on through the carrier storage region to reduce the conduction voltage drop of the semiconductor power device. Thereby, while reducing the conduction voltage drop of the semiconductor power device, the turn-off loss of the semiconductor power device is reduced, and the conduction voltage drop and low turn-off loss of the semiconductor power device are better balanced. It can also help the virtual gate to increase the capacitance between the emitter and the collector when the semiconductor power device is turned off, and reduce the leakage current when the semiconductor power device is turned off, thereby reducing the power consumption of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0031] In the attached figure:

[0032] Figure 1 A schematic diagram of a three-terminal electrode metal layer of a semiconductor power device of the present invention is shown;

[0033] Figures 2 to 6 Schematic diagrams showing semiconductor power devices according to different specific embodiments of the present invention;

[0034] Figures 7 to 10 A schematic diagram of a semiconductor power device obtained by sequentially implementing various steps in a semiconductor power device manufacturing process is shown.

[0035] Reference numerals:

[0036] 10-Drift region 11-First drift region

[0037] 12- Second drift region 20- Base region

[0038] 31-active gate 32-virtual gate

[0039] 40-Emission zone 50-Contact zone

[0040] 51-Part 1 52-Part 2

[0041] 60-preset injection area 70-carrier storage area

[0042] 80-field stop region 90-collector region DETAILED DESCRIPTION

[0043] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0044] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated or otherwise) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] First, let’s introduce the application scenarios of semiconductor power devices. Figure 1 , the semiconductor power device can be a switching device such as but not limited to IGBT, which is a three-terminal switching device, including a gate metal layer, a collector metal layer and an emitter metal layer. The gate metal layer is used to electrically connect the control power supply, and the emitter metal layer and the collector metal layer are electrically connected between the power supply and the load. When the emitter metal layer and the collector metal layer are controlled to be turned on by the gate metal layer, the power supply can supply power to the load; when the emitter metal layer and the collector metal layer are controlled to be turned off by the gate metal layer, the power supply stops supplying power to the load. The switching device can be applied to electronic products such as but not limited to laptops, desktop computers, tablet computers, mobile terminals, smart wearable devices, inverters, power factor correction circuits, voltage converters, etc.

[0049] In some embodiments, a semiconductor power device is provided, referring to Figure 2The semiconductor power device comprises: a substrate, a drift region 10 of a first conductivity type, a base region 20 of a second conductivity type, an active gate 31, two virtual gates 32, and a carrier storage region 70 of a first conductivity type; the substrate has a first surface and a second surface opposite to each other; the drift region 10 is arranged in the substrate and between the first surface and the second surface; the base region 20 is arranged on the side of the drift region 10 facing the first surface; an emitter region 40 of a first conductivity type, a contact region 50 of a second conductivity type and a preset injection region 60 are arranged in the base region 20; the active gate 31 penetrates the base region 20 and extends to the drift ... The drift region 10 includes an emitter region 40 and a contact region 50 located on both sides of the active gate 31; the virtual gate 32 penetrates the base region 20 and extends to the drift region 10; the active gate 31 and the two virtual gates 32 are spaced apart, and the active gate 31 is located between the two virtual gates 32; the carrier storage region 70 is arranged in the drift region 10 on the side facing the base region 20, and is located on both sides of the active gate 31 and the virtual gate 32; the drift region 10 includes a first drift region 11 penetrating the carrier storage region 70 to contact the base region 20, and the first drift region 11 and the preset injection region 60 are both located on the same side of the virtual gate 32 away from the active gate 31.

[0050] The above technical solution has the following beneficial effects: by setting a preset injection region 60 in the base region 20 on the side of the virtual gate 32 away from the active gate 31, and also setting a first drift region 11 that penetrates the carrier storage region 70 to contact the base region 20 on the same side of the virtual gate 32 away from the active gate 31, the semiconductor power device can extract carriers by using the carrier extraction channel based on the preset injection region 60 in addition to the carrier extraction channel based on the contact region 50 when it is turned off, and can extract carriers from the drift region 10 to the base region 20 more quickly, reducing the turn-off tailing effect of the semiconductor power device, thereby reducing the turn-off loss of the semiconductor power device. In addition, the conductivity modulation effect in the drift region 10 when the semiconductor power device is turned on can be enhanced through the carrier storage region 70 to reduce the turn-on voltage drop of the semiconductor power device. Thus, the on-state voltage drop of the semiconductor power device is reduced while the off-state loss of the semiconductor power device is reduced, and the on-state voltage drop and the low off-state loss of the semiconductor power device are better balanced. In addition, the virtual gate 32 can increase the capacitance between the emitter and the collector when the semiconductor power device is turned off, and reduce the leakage current when the semiconductor power device is turned off.

[0051] In some embodiments, the above-mentioned substrate may be a semiconductor substrate, and the semiconductor substrate may be a Si-containing semiconductor substrate. The term "Si-containing semiconductor substrate" refers to any semiconductor material containing at least silicon. Illustrative examples of Si-containing semiconductor materials that can be used as substrates include: Si, SiGe, SiC, SiGeC, silicon on insulator (SOI) or SiGe on insulator (SGOI), but are not limited thereto. Exemplarily, the semiconductor substrate may be made of single crystal silicon material.

[0052] In some embodiments, the gate metal layer and the emitter metal layer are located on a first surface side of the substrate, and the collector metal layer is located on a second surface side of the substrate.

[0053] In some embodiments, reference Figure 2 The base region 20 is arranged close to the gate metal layer and the emitter metal layer of the semiconductor power device.

[0054] In some embodiments, reference Figure 2 The arrangement direction between the active gate 31 and the two dummy gates 32 is perpendicular or substantially perpendicular to the extension direction of the active gate 31 and the dummy gate 32 .

[0055] For example, refer to Figure 2 The arrangement direction between the active gate 31 and the two dummy gates 32 is the x direction, the extension direction of the active gate 31 and the dummy gate 32 is the y direction, and the x direction and the y direction are perpendicular or substantially perpendicular.

[0056] In some embodiments, reference Figure 2 , the arrangement direction and extension direction between the active gate 31 and the two dummy gates 32 are perpendicular to the stacking direction between the drift region 10 and the base region 20. That is, the arrangement direction between the active gate 31 and the two dummy gates 32, the extension direction of the active gate 31 and the dummy gate 32, and the stacking direction between the drift region 10 and the base region 20 are perpendicular to each other.

[0057] For example, refer to Figure 2 The arrangement direction between the active gate 31 and the two dummy gates 32 is the x direction, the extension direction of the active gate 31 and the dummy gate 32 is the y direction, and the stacking direction between the drift region 10 and the base region 20 is the z direction, and these three directions are perpendicular to each other.

[0058] In some embodiments, another semiconductor power device is provided, referring to Figure 2 The doping concentration of the preset injection region 60 is greater than the doping concentration of the base region 20 , and at least a portion of the preset injection region 60 is opposite to the first drift region 11 .

[0059] The above technical solution has the following beneficial effects: by making the doping concentration of the preset injection region 60 greater than the doping concentration of the base region 20, and the first drift region 11 being at least partially opposite to the preset injection region 60, the distance between the preset injection region 60 and the first drift region 11 can be shortened, and the length of the extraction channel for the preset injection region 60 to extract carriers from the drift region 10 can be shortened, thereby improving the carrier extraction efficiency, further reducing the turn-off tailing effect of the semiconductor power device, and further reducing the turn-off loss of the semiconductor power device.

[0060] In some embodiments, another semiconductor power device is provided, referring to Figure 2 , the extension direction of the preset injection region 60 is parallel to the extension direction of the virtual gate 32. For example, referring to Figure 2 , the preset implantation region 60 and the dummy gate 32 both extend along the y direction.

[0061] The above technical solution has the following beneficial effects: by setting a preset injection region 60 extending parallel to the virtual gate 32, the area characteristics of the region where the preset injection region 60 is relative to the first drift region 11 can be increased, and the cross-sectional area of ​​the extraction channel for extracting carriers from the drift region 10 by the preset injection region 60 is increased, thereby improving the carrier extraction efficiency, further reducing the turn-off tailing effect of the semiconductor power device, and further reducing the turn-off loss of the semiconductor power device.

[0062] In some embodiments, another semiconductor power device is provided, referring to Figure 2 The preset injection region 60 is spaced apart from the adjacent dummy gate 32 .

[0063] The above technical solution has the following beneficial effects: by spacing the preset injection region 60 and the adjacent virtual gate 32 , no carrier channel can be formed between the preset injection region 60 and the virtual gate 32 , thereby reducing the influence of the additional preset injection region 60 on the function of the virtual gate 32 .

[0064] In some embodiments, another semiconductor power device is provided, referring to Figure 2 , the extension direction of the first drift region 11 is parallel to the extension direction of the preset injection region 60, and the width of the first drift region 11 is equal to the width of the preset injection region 60. For example, referring to Figure 2 , the first drift region 11 and the preset injection region 60 both extend along the y direction.

[0065] It should be noted that the width of the first drift region 11 refers to the distance between the two side walls of the first drift region 11 in the arrangement direction between the active gate 31 and the two dummy gates 32, that is, the distance between the two side walls of the first drift region 11 in the x direction. Figure 2D1 in represents the width of the first drift region 11. The width of the preset injection region 60 refers to the distance between the two side walls of the preset injection region 60 in the arrangement direction between the active gate 31 and the two dummy gates 32, that is, the distance between the two side walls of the preset injection region 60 in the x direction, as shown in FIG. Figure 2 D2 in FIG. 6 represents the width of the predetermined implantation region 60 .

[0066] The above technical solution has the following beneficial effects: by utilizing the first drift region 11 and the preset injection region 60 to be arranged in parallel and with equal widths, the area of ​​the relative position of the first drift region 11 and the preset injection region 60 can be increased while making the distribution area of ​​the carrier storage region 70 on the side of the virtual gate 32 away from the active gate 31 as large as possible, thereby reducing the turn-off tailing effect of the semiconductor power device to reduce the turn-off loss of the semiconductor power device, while also reducing the conduction voltage drop of the semiconductor power device, achieving a balance between the turn-off loss and the conduction voltage drop.

[0067] In some embodiments, another semiconductor power device is provided, referring to Figure 3 A preset injection region 60 and a first drift region 11 are disposed on a side of each of the two dummy gates 32 away from the active gate 31 .

[0068] The above technical solution has the following beneficial effects: by providing a preset injection region 60 and a corresponding first drift region 11 on the side of each virtual gate 32 in the two virtual gates 32 away from the active gate 31, the area of ​​the preset injection region 60 and the first drift region 11 can be expanded, thereby improving the effect of reducing the turn-off tailing effect of the semiconductor power device, thereby improving the effect of reducing the turn-off loss of the semiconductor power device.

[0069] In other embodiments, reference Figure 1 and Figure 4 , the preset injection region 60 and the corresponding first drift region 11 may be provided only on the side of one of the two dummy gates 32 away from the active gate 31 , while the preset injection region 60 is not provided on the side of the other dummy gate 32 away from the active gate 31 .

[0070] In some embodiments, reference Figure 2 and Figure 3 The carrier storage region 70 located between the two virtual gates 32 may no longer be penetrated by the drift region 10, so that the base region 20 and the drift region 10 between the two virtual gates 32 are completely separated by the carrier storage region 70, so as to increase the area of ​​the carrier storage region 70, thereby enhancing the conductivity modulation effect in the drift region 10 when the semiconductor power device is turned on, and reducing the on-state voltage drop of the semiconductor power device.

[0071] In some other embodiments, another semiconductor power device is provided, referring to Figure 4 and Figure 5 The doping concentration of the contact region 50 is greater than the doping concentration of the base region 20 . The drift region 10 further includes a second drift region 12 penetrating the carrier storage region 70 to contact the base region 20 . The second drift region 12 is located at both sides of the active gate 31 .

[0072] The above technical solution has the following beneficial effects: by setting the second drift region 12 between the two virtual gates 32, the second drift region 12 is in contact with the base region 20, so that another carrier extraction channel is added when the semiconductor power device is turned off, so that the carriers in the drift region 10 can be extracted to the base region 20 more quickly, thereby reducing the turn-off tailing effect of the semiconductor power device, thereby reducing the turn-off loss of the semiconductor power device.

[0073] In some embodiments, another semiconductor power device is provided, referring to Figure 4 , at least a portion of the contact region 50 is located opposite to the second drift region 12 .

[0074] The above technical solution has the following beneficial effects: by setting a contact region 50 with the same doping type as the base region 20 and a higher doping concentration than the base region 20, and the second drift region 12 is at least partially opposite to the contact region 50, the distance between the contact region 50 and the second drift region 12 can be shortened, and the length of the extraction channel for the contact region 50 to extract carriers from the drift region 10 can be shortened, thereby shortening the time for the contact region 50 to extract carriers from the drift region 10 through the second drift region 12, thereby improving the carrier extraction efficiency, further reducing the turn-off tailing effect of the semiconductor power device, and further reducing the turn-off loss of the semiconductor power device.

[0075] Regarding the manner in which at least a portion of the contact region 50 is positioned opposite to the second drift region 12 , a variety of manners may be adopted, some of which are exemplarily introduced below.

[0076] In some embodiments, another semiconductor power device is provided, referring to Figure 4 The contact region 50 includes: a first portion 51 extending in a direction parallel to the extending direction of the active gate 31 and opposite to the second drift region 12. For example, referring to Figure 4 , the second drift region 12 and the active gate 31 both extend along the y direction.

[0077] The above technical solution has the following beneficial effects: by setting a contact area 50 including a first part 51, the characteristic of being able to increase the area of ​​the region where the contact area 50 and the second drift region 12 are opposite to each other when the first part 51 is parallel to the active gate 31 and opposite to the second drift region 12 is utilized, thereby increasing the cross-sectional area of ​​the extraction channel for the contact area 50 to extract carriers from the drift region 10, improving the carrier extraction efficiency, further reducing the turn-off tailing effect of the semiconductor power device, and further reducing the turn-off loss of the semiconductor power device.

[0078] In some embodiments, another semiconductor power device is provided, referring to Figure 4 , the first portion 51 is spaced apart from the active gate 31 .

[0079] The above technical solution has the following beneficial effects: by spacing the first part 51 and the adjacent active gate 31, the carriers of the emission region 40 can enter the drift region 10 through the area between the first part 51 and the adjacent active gate 31, so as to better enhance the conductivity modulation effect in the drift region 10 when the semiconductor power device is turned on through the carrier storage area 70, so as to more effectively reduce the on-state voltage drop of the semiconductor power device.

[0080] In some embodiments, another semiconductor power device is provided, referring to Figure 4 , the extension direction of the second drift region 12 is parallel to the extension direction of the first portion 51, and the width of the second drift region 12 is equal to the width of the first portion 51. For example, referring to Figure 4 , the second drift region 12 and the first portion 51 both extend along the y direction.

[0081] It should be noted that the width of the second drift region 12 refers to the distance between the two side walls of the second drift region 12 in the extending direction perpendicular to the active gate 31, that is, the distance between the two side walls of the second drift region 12 in the x direction. Figure 4 D3 in represents the width of the second drift region 12. The width of the first portion 51 refers to the distance between the two side walls of the first portion 51 in the extending direction perpendicular to the active gate 31, that is, the distance between the two side walls of the first portion 51 in the x direction, as shown in FIG. Figure 4 D4 in denoted by : represents the width of the first portion 51 .

[0082] The above technical solution has the following beneficial effects: by utilizing the second drift region 12 and the first part 51 to be arranged in parallel and with equal width, the area of ​​the relative position of the second drift region 12 and the first part 51 can be increased while making the distribution area of ​​the first carrier storage region 70 as large as possible, thereby reducing the turn-off tailing effect of the semiconductor power device to reduce the turn-off loss of the semiconductor power device, while also reducing the conduction voltage drop of the semiconductor power device, thereby achieving a balance between the turn-off loss and the conduction voltage drop.

[0083] In some embodiments, reference Figure 4 , the first portion 51 and the second drift region 12 are completely opposite in the stacking direction of the drift region 10 and the base region 20. That is, the first portion 51 and the second drift region 12 are completely opposite in the z direction. While increasing the area of ​​the relative region between the second drift region 12 and the first portion 51, the distribution area of ​​the carrier storage region 70 between two adjacent active gates 31 is made as large as possible.

[0084] In some embodiments, another semiconductor power device is provided, referring to Figure 2 A plurality of emission regions 40 are arranged on the side of the first portion 51 facing the first surface, and the plurality of emission regions 40 are arranged at intervals along the extension direction of the first portion 51, that is, the plurality of emission regions 40 are arranged at intervals along the y direction, and each emission region 40 is in contact with the active gate 31; the contact region 50 also includes: a second portion 52 extending from the first portion 51 to between two adjacent emission regions 40.

[0085] The above technical solution has the following beneficial effects: by providing the contact region 50 including the second portion 52, the second portion 52 extends between two adjacent emitter regions 40, so that the contact region 50 and the emitter region 40 are located in the same mesa region, and the conductive plug between the emitter and the emitter region 40 and the contact region 50 is set to the same height, thereby simplifying the difficulty of electrical connection between the contact region 50, the emitter region 40 and the emitter. In addition, by making the emitter region 40 contact the active gate 31, a carrier channel can be formed between the emitter region 40 and the active gate 31.

[0086] In some embodiments, emitter region 40 and contact region 50 may be electrically connected to the emitter metal layer by, for example, but not limited to, conductive plugs.

[0087] In some embodiments, the active gate 31 may be electrically connected to the gate metal layer through, for example but not limited to, a conductive plug.

[0088] In some embodiments, another semiconductor power device is provided, referring to Figure 1 and Figure 2 The preset implantation region 60 is used to electrically connect the emitter metal layer in the semiconductor power device.

[0089] The above technical solution has the following beneficial effects: by electrically connecting the preset injection region 60 to the emitter metal layer of the semiconductor power device, the emitter metal layer emits carriers of the first conductivity type and carriers of the second conductivity type, and can also enable the semiconductor power device to extract carriers in the drift region 10 to the base region 20 through multiple carrier extraction channels when it is turned off, thereby improving the effect of reducing the turn-off tailing effect of the semiconductor power device, thereby improving the effect of reducing the turn-off loss of the semiconductor power device.

[0090] In some embodiments, the predetermined implantation region 60 is electrically connected to the emitter metal layer through, for example but not limited to, a conductive plug, thereby simplifying the implementation of the electrical connection.

[0091] In some embodiments, another semiconductor power device is provided, referring to Figure 2 to Figure 5 , the first conductivity type is N conductivity type, and the second conductivity type is P conductivity type.

[0092] It should be noted that the carriers in the N conductive type are electrons, and the carriers in the P conductive type are holes, and the mobility of electrons is higher than that of holes.

[0093] The above technical solution has the following beneficial effects: by setting an N-conductivity type drift region 10, an emitter region 40 and a carrier storage region 70, as well as a P-conductivity type base region 20, a contact region 50 and a preset injection region 60, the characteristic that the mobility of electrons is higher than that of holes is utilized, thereby improving the voltage resistance of the semiconductor power device and reducing the on-resistance of the semiconductor power device.

[0094] In some other embodiments, the first conductivity type may be a P conductivity type, and the second conductivity type may be an N conductivity type.

[0095] In some embodiments, another semiconductor power device is provided, referring to Figure 2 to Figure 5 , the doping concentrations of the emission region 40 and the carrier storage region 70 are both greater than the doping concentration of the drift region 10 .

[0096] The above technical solution has the following beneficial effects: by making the doping concentrations of the emission region 40 and the carrier storage region 70 greater than the doping concentration of the drift region 10, the conductivity modulation effect in the drift region 10 when the semiconductor power device is turned on can be enhanced, thereby reducing the on-state voltage drop of the semiconductor power device.

[0097] In some embodiments, reference Figure 2 to Figure 5 The doping type and doping concentration of the emitter region 40 and the carriers can be N+, and the doping type and doping concentration of the drift region 10 can be N- or N. The doping type and doping concentration of the base region 20 can be P-, and the doping type and doping concentration of the contact region 50 and the preset injection region 60 can be P+.

[0098] In some embodiments, reference Figure 6 The semiconductor power device may further include: a field stop region 80 disposed on the side of the drift region 10 away from the base region 20, and a collector region 90 disposed on the side of the field stop region 80 away from the drift region 10, wherein the collector region 90 is used to electrically connect the collector metal layer of the semiconductor power device.

[0099] Exemplarily, the collector region 90 may be electrically connected to the collector metal layer by, for example but not limited to, a conductive plug to simplify the electrical connection implementation.

[0100] In some embodiments, the structures in the base region 20, the emitter region 40, the contact region 50, the contact region 50, the dummy gate 32, the active gate 31, the field stop region 80 and the collector region 90 can be prepared by semiconductor preparation processes such as but not limited to etching, deposition, and doping.

[0101] For example, refer to Figure 7 , a drift region 10 may be first formed in the substrate, and then an active gate 31 and a dummy gate 32 may be formed above the drift region 10. Figure 8 Then, a base region 20 is formed on the first surface side of the drift region 10 facing the substrate. Fig. 9 Then, a carrier storage region 70 is formed on the side of the drift region 10 facing the base region 20. Fig.10 , and then an emitter region 40 is formed in the base region 20. Figure 2 , and then a contact region 50 and a preset implantation region 60 are formed in the base region 20 to complete the preparation of the semiconductor power device.

[0102] In addition, in some embodiments, an electronic device is also provided, referring to Figure 1 to Figure 6 , the electronic device includes the semiconductor power device as above.

[0103] The above technical solution has the following beneficial effects: by setting a preset injection region 60 in the base region 20 on the side of the virtual gate 32 away from the active gate 31, and also setting a first drift region 11 in the carrier storage region 70 on the side of the virtual gate 32 away from the active gate 31, the drift region 10 extends to the first drift region 11 and contacts the base region 20, so that when the semiconductor power device is turned off, in addition to using the carrier extraction channel based on the contact region 50 to extract carriers, it can also use the carrier extraction channel based on the preset injection region 60 to extract carriers, and can more quickly extract the carriers of the drift region 10 to the base region 20, reducing the turn-off tailing effect of the semiconductor power device, thereby reducing the turn-off loss of the semiconductor power device. In addition, the conductivity modulation effect in the drift region 10 when the semiconductor power device is turned on can be enhanced through the carrier storage region 70 to reduce the turn-on voltage drop of the semiconductor power device. Thereby, the on-state voltage drop of the semiconductor power device is reduced while the off-state loss of the semiconductor power device is reduced, and the on-state voltage drop and the low off-state loss of the semiconductor power device are better balanced, thereby reducing the power consumption of the electronic device.

[0104] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor power device is used.

[0105] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A semiconductor power device, characterized in that: include: a substrate having opposing first and second surfaces; A drift region of the first conductivity type is disposed in the substrate and located between the first surface and the second surface; A base region of the second conductivity type is arranged on the side of the drift region facing the first surface; an emitter region of the first conductivity type, a contact region of the second conductivity type and a preset injection region are arranged in the base region; an active gate, penetrating the base region and extending to the drift region; the emitter region and the contact region are located on both sides of the active gate; two dummy gates, the dummy gates penetrate the base region and extend to the drift region; the active gate and the two dummy gates are spaced apart, and the active gate is located between the two dummy gates; A carrier storage region of the first conductivity type is arranged in the drift region on a side facing the base region and located on both sides of the active gate and the dummy gate; The drift region includes: a first drift region penetrating the carrier storage region to contact the base region, and the first drift region and the preset injection region are both located on the same side of the dummy gate away from the active gate.

2. The semiconductor power device according to claim 1, characterized in that: The doping concentration of the preset injection region is greater than the doping concentration of the base region, and at least a portion of the preset injection region is located opposite to the first drift region.

3. The semiconductor power device according to claim 2, characterized in that: An extension direction of the preset injection region is parallel to an extension direction of the dummy gate.

4. The semiconductor power device according to claim 3, characterized in that: The preset injection region is spaced apart from the adjacent dummy gate.

5. The semiconductor power device according to claim 3, characterized in that: An extension direction of the first drift region is parallel to an extension direction of the preset injection region, and a width of the first drift region is equal to a width of the preset injection region.

6. The semiconductor power device according to claim 1, characterized in that: The preset injection region and the first drift region are disposed on a side of each of the two virtual gates facing away from the active gate.

7. The semiconductor power device according to claim 1, characterized in that: The doping concentration of the contact region is greater than the doping concentration of the base region; The drift region further includes: a second drift region penetrating the carrier storage region to contact the base region, and the second drift region is located at both sides of the active gate.

8. The semiconductor power device according to claim 1, characterized in that: The preset implantation region is used to electrically connect the emitter metal layer of the semiconductor power device.

9. The semiconductor power device according to claim 1, characterized in that: The first conductivity type is an N conductivity type, and the second conductivity type is a P conductivity type; and / or, The doping concentrations of the emission region and the carrier storage region are both greater than the doping concentration of the drift region.

10. An electronic device, characterized in that: The electronic device comprises the semiconductor power device according to any one of claims 1 to 9.

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