Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof. The solar cell comprises a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are oppositely arranged; a hole transport layer and an electron transport layer, the hole transport layer and the electron transport layer are arranged on the first surface at an interval, the material of the hole transport layer comprises vanadium oxide, and the material of the electron transport layer comprises titanium oxide; the first passivation layer is located on the surface, away from the semiconductor substrate, of the hole transport layer; and the second passivation layer covers the surface, far away from the semiconductor substrate, of the first passivation layer, the surface, far away from the semiconductor substrate, of the electron transport layer and the first surface. According to the solar cell, a good electric contact effect between the electrode and the semiconductor region can be achieved, and therefore the high photoelectric conversion efficiency of the IBC solar cell is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] Compared with the passivated emitter rear cell (PERC cell) and heterojunction cell (HJT cell), the interdigitated back contact solar cell (IBC solar cell) has no grid lines on the front side, and the positive and negative electrodes are prepared on the back side of the cell in a cross-arranged manner, which can avoid the shading loss caused by the shading of the grid lines on the front side of the solar cell. In traditional IBC solar cells, the staggered n-type doped semiconductor region and the p-type doped semiconductor region are formed by diffusion, and then holes are opened in the dielectric layer to achieve electrical contact between the electrode and the emission region. In this traditional IBC solar cell, the electrical contact quality between the electrode and the semiconductor region is poor, which limits the further improvement of the photoelectric conversion efficiency of the IBC solar cell. Summary of the invention

[0003] Based on this, it is necessary to provide a solar cell and a method for preparing the same. In the solar cell of the present application, the electrical contact between the electrode and the semiconductor region is good, and a higher photoelectric conversion efficiency of the IBC solar cell can be achieved.

[0004] In a first aspect, the present application provides a solar cell, comprising:

[0005] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0006] A hole transport layer and an electron transport layer, wherein the hole transport layer and the electron transport layer are arranged on the first surface at an interval, the material of the hole transport layer comprises vanadium oxide, and the material of the electron transport layer comprises titanium oxide;

[0007] a first passivation layer, the first passivation layer being located on a surface of the hole transport layer away from the semiconductor substrate;

[0008] A second passivation layer, wherein the second passivation layer covers a surface of the first passivation layer away from the semiconductor substrate, a surface of the electron transport layer away from the semiconductor substrate, and the first surface.

[0009] In some embodiments, the thickness of the hole transport layer is 20 nm to 30 nm.

[0010] In some embodiments, the thickness of the electron transport layer is 45 nm to 55 nm.

[0011] In some embodiments, the material of the first passivation layer includes aluminum oxide.

[0012] In some embodiments, a material of the second passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0013] In some embodiments, the second surface is suede.

[0014] In some embodiments, a third passivation layer is disposed on the second surface.

[0015] In some embodiments, a fourth passivation layer is further disposed on a surface of the third passivation layer away from the semiconductor substrate, and the fourth passivation layer and the third passivation layer are made of different materials.

[0016] In a second aspect, the present application provides a method for preparing a solar cell as described in any one of the above items, comprising:

[0017] Providing a semiconductor substrate having a first surface and a second surface disposed opposite to each other;

[0018] Prepare a hole transport layer and an electron transport layer, wherein the hole transport layer and the electron transport layer are arranged on the first surface at an interval, the material of the hole transport layer includes vanadium oxide, and the material of the electron transport layer includes titanium oxide;

[0019] preparing a first passivation layer, wherein the first passivation layer is located on a surface of the hole transport layer away from the semiconductor substrate;

[0020] A second passivation layer is prepared, wherein the second passivation layer covers a surface of the first passivation layer away from the semiconductor substrate, a surface of the electron transport layer away from the semiconductor substrate, and the first surface.

[0021] In some embodiments, preparing the hole transport layer comprises:

[0022] The hole transport layer is prepared by atomic layer deposition at 120° C. to 130° C. using a vanadium source and a first oxidant; or, the hole transport layer is prepared by plasma enhanced chemical vapor deposition at 380° C. to 420° C. using a vanadium source and a second oxidant.

[0023] In some embodiments, preparing the electron transport layer comprises:

[0024] The hole transport layer is prepared by atomic layer deposition at 100° C. to 160° C. using a titanium source and a first oxidant; or, the hole transport layer is prepared by plasma enhanced chemical vapor deposition at 380° C. to 420° C. using a titanium source and a second oxidant.

[0025] In the above-mentioned solar cell, the material of the hole transport layer includes vanadium oxide, and the vanadium oxide presents a hole-selective state. The material of the electron transport layer includes titanium oxide, and the titanium oxide presents an electron-selective state. The hole transport layer and the electron transport layer in the present application cooperate with each other, and the contact barrier between the two and the electrode is small, which can achieve a better conduction effect of photogenerated carriers. At the same time, the surface of the hole transport layer is passivated by stacking two different materials, which can better improve the surface contact effect between the passivated hole transport layer and the electrode. The solar cell can achieve a better electrical contact effect between the electrode and the hole transport layer and the electron transport layer, thereby achieving a higher photoelectric conversion efficiency of the IBC solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure for preparing a hole transport layer and a first passivation layer on the surface of a semiconductor substrate;

[0027] Figure 2 For Figure 1 A schematic diagram of a structure for preparing a first mask layer and a second mask layer based on the structure shown;

[0028] Figure 3 For Figure 2 A schematic diagram of a structure in which part of the hole transport layer and the dielectric layer are removed from the structure shown;

[0029] Figure 4 For Figure 3 A schematic diagram of a structure in which the first mask layer is removed based on the structure shown;

[0030] Figure 5 For Figure 4 A schematic diagram of the structure of preparing an electron transport layer based on the structure shown;

[0031] Figure 6 For Figure 5 A schematic diagram of a structure for preparing a first passivation layer based on the structure shown;

[0032] Figure 7 For Figure 6 A schematic diagram of a structure for preparing a third passivation layer and a fourth passivation layer based on the structure shown;

[0033] Figure 8 For Figure 6 Schematic diagram of the structure of preparing the first electrode and the second electrode based on the structure shown.

[0034] Description of Reference Numerals

[0035] 10. semiconductor substrate; 21. hole transport layer; 22. first passivation layer; 31. first mask layer; 32. second mask layer; 40. electron transport layer; 50. second passivation layer; 61. third passivation layer; 62. fourth passivation layer; 71. first electrode; 72. second electrode. DETAILED DESCRIPTION

[0036] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] An embodiment of the present application provides a solar cell, comprising: a semiconductor substrate 10, the semiconductor substrate 10 having a first surface and a second surface arranged opposite to each other; a hole transport layer 21 and an electron transport layer 40, the hole transport layer 21 and the electron transport layer 40 are arranged on the first surface at intervals, the material of the hole transport layer 21 includes vanadium oxide, and the material of the electron transport layer 40 includes titanium oxide; a first passivation layer 22, the first passivation layer 22 is located on the surface of the hole transport layer 21 away from the semiconductor substrate 10; a second passivation layer 50, the second passivation layer 50 covers the surface of the first passivation layer 22 away from the semiconductor substrate 10, the surface of the electron transport layer 40 away from the semiconductor substrate 10, and the first surface.

[0039] In the above-mentioned solar cell, the material of the hole transport layer 21 includes vanadium oxide, and the vanadium oxide presents a hole-selective state. The material of the electron transport layer 40 includes titanium oxide, and the titanium oxide presents an electron-selective state. The hole transport layer 21 and the electron transport layer 40 in the present application cooperate with each other, and the contact barrier between the two and the electrode is small, which can achieve a better conduction effect of photogenerated carriers. At the same time, the surface of the hole transport layer 21 is passivated by stacking two different materials, which can better improve the surface contact effect between the passivated hole transport layer 21 and the electrode. The solar cell can achieve a good electrical contact effect between the electrode and the hole transport layer 21 and the electron transport layer 40, thereby achieving a higher photoelectric conversion efficiency of the IBC solar cell.

[0040] In some embodiments, the material of the hole transport layer 21 is vanadium oxide.

[0041] In some embodiments, the material of the electron transport layer 40 is titanium oxide.

[0042] In some embodiments, the thickness of the hole transport layer 21 is 20 nm to 30 nm. Within the thickness range of the hole transport layer 21, the film quality of the hole transport layer 21 is good, and the selective contact effect of the obtained battery is good. Optionally, the thickness of the hole transport layer 21 is 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm or 30 nm.

[0043] In some embodiments, the thickness of the electron transport layer 40 is 45 nm to 55 nm. Within the thickness range of the electron transport layer 40, the film quality of the electron transport layer 40 is good, and the selective contact effect of the obtained battery is good. Optionally, the thickness of the electron transport layer 40 is 45 nm, 46 nm, 47 nm, 48 nm, 49 nm, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm or 55 nm.

[0044] In some embodiments, the material of the first passivation layer 22 includes aluminum oxide. Aluminum oxide has a good matching effect with n-type semiconductor materials, and can perform a good passivation effect on the hole transport layer 21, so as to obtain a solar cell with a good contact effect.

[0045] In some embodiments, the material of the first passivation layer 22 is aluminum oxide.

[0046] In some embodiments, the material of the second passivation layer 50 includes at least one of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0047] In some embodiments, the second surface is a suede surface. It is understood that the suede surface can be a suede surface of different morphologies. Exemplarily, the suede surface can be a pyramid-shaped suede surface.

[0048] In some embodiments, a third passivation layer 60 is further disposed on the second surface. Passivating the front side of the cell can further improve the photovoltaic performance of the solar cell.

[0049] In some embodiments, the material of the third passivation layer 60 includes at least one of aluminum oxide, silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0050] In some embodiments, a fourth passivation layer 62 is further disposed on the surface of the third passivation layer 60 away from the semiconductor substrate 10, and the fourth passivation layer 62 is made of different materials from the third passivation layer 60. Performing stacked passivation on the front side of the cell can further improve the photovoltaic performance of the solar cell.

[0051] In some embodiments, the material of the fourth passivation layer 62 includes at least one of aluminum oxide, silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0052] In some embodiments, the materials of the third passivation layer 60 and the fourth passivation layer 62 are different.

[0053] In some embodiments, the material of the semiconductor substrate 10 includes an n-type single crystal silicon wafer.

[0054] In some embodiments, the solar cell further includes: a first electrode 71 and a second electrode 72, wherein the first electrode 71 is located on a surface of the second passivation layer 50 covering the first passivation layer 22 away from the semiconductor substrate 10, and the second electrode 72 is located on a surface of the second passivation layer 50 covering the electron transport layer 40 away from the semiconductor substrate 10.

[0055] Another embodiment of the present application provides a method for preparing any of the above-mentioned solar cells, comprising: providing a semiconductor substrate 10, the semiconductor substrate 10 having a first surface and a second surface arranged opposite to each other; preparing a hole transport layer 21 and an electron transport layer 40, the hole transport layer 21 and the electron transport layer 40 are arranged on the first surface at intervals, the material of the hole transport layer 21 includes vanadium oxide, and the material of the electron transport layer 40 includes titanium oxide; preparing a first passivation layer 22, the first passivation layer 22 is located on the surface of the hole transport layer 21 away from the semiconductor substrate 10; preparing a second passivation layer 50, the second passivation layer 50 covers the surface of the first passivation layer 22 away from the semiconductor substrate 10, the surface of the electron transport layer 40 away from the semiconductor substrate 10 and the first surface.

[0056] In some examples of this embodiment, the method for preparing a solar cell includes steps S100 to S500, which are specifically as follows.

[0057] S100 : providing a semiconductor substrate 10 , wherein the semiconductor substrate 10 has a first surface and a second surface opposite to each other.

[0058] In some embodiments, the method further includes: cleaning the semiconductor substrate 10 to remove impurities on the surface of the semiconductor substrate 10 .

[0059] In some embodiments, cleaning the semiconductor substrate 10 includes: cleaning the semiconductor substrate 10 using a mixed solution of a potassium hydroxide solution and a hydrogen peroxide solution.

[0060] In some embodiments, the method further includes: texturing the cleaned semiconductor substrate 10 to form a textured surface on the surface of the semiconductor substrate 10 .

[0061] In some embodiments, texturing the cleaned semiconductor substrate 10 includes: anisotropically etching the semiconductor substrate 10 using an etching solution to form a pyramid-shaped texture surface on the surface of the semiconductor substrate 10 .

[0062] In some embodiments, the etching solution includes a potassium hydroxide solution.

[0063] S200: preparing a hole transport layer 21 and an electron transport layer 40, wherein the hole transport layer 21 and the electron transport layer 40 are disposed on the first surface at intervals, the material of the hole transport layer 21 includes vanadium oxide, and the material of the electron transport layer 40 includes titanium oxide.

[0064] In some embodiments, preparing the hole transport layer 21 includes: preparing the hole transport layer 21 by atomic layer deposition at 120°C to 130°C using a vanadium source and a first oxidant. Within the temperature range of the atomic layer deposition, a hole transport layer 21 with good film forming effect and compactness can be deposited, and at the same time, a lower deposition temperature can reduce the damage to the passivation stability caused by a higher temperature. Optionally, the temperature of the atomic layer deposition is 120°C, 121°C, 122°C, 123°C, 124°C, 125°C, 126°C, 127°C, 128°C, 129°C or 130°C. Exemplarily, the vanadium source for atomic layer deposition includes tetraethylmethylaminovanadium (VTIP). Exemplarily, the first oxidant for atomic layer deposition includes deionized water.

[0065] In some embodiments, the number of cycles of atomic layer deposition is 160 to 240. Within the number of cycles of atomic layer deposition, a hole transport layer 21 with a suitable thickness can be obtained. Optionally, the number of cycles of atomic layer deposition is 160, 170, 180, 190, 200, 210, 220, 230 or 240.

[0066] In some embodiments, preparing the hole transport layer 21 includes: preparing the hole transport layer 21 by plasma enhanced chemical vapor deposition at 380°C to 420°C through a vanadium source and a second oxidant. Within the temperature range of the plasma enhanced chemical vapor deposition, a hole transport layer 21 with good film forming effect and compactness can be deposited, and at the same time, a lower deposition temperature can reduce the damage to the passivation stability caused by a higher temperature. Optionally, the temperature of the plasma enhanced chemical vapor deposition is 380°C, 385°C, 390°C, 395°C, 400°C, 405°C, 410°C, 415°C or 420°C. Exemplarily, the vanadium source for plasma enhanced chemical vapor deposition includes VTIP. The second oxidant for plasma enhanced chemical vapor deposition includes N2O.

[0067] In some embodiments, preparing the electron transport layer 40 includes: preparing the electron transport layer 40 by atomic layer deposition at 100° C. to 160° C. using a titanium source and a first oxidant.

[0068] In some embodiments, preparing the electron transport layer 40 includes: preparing the electron transport layer 40 by plasma enhanced chemical vapor deposition at 380° C. to 420° C. using a titanium source and a second oxidant.

[0069] S300 : preparing a first passivation layer 22 , wherein the first passivation layer 22 is located on a surface of the hole transport layer 21 away from the semiconductor substrate 10 .

[0070] In some embodiments, reference Figures 1 to 5 , Figure 1 A schematic diagram of the structure of preparing a hole transport layer 21 and a first passivation layer 22 on the surface of a semiconductor substrate 10; Figure 2 For Figure 1 A schematic diagram of a structure for preparing a first mask layer 31 and a second mask layer 32 based on the structure shown; Figure 3 For Figure 2 A schematic diagram of a structure in which part of the hole transport layer 21 and the dielectric layer are removed from the structure shown; Figure 4 For Figure 3 A schematic diagram of a structure in which the first mask layer 31 is removed based on the structure shown; Figure 5 For Figure 4 Schematic diagram of the structure of preparing an electron transport layer 40 based on the structure shown; preparing a hole transport layer 21, an electron transport layer 40 and a first passivation layer 22 includes the following steps: preparing a hole transport layer 21 and a first passivation layer 22 stacked in sequence on a semiconductor substrate 10; preparing a first mask layer 31 and a second mask layer 32 on the surface of the first passivation layer 22, wherein the first mask layer 31 cannot be removed by a developer, and the second mask layer 32 can be removed by a developer; removing the second mask layer 32, and etching the exposed first passivation layer 22 and hole transport layer 21; removing the first mask layer 31, and preparing an electron transport layer 40 on the surface of the semiconductor substrate 10.

[0071] In some embodiments, the material of the first mask layer 31 includes photosensitive polyimide. In some embodiments, the material of the second mask layer 32 includes photosensitive polyimide.

[0072] S400 : preparing a second passivation layer 50 , the second passivation layer 50 covers the surface of the first passivation layer 22 away from the semiconductor substrate 10 , the surface of the electron transport layer 40 away from the semiconductor substrate 10 , and the first surface.

[0073] Figure 6 For Figure 5 The schematic diagram of the structure of preparing the first passivation layer 22 based on the structure shown in FIG. Figure 6 As shown, the second passivation layer 50 covers the surface of the first passivation layer 22 away from the semiconductor substrate 10 , the surface of the electron transport layer 40 away from the semiconductor substrate 10 , and the first surface.

[0074] S500 : preparing a first electrode 71 and a second electrode 72 , wherein the first electrode 71 is located on a surface of the second passivation layer 50 covering the first passivation layer 22 away from the semiconductor substrate 10 , and the second electrode 72 is located on a surface of the second passivation layer 50 covering the electron transport layer 40 away from the semiconductor substrate 10 .

[0075] Figure 8 For Figure 6 A schematic diagram of the structure of preparing the first electrode 71 and the second electrode 72 based on the structure shown in FIG. Figure 8 As shown, the first electrode 71 is located on the surface of the second passivation layer 50 covering the first passivation layer 22 and away from the semiconductor substrate 10 , and the second electrode 72 is located on the surface of the second passivation layer 50 covering the electron transport layer 40 and away from the semiconductor substrate 10 .

[0076] In some embodiments, the materials of the first electrode 71 and the second electrode 72 are independently selected from all metal electrodes available in the art. For example, the material of the first electrode 71 is a silver electrode. For example, the material of the second electrode 72 includes nickel and aluminum.

[0077] In some embodiments, the method further includes: preparing a third passivation layer 60 on the first surface.

[0078] In some embodiments, the method further includes: preparing a fourth passivation layer 62 on the surface of the third passivation layer 60 .

[0079] Figure 7 For Figure 6 A schematic diagram of a structure in which a third passivation layer 60 and a fourth passivation layer 62 are prepared based on the structure shown in FIG. Figure 7 As shown, the third passivation layer 60 is disposed on the surface of the semiconductor substrate 10 having the light trapping structure, and the fourth passivation layer 62 is disposed on the surface of the third passivation layer 60 away from the semiconductor substrate 10 .

[0080] The following are specific embodiments

[0081] Example 1

[0082] Refer again Figures 1 to 8 , the preparation method of the solar cell is as follows:

[0083] (1) The semiconductor substrate 10 is cleaned for about 90 seconds at 70° C. using a mixed solution of potassium hydroxide solution and hydrogen peroxide solution to remove impurities on the surface of the silicon wafer.

[0084] (2) At 78°C, the front side of the silicon wafer is subjected to chain texturing for about 450 seconds using a potassium hydroxide solution and an additive to form a pyramid-shaped texturing surface on the front side of the silicon wafer as a light trapping structure.

[0085] (3) Under the condition of 120°C~130°C, using ALD equipment, VTIP and deionized water as precursor and oxidant, 160~240 cycles were performed to prepare a vanadium oxide film with a thickness of 20nm~30nm as the hole transport layer 21.

[0086] (4) At 190° C. to 210° C., an ALD device is used, trimethylaluminum (TMA) and deionized water are used as a precursor and an oxidant, and 450 to 550 cycles are performed to prepare a 45 nm to 55 nm aluminum oxide film as the first passivation layer 22 .

[0087] (5) A patterned mask layer is prepared using photosensitive polyimide, and a first mask layer 31 and a second mask layer 32 are obtained by photochemical reaction, and the hole transport layer 21 and the first passivation layer 22 covered by the second mask layer 32 are removed by dry etching.

[0088] (6) The first mask layer 31 is removed.

[0089] (7) A titanium oxide thin film with a thickness of 22.5 nm to 27.5 nm was prepared as the electron transport layer 40 by using an ALD device at 100° C. to adopt titanium tetraisopropoxide and deionized water as a precursor and an oxidant for 225 to 275 cycles.

[0090] (8) Using silane and methane as silicon source and carbon source and H 2 as carrier gas, a 20 nm thick silicon carbide film is deposited as the second passivation layer 50 .

[0091] (9) Using the same conditions as in step (4) and step (8), an aluminum oxide film as the third passivation layer 60 and a silicon carbide film as the fourth passivation layer 62 are respectively prepared on the front side of the silicon wafer.

[0092] (10) Anneal at 380℃~420℃ for 10 min to activate surface passivation.

[0093] (11) Prepare a silver first electrode 71 and a nickel aluminum second electrode 72 respectively.

[0094] Example 2

[0095] The preparation method of the solar cell in this embodiment is basically the same as that in Embodiment 1, except that:

[0096] In step (3), at 400° C., a plasma enhanced chemical vapor deposition device is used, and VTIP and N 2 O are used as a precursor and an oxidant to prepare a vanadium oxide film with a thickness of 20 nm to 30 nm as the hole transport layer 21 .

[0097] In step (7), at 400° C., an ALD device and a plasma enhanced chemical vapor deposition device are used, and titanium tetraisopropoxide and N 2 O are used as precursors and oxidants to prepare a titanium oxide film with a thickness of 22.5 nm to 27.5 nm as the electron transport layer 40 .

[0098] Comparative Example 1

[0099] (1) The semiconductor substrate 10 is cleaned for about 90 seconds at 70° C. using a mixed solution of potassium hydroxide solution and hydrogen peroxide solution to remove impurities on the surface of the silicon wafer.

[0100] (2) At 78°C, the front side of the silicon wafer is subjected to chain texturing for about 450 seconds using a potassium hydroxide solution and an additive to form a pyramid-shaped texturing surface on the front side of the silicon wafer as a light trapping structure.

[0101] (3) At 600°C, a layer of intrinsic amorphous silicon is deposited on the back of the silicon wafer by low-pressure chemical vapor deposition.

[0102] (4) Boron diffusion is performed at 1000° C. to form P-type polysilicon as the P region, i.e., the hole transport layer 21.

[0103] (5) A patterned mask layer is prepared using photosensitive polyimide, and a first mask layer 31 and a second mask layer 32 are obtained by photochemical reaction, and the hole transport layer 21 covered by the second mask layer 32 is removed by dry etching.

[0104] (6) The first mask layer 31 is removed.

[0105] (7) Phosphorus diffusion is performed at 900° C. to form N-type polysilicon as the N region, i.e., the electron transport layer 40 .

[0106] (8) Using silane and methane as silicon source and carbon source and H 2 as carrier gas, a 20 nm thick silicon carbide film is deposited as the second passivation layer 50 .

[0107] (9) Using the same conditions as step (4) and step (8) in Example 1, an aluminum oxide film as the third passivation layer 60 and a silicon carbide film as the fourth passivation layer 62 are prepared on the front side of the silicon wafer.

[0108] (10) Anneal at 380℃~420℃ for 10 min to activate surface passivation.

[0109] (11) Prepare a silver first electrode 71 and a nickel aluminum second electrode 72 respectively.

[0110] The performance of the solar cells prepared in Examples 1, 2 and Comparative Example 1 was tested, including the open circuit voltage U oc , short circuit current I sc , fill factor FF and conversion efficiency E ta The test results are shown in Table 1:

[0111] Table 1

[0112]

[0113] It can be seen that the photoelectric conversion efficiency and open circuit voltage of the solar cells in Examples 1 and 2 are higher than those in Comparative Example 1. At the same time, the yields of Examples 1 and 2 are also higher than those in Comparative Example 1, indicating that the high temperature process will affect the warpage of the silicon wafer, so the yield in Comparative Example 1 is lower. Furthermore, the open circuit voltage of the solar cell in Example 2 is relatively small compared to that in Example 1, because the thin film grown by plasma enhanced chemical vapor deposition is not dense enough, so the passivation effect is not as good as the thin film prepared by atomic layer deposition in Example 1.

[0114] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be based on the attached claims, and the description and drawings may be used to interpret the contents of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A hole transport layer and an electron transport layer, wherein the hole transport layer and the electron transport layer are arranged on the first surface at an interval, the material of the hole transport layer comprises vanadium oxide, and the material of the electron transport layer comprises titanium oxide; a first passivation layer, the first passivation layer being located on a surface of the hole transport layer away from the semiconductor substrate; A second passivation layer, wherein the material of the second passivation layer is different from the material of the first passivation layer, and the second passivation layer covers a surface of the first passivation layer away from the semiconductor substrate, a surface of the electron transport layer away from the semiconductor substrate, and the first surface.

2. The solar cell according to claim 1, characterized in that: The thickness of the hole transport layer is 20nm-30nm.

3. The solar cell according to claim 1, characterized in that: The thickness of the electron transport layer is 45nm-55nm.

4. The solar cell according to claim 1, characterized in that: The material of the first passivation layer includes aluminum oxide; And / or, the material of the second passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide and silicon oxynitride.

5. The solar cell according to any one of claims 1 to 4, characterized in that: The second surface is a suede surface.

6. The solar cell according to claim 5, characterized in that: A third passivation layer is disposed on the second surface.

7. The solar cell according to claim 6, characterized in that: A fourth passivation layer is disposed on a surface of the third passivation layer away from the semiconductor substrate, and the fourth passivation layer and the third passivation layer are made of different materials.

8. A method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: include: Providing a semiconductor substrate having a first surface and a second surface disposed opposite to each other; Prepare a hole transport layer and an electron transport layer, wherein the hole transport layer and the electron transport layer are arranged on the first surface at an interval, the material of the hole transport layer includes vanadium oxide, and the material of the electron transport layer includes titanium oxide; preparing a first passivation layer, wherein the first passivation layer is located on a surface of the hole transport layer away from the semiconductor substrate; A second passivation layer is prepared, wherein the second passivation layer covers a surface of the first passivation layer away from the semiconductor substrate, a surface of the electron transport layer away from the semiconductor substrate, and the first surface.

9. The method for preparing a solar cell according to claim 8, characterized in that: The preparation of the hole transport layer comprises: The hole transport layer is prepared by atomic layer deposition at 120° C. to 130° C. using a vanadium source and a first oxidant; or, the hole transport layer is prepared by plasma enhanced chemical vapor deposition at 380° C. to 420° C. using a vanadium source and a second oxidant.

10. The method for preparing a solar cell according to claim 8, characterized in that: The preparation of the electron transport layer comprises: The hole transport layer is prepared by atomic layer deposition at 100° C. to 160° C. using a titanium source and a first oxidant; or, the hole transport layer is prepared by plasma enhanced chemical vapor deposition at 380° C. to 420° C. using a titanium source and a second oxidant.

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