Event type parallel online learning neuromorphic calculation method and system

Abstract

The invention provides an event type parallel online learning neuromorphic calculation method and system. The method comprises a framework construction step, a sample learning step, a sparse calculation step and a parallel calculation step. The system comprises a computing core, a Mesh-Tree mixed on-chip routing communication network, a configuration and monitoring module, a global control module and an Argmax decision module. The sparse calculation step (event-driven type) and the parallel calculation step solve the problem of low efficiency when large-scale neuromorphic hardware realizes online learning, and the neural modulation-based online learning framework and the sample learning step have the advantages that the efficiency is high, and the efficiency is high. The compatibility problem and the large-amount memory consumption problem of the current customized online learning processor are relieved; according to the computing system, the computing method is efficiently realized, and meanwhile, the compatibility, the expandability and the learning performance of the neuromorphic processor supporting online learning are improved based on a computing engine architecture capable of configuring a data path and flexible NoC communication.

Description

Technical Field

[0001] The present invention relates to the field of neuromorphic computing, and in particular to an event-based parallel online learning neuromorphic computing method and system. Background Art

[0002] Artificial Neural Networks (ANNs) have made significant progress in fields such as computer vision and natural language processing, but their offline training and edge device deployment face problems of low computational efficiency and poor generalization ability. The reasoning process of ANNs consumes a lot of energy, and the model performance may degrade under environmental changes and device drift. Inspired by biological computing, spiking neural networks (SNNs) provide a more flexible and energy-efficient computing method by simulating the characteristics of biological nervous systems. The learning ability of neuromorphic hardware provides a good foundation for SNNs, which helps to solve the bottlenecks of ANNs in terms of energy efficiency and generalization ability.

[0003] To achieve on-chip learning, research has focused on synaptic plasticity rules, including Hebbian learning and back propagation (BP) learning. Although these rules have been applied in multi-core neuromorphic hardware, their practical performance is limited due to the lack of theoretical support. Modulated synaptic plasticity is associated with neuromodulators, which helps guide the solution of complex learning tasks; at the same time, this supervised plasticity can also be easily associated with the classic supervised BP training algorithm. Since recurrent neural networks are similar to SNNs in structure, the back propagation through time (BPTT) algorithm can be directly used for SNN training. However, the BPTT algorithm has high memory and computation requirements and is difficult to implement on resource-constrained online learning devices. To this end, a variety of efficient online training algorithms have been developed to alleviate the need for BPTT. In general, existing neuromorphic online learning implementations are usually tightly coupled with specific algorithms and lack a unified on-chip learning platform. Existing algorithms are mainly targeted at high-performance von Neumann architectures and are difficult to support batch learning of SNNs. In addition, existing implementations have not yet fully utilized the sparsity and parallelism in the SNN learning process.

[0004] Through searching patent documents, it is found that CN115996173A discloses a communication optimization method and system for parallel training of distributed deep learning operators, including: model analysis, strategy evaluation and generation of optimal optimization strategy, operator splitting and hidden communication, and integration of model training and operator splitting. This patent only focuses on communication optimization for parallel training of distributed deep learning operators, and the method and system are relatively simple.

[0005] In summary, in response to the above-mentioned problems of the prior art, studying an event-based parallel online learning neuromorphic computing method and system has become a key task that needs to be solved urgently. Summary of the invention

[0006] In view of the defects in the prior art, the purpose of the present invention is to provide an event-based parallel online learning neuromorphic computing method and system.

[0007] According to the present invention, an event-based parallel online learning neuromorphic computing method is provided, comprising the following steps:

[0008] The framework construction step unifies and formalizes a variety of mainstream neuromorphic online learning algorithms, and builds an online learning framework based on neural modulation to guide the general and scalable design of neuromorphic hardware processors;

[0009] The sample learning step, based on the online learning framework, uses batch parameter update averaging to improve the stability of learning / training, while reducing memory requirements by parameter gradient accumulation and delayed update;

[0010] The sparse computing step is based on the online learning framework. In the forward process, it simulates the impact of the presynaptic neuron firing on the postsynaptic neuron. In the backward process, it skips the "zero value" related calculations to improve computing efficiency.

[0011] The parallel computing step is based on the online learning framework and combined with sparse event-based computing to split the operators. Then, the split operators are deployed in multiple cores for parallel computing to optimize the computing efficiency.

[0012] Preferably, the online learning framework is based on the three-factor learning rule, which provides a basis for explaining how the brain learns complex tasks by linking neuromodulators to local plasticity, described by the formula:

[0013]

[0014] in, is the gradient of the weight parameter, Pre and Post represent the activities of presynaptic and postsynaptic neurons respectively, M represents the neuromodulator, F1 represents the influence process of presynaptic and postsynaptic neurons, and F2 represents the influence process of neuromodulator on synaptic activity.

[0015] Preferably, in the sample learning step: by streaming the samples in a batch, that is, according to the rules of the online learning framework, the corresponding weight parameter gradients are calculated, and then by accumulating the gradient calculation results in a batch and combining the weight delayed update, low memory usage is achieved.

[0016] Preferably, the sparse computing step includes the following sub-steps:

[0017] Step S1, in the forward event-based calculation process, address event representation is used to propagate pulses between layers, and the influence of presynaptic pulses on the membrane potential of postsynaptic neurons is calculated based on the fan-out priority calculation method;

[0018] Step S2, in the backward event-based weight gradient calculation process, the calculation is performed based on the sparsity of the presynaptic spike activity. The process is similar to step S1, and the calculation is performed based on the influence of the presynaptic spike activity on the weight gradient, while ignoring the calculation related to the "zero value" activity;

[0019] Step S3, during the backward event-type modulation factor propagation calculation process, the modulation factor coding is calculated by combining pooling and proxy gradient. The modulation factor coding indicates valid modulation information, avoids calculating invalid modulation information backward, and is used to improve calculation efficiency.

[0020] Preferably, step S1 includes the following sub-steps:

[0021] Step S1.1, updating the membrane potential in a fan-out axon-first manner, including: firstly performing compensation in combination with the attenuation factor of the neuron model to facilitate the operator fusion operation in step 2;

[0022] Step 1.2: The membrane potential attenuation operator, bias calculation operator, pooling operator, proxy gradient calculation operator, and release activation operator are merged into one operator to reduce the memory access frequency of the membrane potential, thereby improving the calculation efficiency.

[0023] Preferably, the parallel computing step includes: dividing the convolution operator or the fully connected operator according to four dimensions, splitting the operator into multiple parallel parts, and mapping the parallel parts to different computing cores to complete the calculation, so as to increase the computing parallelism and thus improve the computing efficiency.

[0024] Preferably, the parallel computing step includes the following three sub-steps:

[0025] Step M1: During the forward event-based parallel computing process, AER events are also propagated between layers. Based on the fan-out-first computing method, the change in the inner membrane potential of each core is calculated. Then, according to the mapping configuration information, if operator segmentation based on the input channel dimension occurs, partial summation and aggregation are performed before activation. If there is no operator segmentation based on the input channel dimension, the activation operation is performed directly.

[0026] Step M2: in the backward event-based parallel weight gradient calculation process, the influence of the previous pulse activity on the weight gradient is calculated, and then whether to perform partial sum aggregation is determined according to the mapping configuration information;

[0027] Step M3, during the backward event-type parallel modulation factor propagation calculation process, the modulation factor code is propagated to the corresponding parallel computing core of the next layer according to the filtering conditions, and the factor code also indicates the effective modulation information of each computing core; then, according to the modulation factor code, the convolution result of the corresponding position output error and the converted weight kernel is calculated, where the converted weight kernel is the same as the forward weight kernel after rotating 180° and exchanging the input and output channels. Similarly, whether to perform partial sum aggregation is determined according to the mapping configuration information.

[0028] The present invention also provides an event-based parallel online learning neuromorphic computing system, comprising a plurality of computing cores, a Mesh-Tree hybrid on-chip routing communication network, a global control module, a configuration and monitoring module, and an Argmax decision module;

[0029] The computing core includes a computing engine, a memory pool, a local scheduler, and a special function unit. The computing engine includes an issuing computing engine and a learning computing engine. The memory pool is used to store data related to neuron dynamics, including membrane potential, modulation factor, weight, and weight gradient. The learning computing engine supports the completion of forward and backward event-based parallel computing. The issuing computing engine supports the completion of proxy gradient calculation, activation, and pooling operator operations. The special function unit implements partial sum aggregation and weight update operations in multiple computing cores.

[0030] The on-chip routing communication network adopts a hybrid topology of Mesh and Tree. Mesh supports scalable multi-core interconnection communication, while Tree routing provides a lower-cost communication method between the divided computing cores, improving the communication efficiency of the local computing core group.

[0031] The global control module implements hierarchical scheduling, combining coarse-grained tokens and fine-grained local control commands. Tokens are used to determine the type of calculation and start distributed computing cores, coordinating the operation sequence between multiple cores.

[0032] Preferably, the learning computing engine includes multiple parallel computing channels, each channel includes a configurable computing path and a multiplier and adder; at the same time, in order to support the calculation of multiple computing channels of a single computing core, the multiplication and addition calculation results of multiple channels are fed to the addition tree for result aggregation operations. In order to balance the computing efficiency and resource consumption, an addition tree structure with feedback is adopted to realize batch aggregation operations of data in the channel.

[0033] Preferably, the process of implementing hierarchical scheduling by the global control module includes the following steps:

[0034] Step 1: Before on-chip learning begins, the workload is physically mapped to different computing cores, and the configuration module initializes the structural parameters and states;

[0035] Step 2: The global control module issues tokens to control different computing cores to perform corresponding forward and backward computing operations;

[0036] Step 3: When the computing core receives the token, the local control unit parses the computing type and coordinates internal computing resources to complete the relevant computing tasks;

[0037] Step 4: After the computing core completes the computing task, it notifies the global control module, and the global control module performs a new round of scheduling control based on the status information fed back by all computing cores.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The sparse computing steps (event-driven) and parallel computing steps of the present invention solve the low efficiency problem existing in large-scale neuromorphic hardware to realize online learning. At the same time, the online learning framework based on neural modulation and the sample learning steps of the present invention alleviate the compatibility problem and the large memory consumption problem of the current customized online learning processor. The computing system of the present invention efficiently realizes the computing method of the present invention. At the same time, the computing engine architecture based on the configurable data path and the flexible NoC communication improve the compatibility, scalability and learning performance of the neuromorphic processor supporting online learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0041] Figure 1 Schematic diagram of an event-based parallel online learning neuromorphic computing method and system in an embodiment of the present invention;

[0042] Figure 2 It is a schematic diagram of forward event-based calculation and backward weight gradient event-based calculation in the convolution operator (based on wide and high dimensional blocks) in an embodiment of the present invention;

[0043] Figure 3 is a schematic diagram of multi-core parallel mapping in an embodiment of the present invention;

[0044] Figure 4 It is a schematic diagram of forward parallel event-based calculation and backward parallel weight gradient event-based calculation in the convolution operator (based on wide and high dimensional blocks) in an embodiment of the present invention;

[0045] Figure 5 is a schematic diagram of a local / global neural modulation supervised learning framework in an embodiment of the present invention;

[0046] Figure 6 is a schematic diagram of a neuromorphic hardware architecture supporting online learning in an embodiment of the present invention;

[0047] Figure 7 It is a schematic diagram of the computing engine architecture (learning and issuing computing engines) in an embodiment of the present invention;

[0048] Figure 8 is a schematic diagram of the forward event membrane potential update calculation mapping in an embodiment of the present invention;

[0049] Fig. 9 It is a schematic diagram of forward computing pooling-issuing and other fusion operator computing mapping in an embodiment of the present invention;

[0050] Fig.10 It is a schematic diagram of backward modulation factor propagation calculation mapping in an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0052] The present invention provides an event-based parallel online learning neuromorphic computing method and system, wherein the method includes a framework construction step, a sample learning step, a sparse computing step and a parallel computing step; the system includes a computing core, a Mesh-Tree hybrid on-chip routing communication network (Network on Chip, NoC), a configuration and monitoring module, a global control module and an Argmax decision module.

[0053] Embodiment 1:

[0054] Figure 1 Schematic diagram of an event-based parallel online learning neuromorphic computing method and system in an embodiment of the present invention.

[0055] Figure 1 As shown, this embodiment provides an event-based parallel online learning neuromorphic computing method, comprising the following steps:

[0056] The framework construction steps unify and formalize a variety of mainstream neuromorphic online learning algorithms, and build an online learning framework based on neural modulation to guide the general and scalable design of neuromorphic hardware processors.

[0057] Specifically, the online learning framework is based on the three-factor learning rule, which provides a basis for explaining how the brain learns complex tasks by linking neuromodulators with local plasticity. The formula is described as:

[0058]

[0059] in, is the gradient of the weight parameter, Pre and Post represent the activities of presynaptic and postsynaptic neurons respectively, M represents the neuromodulator, F1 represents the influence process of presynaptic and postsynaptic neurons, and F2 represents the influence process of neuromodulator on synaptic activity.

[0060] The sample learning step, based on the online learning framework, uses batch parameter update averaging to improve the stability of learning / training, while reducing memory requirements through parameter gradient accumulation and delayed update.

[0061] Specifically, by streaming the samples in a batch, that is, calculating the corresponding weight parameter gradients according to the rules of the online learning framework, and then accumulating the gradient calculation results in a batch and combining them with weight delayed update, low memory usage is achieved.

[0062] The sparse computing step is based on the online learning framework. In the forward process, it simulates the impact of the presynaptic neuron's firing on the postsynaptic neuron. In the backward process, it skips the "zero value" related calculations to improve computing efficiency.

[0063] Specifically, the sparse calculation step includes the following sub-steps:

[0064] Step S1, in the forward event-based calculation process, Address Event Representation (AER) is used to propagate pulses between layers, and the influence of presynaptic pulses on the membrane potential of postsynaptic neurons is calculated based on the fan-out (axon) priority calculation method.

[0065] More specifically, step S1 includes the following sub-steps:

[0066] Step S1.1, updating the membrane potential in a fan-out axon-first manner, includes: firstly performing compensation in combination with the attenuation factor of the neuron model to facilitate the operator fusion operation of step 2.

[0067] Step 1.2: The membrane potential attenuation operator, bias calculation operator, pooling operator, proxy gradient calculation operator, and release activation operator are merged into one operator to reduce the memory access frequency of the membrane potential, thereby improving the calculation efficiency.

[0068] Step S2, in the backward event-type weight gradient calculation process, the calculation is based on the sparsity of the presynaptic spike activity (or defined as the eligibility trace, etc.). The process is similar to step S1. The calculation is performed based on the influence of the pre-spike activity on the weight gradient, while ignoring the calculation related to the "zero value" activity.

[0069] Step S3, during the backward event-type modulation factor (or error) propagation calculation process, the modulation factor coding is calculated by combining pooling and proxy gradient. The modulation factor coding indicates valid modulation (error) information, avoids calculating invalid modulation (or error) information in the backward direction, and is used to improve calculation efficiency.

[0070] The parallel computing step combines sparse event-based computing to split the operator, and then deploys the split operators in multiple cores for parallel computing to optimize computing efficiency.

[0071] Specifically, by dividing the convolution operator or fully connected operator according to four dimensions (width, height, input channel and output channel, full connection can be regarded as a special case with width and height of 1), the operator is split into multiple parallel parts, and the parallel parts are mapped to different computing cores to complete the calculation, so as to increase the computing parallelism and thus improve the computing efficiency.

[0072] Specifically, parallel computing is completed using multiple computing cores, and each computing core deploys the segmented operators. Taking forward computing as an example, after the operator is divided, the input activation pulse is allocated based on the address event representation (AER). By setting filtering conditions for the computing core and combining the image block configuration information mapped inside the computing core, the boundary replication problem caused by the convolution operator in wide and high dimensional blocks can be easily handled, thereby completing the preparation of input data. For operator blocks based on the input channel dimension, by creating a base core, the intermediate calculation results in each block computing core are iteratively accumulated to achieve partial and aggregation and final activation release. At the same time, the feedforward accumulation topology can also be organized in the form of an addition tree to achieve aggregate computing. For operator blocks based on the output channel dimension, the data of different output channels in each computing core is reorganized through the image block configuration information and the routing information table.

[0073] More specifically, the parallel computing step includes the following three sub-steps:

[0074] Step M1: During the forward event-based parallel computing process, AER events are also propagated between layers (the convolution operator needs to consider the impact of the AER boundary on the membrane potential of the mapped neuron). Based on the fan-out (axon) priority calculation method, the change in the membrane potential of each core is calculated. Then, according to the mapping configuration information, if the operator segmentation based on the input channel dimension occurs, partial sum aggregation and activation operation are performed; if there is no operator segmentation based on the input channel dimension, activation operation is performed directly.

[0075] Step M2, during the backward event-type parallel weight gradient calculation process, the influence of the previous pulse activity (the convolution operator needs to consider the previous pulse activity boundary) on the weight gradient is calculated, and then the mapping configuration information is used to decide whether to perform partial sum aggregation (corresponding to whether operator segmentation based on width, height or output channel dimension occurs).

[0076] Step M3, in the backward event-type parallel modulation factor (or error) propagation calculation process, the modulation factor coding is propagated to the corresponding parallel computing core of the next layer according to the filtering conditions, and the factor coding also indicates the effective modulation (or error) information of each computing core; then, according to the modulation factor coding, the convolution result of the corresponding position output error and the converted weight kernel is calculated (the convolution needs to consider the influence of the boundary output error information), where the converted weight kernel is equivalent to the forward weight kernel after rotating 180° (convolution) and exchanging the input and output channels. Similarly, whether to perform partial and aggregation (corresponding to whether the operator segmentation based on the output channel dimension occurs) is determined according to the mapping configuration information.

[0077] Example 2: Event-based calculation method

[0078] Online learning / training is divided into three main stages in the present invention: feed forward (FF), backward modulation factor (error) propagation (MP) and weight gradient (WG) calculation stage. The calculation method of the MP stage combines the proxy gradient and pooling to form coding, which is convenient for calculating the effective modulation factor. The calculation process can refer to Example 8 given in the present invention. Figure 2 The event-based calculation method of the convolution operator FF and WG stages in the present invention is given, which only considers the influence of active pulse events or effective presynaptic neuron activities on the postsynaptic neuron membrane potential or weight gradient, avoids invalid calculations related to non-zero elements, and improves calculation efficiency.

[0079] Specifically, the event calculation mainly includes the following steps:

[0080] Step 1: Save input spikes or presynaptic neuron activities in the event queue in AER format;

[0081] Step 2: Rotate the weight kernel or error kernel 180° to access the update amount position by position on subsequent steps;

[0082] Step 3: Read a single AER event and update the corresponding membrane potential or weight gradient. The specific update amount is obtained according to step 2. Repeat step 3 until the event queue is empty.

[0083] Example 3: Multi-core parallel computing method

[0084] In the multi-core parallel computing method of the present invention, convolution operators and fully connected operators are divided by width, height, input channels and output channels, and then deployed to multiple computing cores for parallel computing to improve computing efficiency. Figure 3 It explains the process of deploying the computing core after dividing the network into blocks based on width and height dimensions. After the convolution operator and the fully connected operator are split, they are mapped to multiple computing cores and the calculation is completed in distributed parallel.

[0085] Specifically, the parallel computation includes that, in the convolution operator, the update of the forward membrane potential is completed in parallel by input partitions and shared weights. In the reverse phase, partial weight gradients are calculated in a distributed manner, and the final weight gradients are obtained by aggregating these partial weight gradient results; the forward membrane potential update calculation of the fully connected operator is realized by sharing input and partition weights. Therefore, the computational behavior of weight gradients and errors in the reverse fully connected operation is similar to the computation of membrane potential and weight gradients in the convolution operation. The parallel computation method combines the AER event representation, and image partitions can be directly implemented by setting filter conditions within the computing core, parsing AER addresses and caching corresponding AER events to prepare input data. This event-based data preparation method can be directly applied to the fully connected operator. However, for the convolution operator, boundary replication of the input feature partitions is necessary to ensure that the parallel distributed computing results are consistent with the single-core computing results.

[0086] Example 4: Parallel event-based computing method

[0087] Figure 4 The parallel event-based computing method in the present invention is described, which is a computing method further combined with Embodiment 2 and Embodiment 3.

[0088] Specifically, the multi-core data preparation is completed based on the AER event processing method provided in Example 3, and the computing task is completed in a distributed manner in combination with the event-based computing method provided in Example 2. In the final stage, data of multiple computing cores are merged according to the block strategy. Figure 4 The schematic diagram given also divides the convolution operator into blocks in width and height dimensions. In the final stage, the membrane potential part and the result need to be spliced ​​and the weight gradient part and the sum need to be aggregated to obtain the same result as the single-core calculation.

[0089] Example 5: Learning framework based on local-global neural modulation

[0090] Figure 5 The present invention describes a learning framework based on neural modulation, including learning methods in which modulation factors come from the global, local, and no neural modulation factors.

[0091] Specifically, the global modulation factor corresponds to the modulation factor (error) from the layer-by-layer propagation of the last layer, which is consistent with the global back-propagation process in ANN; the local modulation factor corresponds to the modulation factor (error) from the direct calculation of the auxiliary layer, thus alleviating the backward locking problem caused by the global modulation; the process without neural modulation corresponds to unsupervised bionic learning, such as STDP, SDSP and other learning methods.

[0092] Example 6: Online Learning on Neuromorphic Hardware

[0093] Figure 6 The hardware architecture and system of the present invention supporting event-based parallel online learning neuromorphic computing are described, including multiple computing cores, a Mesh-Tree on-chip routing communication network, a configuration and monitoring module, a global control module, and an Argmax decision module.

[0094] Figure 7 The computing core architecture of the present invention is described, including a computing engine, a memory pool, a local scheduler, a special function unit, etc. The computing engine includes a distribution computing engine and a learning computing engine. The memory pool mainly stores data related to neuron dynamics, such as membrane potential, modulation factor, weight, weight gradient, etc. The learning computing engine mainly supports forward and backward event-based parallel computing; the distribution computing engine mainly supports the completion of proxy gradient calculation, activation, pooling and other operator operations; the special function unit mainly implements operations such as partial sum aggregation and weight update calculation in multiple computing cores.

[0095] Specifically, the learning computing engine of the present invention comprises a plurality of parallel computing channels, each channel being composed of a configurable computing path and a multiplier-adder; at the same time, in order to support the calculation of multiple computing channels of a single computing core, the multiplication and addition calculation results of the multiple channels are fed to an addition tree for result aggregation operations. In order to balance the computing efficiency and resource consumption, an addition tree structure with feedback can be used to realize batch aggregation operations of data within the channel.

[0096] Example 7: Forward Computation Mapping Based on Leakage Integrated Release Model

[0097] The forward FF stage mainly involves three basic calculations: membrane potential update, pooling and excitation calculation, and membrane potential reset after activation. Figure 8The forward membrane potential update mapping process based on the Leaky Integrate and Fire (LIF) neuron model of the present invention is described. Specifically, in the event-driven membrane potential update process, the LCE is set to the multiply-add mode, which is implemented by configuring the multiplexer. Then, the pulse AER events are extracted in sequence, and the weights, attenuation terms and membrane potentials involved in the affected area are piped into the multi-channel LCE, and the updated membrane potential is then written back. The output channel weights are stored in a separate entry (stored by output channel priority) and then arranged according to the position and input channel order; the membrane potential is also stored in parallel according to the output channel priority to support multi-channel calculations.

[0098] Fig. 9 The subsequent calculation process of the FF stage is further described. Specifically, it includes:

[0099] Step 1: LCE is configured in multiply-add mode.

[0100] Step 2: The operands, including attenuation, membrane potential, and bias vector, are sequentially transmitted to the LCE according to the pooling range to update the corresponding membrane potential.

[0101] Step 3: The updated membrane potential vector is further transferred to the multi-channel FCE. In the FCE, the membrane potential within each channel pooling window is combined with the head and tail flags of the pooling data and processed sequentially to complete the maximum pooling and proxy gradient operations.

[0102] Step 4: Generate the final proxy gradient-pooling code using the obtained pooling code and proxy gradient code. At the same time, generate the pulse emission flag in parallel to facilitate the generation and transmission of pulse AER events.

[0103] Example 8: Backward Modulation Factor Calculation Mapping Based on LIF Model

[0104] Fig.10 The backward modulation factor propagation calculation mapping process based on the LIF model of the present invention is described. The modulation propagation calculation can be regarded as the dual form of the forward calculation, performing the convolution of the virtual output error (or membrane potential gradient) with the 180° rotation weight, while exchanging the input-output channels. The virtual output error is obtained by performing a reverse pooling operation on the output error, and the proxy gradient-pooling encoding retains the necessary address information and pooling information of the non-zero error to facilitate the propagation of the modulation factor. At the same time, the weights are stored in parallel according to the output channel priority, and aggregation between the output channels is required when performing the modulation propagation calculation.

[0105] Specifically, the modulation factor propagation calculation of the present invention includes:

[0106] Step 1: Parse the proxy gradient from the previous layer - pooling the encoded AER to avoid unnecessary propagation of zero-value modulation.

[0107] Step 2: Read the virtual output error and rotation weights for multiplication and accumulation operations, calculate the channel-level intermediate results in the convolution window, and perform the final aggregation through the back-end addition tree and feedback accumulation path.

[0108] Step 3: Repeat steps 1 and 2 until the proxy gradient-pooling encoding AER queue is empty.

[0109] Embodiment 9:

[0110] This embodiment provides an event-based parallel online learning neuromorphic computing system, including multiple computing cores, a Mesh-Tree hybrid on-chip routing communication network, a global control module, a configuration and monitoring module, and an Argmax decision module.

[0111] Specifically, the computing core includes a computing engine, a memory pool, a local scheduler, and a special function unit. The computing engine includes a firing compute engine (FCE) and a learning compute engine (LCE). The memory pool is used to store data related to neuronal dynamics, including membrane potential, modulation factors, weights, and weight gradients. The learning compute engine supports the completion of forward and backward event-based parallel computing. The firing compute engine supports the completion of operator operations such as proxy gradient calculation, activation, and pooling. The special function unit implements partial and aggregate, and weight update operations in multiple computing cores.

[0112] More specifically, the learning computing engine includes multiple parallel computing channels, each channel includes a configurable computing path and a multiplier and adder; at the same time, in order to support the calculation of multiple computing channels of a single computing core, the multiplication and addition calculation results of multiple channels are fed to the addition tree for result aggregation operations. In order to balance computing efficiency and resource consumption, an addition tree structure with feedback is adopted to realize batch aggregation operations of data in the channel.

[0113] Specifically, the on-chip routing communication network (NoC) adopts a hybrid topology of Mesh and Tree. Mesh supports scalable multi-core interconnection communication, while Tree routing provides a lower-cost communication method between the divided computing cores, improving the communication efficiency of the local computing core group.

[0114] Specifically, the global control module implements hierarchical scheduling, combining coarse-grained tokens and fine-grained local control commands. Tokens are used to determine the type of calculation and start distributed computing cores, coordinating the operation sequence between multiple cores.

[0115] Specifically, the process of implementing hierarchical scheduling by the global control module includes the following steps:

[0116] Step 1: Before on-chip learning begins, the workload is physically mapped to different computing cores, and the configuration module initializes the structural parameters and states;

[0117] Step 2: The global control module issues tokens to control different computing cores to perform corresponding forward and backward computing operations;

[0118] Step 3: When the computing core receives the token, the local control unit parses the computing type and coordinates internal computing resources to complete the relevant computing tasks;

[0119] Step 4: After the computing core completes the computing task, it notifies the global control module. The global control module performs a new round of scheduling control based on the status information fed back by all computing cores.

[0120] The configuration and monitoring module and the Argmax decision module are existing technologies and will not be described in detail here.

[0121] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0122] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. An event-based parallel online learning neuromorphic computing method, characterized in that: The following steps are involved: The framework construction step unifies and formalizes a variety of mainstream neuromorphic online learning algorithms, and builds an online learning framework based on neural modulation to guide the general and scalable design of neuromorphic hardware processors; The sample learning step, based on the online learning framework, uses batch parameter update averaging to improve the stability of learning / training, while reducing memory requirements by parameter gradient accumulation and delayed update; The sparse computing step, based on the online learning framework, simulates the effect of the presynaptic neuron firing on the postsynaptic neuron in the forward process, and skips the "zero value" related calculations in the backward process to improve computing efficiency; The parallel computing step is based on the online learning framework and combined with the sparse event-based computing to split the operators, and then deploy the split operators in multiple cores for parallel computing to optimize the computing efficiency.

2. The event-based parallel online learning neuromorphic computing method according to claim 1, characterized in that: The online learning framework is based on the three-factor learning rule, which provides a basis for explaining how the brain learns complex tasks by linking neuromodulators to local plasticity. The formula is described as: in, is the gradient of the weight parameter, Pre and Post represent the activities of presynaptic and postsynaptic neurons respectively, M represents the neuromodulator, F1 represents the influence process of presynaptic and postsynaptic neurons, and F2 represents the influence process of neuromodulator on synaptic activity.

3. The event-based parallel online learning neuromorphic computing method according to claim 1, characterized in that: In the sample learning step: by streaming the samples in a batch, that is, according to the rules of the online learning framework, the corresponding weight parameter gradient is calculated, and then the gradient calculation results in a batch are accumulated and combined with the weight delay update.

4. The event-based parallel online learning neuromorphic computing method according to claim 1, characterized in that: The sparse calculation step includes the following sub-steps: Step S1, in the forward event-based calculation process, address event representation is used to propagate pulses between layers, and the influence of presynaptic pulses on the membrane potential of postsynaptic neurons is calculated based on the fan-out priority calculation method; Step S2, in the backward event-type weight gradient calculation process, the calculation is performed based on the sparsity of the presynaptic pulse activity. The process is similar to step S1, and the calculation is performed based on the influence of the presynaptic pulse activity on the weight gradient, while ignoring the calculation related to the "zero value" activity; Step S3, in the process of backward event-type modulation factor propagation calculation, the modulation factor coding is calculated by combining pooling and proxy gradient, and the modulation factor coding indicates valid modulation information to avoid calculating invalid modulation information in the backward direction.

5. The event-based parallel online learning neuromorphic computing method according to claim 4, characterized in that: The step S1 includes the following sub-steps: Step S1.1, updating the membrane potential in a fan-out axon-first manner, including: firstly performing compensation in combination with the attenuation factor of the neuron model to facilitate the operator fusion operation in step 2; Step 1.2: The membrane potential attenuation operator, bias calculation operator, pooling operator, proxy gradient calculation operator, and release activation operator are merged into one operator to reduce the memory access frequency of the membrane potential, thereby improving the calculation efficiency.

6. The event-based parallel online learning neuromorphic computing method according to claim 1, characterized in that: The parallel computing step includes: dividing the convolution operator or the fully connected operator according to four dimensions, splitting the operator into multiple parallel parts, and mapping the parallel parts to different computing cores to complete the calculation, so as to increase the computing parallelism and thus improve the computing efficiency.

7. The event-based parallel online learning neuromorphic computing method according to claim 6, characterized in that: The parallel computing step includes the following three sub-steps: Step M1: During the forward event-based parallel computing process, AER events are also propagated between layers. Based on the fan-out-first computing method, the change in the inner membrane potential of each core is calculated. Then, according to the mapping configuration information, if operator segmentation based on the input channel dimension occurs, partial sum aggregation and activation operation are performed; If there is no operator splitting based on the input channel dimension, the activation operation is performed directly; Step M2: in the backward event-based parallel weight gradient calculation process, the influence of the previous pulse activity on the weight gradient is calculated, and then whether to perform partial sum aggregation is determined according to the mapping configuration information; Step M3, in the backward event-type parallel modulation factor propagation calculation process, the modulation factor code is propagated to the corresponding parallel computing core of the next layer according to the filtering condition, and the factor code also indicates the effective modulation information of each computing core; Then, according to the modulation factor encoding, the convolution result of the output error at the corresponding position and the converted weight kernel is calculated, where the converted weight kernel is the same as the forward weight kernel after rotating 180° and exchanging the input and output channels. Similarly, whether to perform partial sum aggregation is determined according to the mapping configuration information.

8. An event-based parallel online learning neuromorphic computing system, characterized in that: It includes multiple computing cores, a Mesh-Tree hybrid on-chip routing communication network, a global control module, a configuration and monitoring module, and an Argmax decision module; The computing core includes a computing engine, a memory pool, a local scheduler, and a special function unit. The computing engine includes a distribution computing engine and a learning computing engine. The memory pool is used to store data related to neuron dynamics, including membrane potential, modulation factor, weight, and weight gradient; the learning computing engine supports the completion of forward and backward event-based parallel computing; the distribution computing engine supports the completion of proxy gradient calculation, activation, and pooling operator operations; the special function unit implements partial sum aggregation and weight update operations in multiple computing cores; The on-chip routing communication network adopts a hybrid topology of Mesh and Tree. Mesh supports scalable multi-core interconnection communication, while Tree routing provides a lower-cost communication method between the divided computing cores, thereby improving the communication efficiency of the local computing core group. The global control module implements hierarchical scheduling, combining coarse-grained tokens and fine-grained local control commands. The tokens are used to determine the type of calculation and start distributed computing cores, coordinating the operation sequence between multiple cores.

9. The event-based parallel online learning neuromorphic computing system according to claim 8, characterized in that: The learning computing engine includes multiple parallel computing channels, each channel includes a configurable computing path and a multiplier and adder; at the same time, in order to support the calculation of multiple computing channels of a single computing core, the multiplication and addition calculation results of multiple channels are fed to the addition tree for result aggregation operation. In order to balance the computing efficiency and resource consumption, an addition tree structure with feedback is adopted to realize the batch aggregation operation of data in the channel.

10. The event-based parallel online learning neuromorphic computing system according to claim 8, characterized in that: The process of implementing hierarchical scheduling by the global control module includes the following steps: Step 1: Before on-chip learning begins, the workload is physically mapped to different computing cores, and the configuration module initializes the structural parameters and states; Step 2: The global control module issues tokens to control different computing cores to perform corresponding forward and backward computing operations; Step 3: When the computing core receives the token, the local control unit parses the computing type and coordinates internal computing resources to complete the relevant computing tasks; Step 4: After the computing core completes the computing task, it notifies the global control module, and the global control module performs a new round of scheduling control based on the status information fed back by all computing cores.

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