Filter, preparation method thereof and electronic equipment

Abstract

The invention provides a filter, a preparation method thereof and electronic equipment. The filter comprises a substrate provided with conductive columns, a first structural layer is arranged on the first surface of the substrate, and a second structural layer, a first insulating layer, a lead layer, a second insulating layer and a bonding pad layer are arranged on the second surface of the substrate; each of the first structural layer and the second structural layer comprises a connecting electrode connected with the conductive column, the second structural layer further comprises a capacitor structure, the lead layer comprises at least one lead, the leads are connected with the capacitor structure, the pad layer comprises at least one pad, and the pads are connected with the leads; materials of the first insulating layer and the second insulating layer include organic materials. By arranging the first insulating layer and the second insulating layer which are made of organic materials, the performance stability and reliability of the filter can be improved, and the performance of the filter is improved.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of semiconductor technology, and in particular to a filter and a manufacturing method thereof, and an electronic device. Background Art

[0002] As an important component of communication terminals, filters can solve the mutual interference problem in the process of signal transmission and improve spectrum utilization. With the development of mobile communication technology, mobile communication systems require filters with small area, high performance and good consistency. Integrated Passive Devices (IPDs) are widely used in radio frequency (RF) front-end chips in wireless communication equipment due to their superior independent passive component characteristics.

[0003] At present, existing filters have problems such as low performance stability and reliability. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a filter and a preparation method thereof, and an electronic device to solve the problems of low performance stability and reliability of existing filters.

[0006] On the one hand, the present disclosure provides a filter, including a substrate, in which a conductive column is arranged in the substrate and passes through the substrate in the thickness direction, a first structural layer is arranged on the first surface of the substrate, a second structural layer is arranged on the second surface of the substrate, a first insulating layer is arranged on the side of the second structural layer away from the substrate, a lead layer is arranged on the side of the first insulating layer away from the substrate, a second insulating layer is arranged on the side of the lead layer away from the substrate, and a pad layer is arranged on the side of the second insulating layer away from the substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive column, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, and the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0007] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the substrate; the orthographic projection of the second electrode plate on the substrate is within the range of the orthographic projection of the capacitor dielectric layer on the substrate.

[0008] In an exemplary embodiment, the orthographic projection of the capacitor dielectric layer on the base substrate is located within the range of the orthographic projection of the first electrode plate on the base substrate.

[0009] In an exemplary embodiment, along a direction away from the substrate, areas of the first electrode plate, the capacitor dielectric layer, and the second electrode plate decrease in sequence.

[0010] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, there is a first distance between an edge of the first electrode plate and an edge of the capacitor dielectric layer, and the first distance is greater than or equal to 50 nm.

[0011] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, there is a second distance between an edge of the capacitor dielectric layer and an edge of the second electrode plate, and the second distance is greater than or equal to 50 nm.

[0012] In an exemplary embodiment, the first electrode plate includes a seed layer disposed on the second surface of the substrate and a conductive layer disposed on a side of the seed layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer disposed on the second surface of the substrate and a conductive layer disposed on a side of the seed layer away from the substrate.

[0013] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

[0014] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are disposed in the same layer and are simultaneously formed by the same patterning process.

[0015] In an exemplary embodiment, the orthographic projection of the connection electrode in the second structure layer on the base substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

[0016] In an exemplary embodiment, the first electrode plate includes a seed layer disposed on the second surface of the substrate, a conductive layer disposed on a side of the seed layer away from the substrate, and a conductive protective layer disposed on a side of the conductive layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer disposed on the second surface of the substrate, a conductive layer disposed on a side of the seed layer away from the substrate, and a conductive protective layer disposed on a side of the conductive layer away from the substrate.

[0017] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, the material of the conductive protection layer includes titanium, and the thickness of the titanium layer is 10 nm to 200 nm.

[0018] In an exemplary embodiment, the first electrode plate and the connecting electrode are disposed in the same layer and are simultaneously formed by a same damascene process.

[0019] In an exemplary embodiment, the first electrode plate and the connection electrode are respectively formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connection electrode.

[0020] In an exemplary embodiment, the second electrode plate has a stacked structure of titanium layer / copper layer / titanium layer, or a stacked structure of titanium layer / aluminum layer / titanium layer, wherein the thickness of the titanium layer is 30nm to 50nm, and the thickness of the copper layer or the aluminum layer is 200nm to 400nm.

[0021] In an exemplary embodiment, the connection electrode in the first structural layer includes a seed layer and a conductive layer disposed on a side of the seed layer away from the substrate, the seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

[0022] In an exemplary embodiment, the first structure layer further includes a protection layer disposed on a side of the connection electrode away from the base substrate, the material of the protection layer includes an organic material, and the thickness of the protection layer is 1 μm to 10 μm.

[0023] In an exemplary embodiment, a cross-sectional shape of the conductive pillar in a direction perpendicular to the base substrate includes a pillar shape, a cone shape, or an hourglass shape.

[0024] On the other hand, the present disclosure also provides an electronic device, comprising the aforementioned filter.

[0025] In another aspect, the present disclosure further provides a method for preparing a filter, comprising:

[0026] forming a metallized through-hole substrate, wherein the substrate substrate is provided with a conductive column penetrating the substrate substrate in a thickness direction;

[0027] A first structural layer is formed on one side of the first surface of the base substrate, a second structural layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on the side of the second structural layer away from the base substrate, a lead layer is arranged on the side of the first insulating layer away from the base substrate, a second insulating layer is arranged on the side of the lead layer away from the base substrate, and a pad layer is arranged on the side of the second insulating layer away from the base substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0028] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the substrate; the orthographic projection of the second electrode plate on the substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the substrate, and the orthographic projection of the capacitor dielectric layer on the substrate is located within the range of the orthographic projection of the first electrode plate on the substrate.

[0029] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are disposed in the same layer and are simultaneously formed by the same patterning process.

[0030] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are arranged in the same layer and are formed simultaneously through the same damascene process.

[0031] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode in the second structure layer.

[0032] In an exemplary embodiment, the capacitor dielectric layer and the second electrode plate are respectively formed by a patterning process including a dry etching process.

[0033] In another aspect, the present disclosure further provides a method for preparing a filter, comprising:

[0034] Forming a metallized blind hole substrate, wherein the substrate substrate is provided with a conductive column that does not penetrate the substrate substrate in a thickness direction;

[0035] A second structure layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on a side of the second structure layer away from the base substrate, a lead layer is arranged on a side of the first insulating layer away from the base substrate, a second insulating layer is arranged on a side of the lead layer away from the base substrate, and a pad layer is arranged on a side of the second insulating layer away from the base substrate;

[0036] Turning over the substrate, and performing a thinning process on the first surface of the substrate until the conductive pillars are exposed, wherein the first surface and the second surface are surfaces facing away from each other;

[0037] forming a first structural layer on one side of the first surface of the substrate;

[0038] The first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the materials of the first insulating layer and the second insulating layer include organic materials.

[0039] The filter and its preparation method, and the electronic device provided by the present disclosure can not only effectively reduce the parasitic capacitance between the various conductive layers, but also effectively avoid poor drilling and corrosion, effectively improve the performance stability and reliability of the filter, and improve the performance of the filter.

[0040] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0042] Figure 1 It is a structural schematic diagram of a filter according to an exemplary embodiment of the present disclosure;

[0043] Figure 2A and Figure 2B A schematic diagram of a metallized TGV substrate for forming a filter disclosed in the present invention;

[0044] Figure 3A and Figure 3B A schematic diagram of forming a first structural layer of a filter disclosed in the present invention;

[0045] Figure 4 This is a schematic diagram of a filter disclosed in the present invention after a second conductive layer is formed;

[0046] Figure 5 This is a schematic diagram of a filter disclosed in the present invention after a surface insulating layer is formed;

[0047] Figure 6 This is a schematic diagram of a filter disclosed in the present invention after forming a second pole plate;

[0048] Figure 7 This is a schematic diagram of a filter disclosed in the present invention after a first insulating layer is formed;

[0049] Figure 8 This is a schematic diagram of a filter disclosed in the present invention after forming a lead layer;

[0050] Fig. 9 This is a schematic diagram of a filter disclosed in the present invention after a second insulating layer is formed;

[0051] Fig.10 It is a schematic diagram of the structure of another filter of an exemplary embodiment of the present disclosure;

[0052] Fig.11 is a schematic cross-sectional view of a capacitor structure of an exemplary embodiment of the present disclosure;

[0053] FIG. 12A to FIG. 12E A schematic diagram of forming a first structural layer and a second conductive layer for another filter disclosed in the present invention;

[0054] Fig.13 This is a schematic diagram of another filter disclosed in the present invention after forming a capacitor dielectric layer;

[0055] Fig.14 This is a schematic diagram of another filter disclosed in the present invention after forming a second pole plate;

[0056] Fig.15 It is a schematic diagram of a planar structure of a capacitor structure of an exemplary embodiment of the present disclosure;

[0057] Fig.16 It is a structural schematic diagram of another filter of the exemplary embodiment of the present disclosure;

[0058] Fig.17A and Fig. 17B A schematic diagram of a metallized BGV substrate for forming another filter disclosed in the present invention;

[0059] 18A to 18D A schematic diagram of forming a second conductive layer for another filter disclosed in the present invention;

[0060] Fig.19 This is a schematic diagram of another filter disclosed in the present invention after forming a capacitor dielectric layer;

[0061] Fig. 20 This is a schematic diagram of another filter after forming a second pole plate according to the present disclosure;

[0062] Fig.21 This is a schematic diagram of another filter after forming a pad layer in the present disclosure;

[0063] Fig.22A and Fig. 22B It is a schematic diagram of another filter disclosed in the present invention after forming a first conductive layer;

[0064] Fig.23 The figure is a schematic diagram of the structure of another filter according to an exemplary embodiment of the present disclosure.

[0065] Description of reference numerals:

[0066] 10—substrate substrate; 11—protective layer; 12—surface insulating layer;

[0067] 31—first conductive column; 32—second conductive column; 41—first connecting electrode;

[0068] 42—second connecting electrode; 43—third connecting electrode; 44—fourth connecting electrode;

[0069] 45—fifth connecting electrode; 51—first electrode plate; 52—second electrode plate;

[0070] 53—capacitor dielectric layer; 61—first insulating layer; 62—second insulating layer;

[0071] 71—first lead; 72—second lead; 73—third lead;

[0072] 81—first pad; 82—second pad; 83—third pad;

[0073] 91—first through hole; 92—second through hole; 93—first blind hole;

[0074] 94—second blind hole; 100—first structural layer; 200—second structural layer. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0076] The proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The drawings described in this disclosure are only schematic diagrams of the structure, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0077] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0078] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0079] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0080] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0081] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0082] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0083] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0084] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0085] With the development of 5G technology, 5G frequency bands continue to increase, and the RF front-end is facing growing demand. In the 5G RF front-end, the filter device is one of the core components, and the number of filters in each 5G mobile phone is at least 50 or more. In order to meet the needs of miniaturization, high integration, high frequency bandwidth and low cost, through glass via (TGV) technology has gradually become a feasible technology for the design of passive filters (LC filters). Through glass via TGV technology refers to making a through hole on a glass substrate and filling the through hole with metal material to electrically connect the functional structure on the upper surface of the glass substrate and the functional structure on the lower surface of the glass substrate. Since glass materials have the advantages of good high-frequency characteristics, good insulation, low loss, and excellent Q value of glass core 3D inductors, compared with silicon (Si)-based IPDs, TGV-based IPDs can avoid the problem of high microwave loss of devices caused by poor silicon-based insulation. Compared with low-temperature co-fired ceramics (LTCC) and high-resistance silicon (HRSi)-based IPD filters, TGV-based IPDs have the characteristics of compact size, low insertion loss, good high-frequency performance and easy packaging. They can achieve better electrical performance and can play an important role in 5G NR and WiFi 6.

[0086] The present disclosure provides a passive filter, comprising a substrate, wherein the substrate is provided with a conductive column that penetrates the substrate in a thickness direction, a first structural layer is provided on a first surface of the substrate, a second structural layer is provided on a second surface of the substrate, a first insulating layer is provided on a side of the second structural layer away from the substrate, a lead layer is provided on a side of the first insulating layer away from the substrate, a second insulating layer is provided on a side of the lead layer away from the substrate, and a pad layer is provided on a side of the second insulating layer away from the substrate, wherein the first surface and the second surface are surfaces that are opposite to each other; the first structural layer and the second structural layer both comprise connecting electrodes connected to the conductive column, the second structural layer further comprises a capacitor structure, the lead layer comprises at least one lead connected to the capacitor structure, and the pad layer comprises at least one pad connected to the lead; and the material of the first insulating layer and the second insulating layer comprises an organic material.

[0087] In an exemplary embodiment, the thickness of the first insulating layer and the second insulating layer may be about 1 μm to 10 μm.

[0088] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the substrate; the orthographic projection of the second electrode plate on the substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the substrate, and the orthographic projection of the capacitor dielectric layer on the substrate is located within the range of the orthographic projection of the first electrode plate on the substrate.

[0089] In an exemplary embodiment, along a direction away from the substrate, areas of the first electrode plate, the capacitor dielectric layer, and the second electrode plate decrease in sequence.

[0090] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, there is a first distance between an edge of the first electrode plate and an edge of the capacitor dielectric layer, and the first distance is greater than or equal to 50 nm.

[0091] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, there is a second distance between an edge of the capacitor dielectric layer and an edge of the second electrode plate, and the second distance is greater than or equal to 50 nm.

[0092] Figure 1 FIG. 1 is a schematic diagram of a filter structure according to an exemplary embodiment of the present disclosure. Figure 1As shown, the main structure of the filter of the exemplary embodiment of the present disclosure may include a substrate 10, a first structure layer 100 and a second structure layer 200. The first structure layer 100 may be arranged on one side of the first surface of the substrate substrate 10, and the second structure layer 200 may be arranged on one side of the second surface of the substrate substrate 10. The first surface and the second surface are two surfaces of the substrate substrate 10 that are opposite to each other.

[0093] In an exemplary embodiment, a plurality of conductive pillars are embedded in the base substrate 10 , and the plurality of conductive pillars penetrate the base substrate 10 in the thickness direction, so that corresponding electrodes in the first structure layer 100 and the second structure layer 200 can be connected to each other through the plurality of conductive pillars.

[0094] In an exemplary embodiment, the plurality of conductive pillars may include at least a first conductive pillar 31 and a second conductive pillar 32, and the structures of the two conductive pillars may be substantially the same. On a plane parallel to the substrate, the shape of the conductive pillar may be circular or elliptical, and on a plane perpendicular to the substrate, the cross-sectional shape of the conductive pillar may be an hourglass shape.

[0095] In an exemplary embodiment, the first structure layer 100 may include at least a first connection electrode 41 and a second connection electrode 42 arranged on the first surface of the base substrate 10, and a protective layer 11 arranged on the side of the first connection electrode 41 and the second connection electrode 42 away from the base substrate, the first connection electrode 41 is connected to the first conductive column 31, the second connection electrode 42 is connected to the second conductive column 32, and the material of the protective layer 11 includes an organic material.

[0096] In an exemplary embodiment, the second structure layer 200 may include at least a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, and a capacitor structure disposed on the second surface of the base substrate 10, the fourth connection electrode 44 is connected to the first conductive pillar 31, and the fifth connection electrode 45 is connected to the second conductive pillar 32. The capacitor structure may include a first electrode plate 51 disposed on the second surface of the base substrate 10, a surface insulating layer 12 disposed on a side of the first electrode plate 51 away from the base substrate, and a second electrode plate 52 disposed on a side of the surface insulating layer 12 away from the base substrate.

[0097] In an exemplary embodiment, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, the fourth connection electrode 44 and the fifth connection electrode 45 are configured as a filter inductor coil routing to form a filter inductor of a three-dimensional spiral inductor structure. The first electrode plate 51 can be used as a lower electrode plate of the capacitor structure, and the second electrode plate 52 can be used as an upper electrode plate of the capacitor structure. The first electrode plate 51, the surface insulating layer 12 and the second electrode plate 52 constitute a filter capacitor of the MIM structure.

[0098] In an exemplary embodiment, the third connection electrode 43 , the fourth connection electrode 44 , the fifth connection electrode 45 and the first electrode plate 51 may be disposed in the same layer and simultaneously formed through the same patterning process.

[0099] In an exemplary embodiment, the filter may also include a first insulating layer 61 arranged on the side of the second structural layer 200 away from the base substrate, a lead layer arranged on the side of the first insulating layer 61 away from the base substrate, a second insulating layer 62 arranged on the side of the lead layer away from the base substrate, and a pad layer arranged on the side of the second insulating layer 62 away from the base substrate.

[0100] In an exemplary embodiment, the first insulating layer 61 may be provided with a first via hole, a second via hole, and a third via hole, the lead layer may include at least a first lead 71, a second lead 72, and a third lead 73, the first lead 71 is connected to the third connection electrode 43 through the first via hole, the second lead 72 is connected to the first electrode plate 51 through the second via hole, and the third lead 73 is connected to the second electrode plate 52 through the third via hole. The second insulating layer 62 may be provided with a fourth via hole, a fifth via hole, and a sixth via hole, the pad layer may include at least a first pad 81, a second pad 82, and a third pad 83, the first pad 81 is connected to the first lead 71 through the fourth via hole, the second pad 82 is connected to the second lead 72 through the fifth via hole, and the third pad 83 is connected to the third lead 73 through the sixth via hole.

[0101] In an exemplary embodiment, the materials of the first insulating layer 61 and the second insulating layer 62 include an organic material, and the thickness of the first insulating layer 61 and the second insulating layer 62 may be about 1 μm to 10 μm.

[0102] In an exemplary embodiment, the first connection electrode 41 and the second connection electrode 42 may include a stacked seed layer and a conductive layer, the seed layer is disposed on the first surface of the substrate, and the conductive layer is disposed on a side of the seed layer away from the substrate. The third connection electrode 43, the fourth connection electrode 44, the fifth connection electrode 45 and the first electrode plate 51 may each include a stacked seed layer and a conductive layer, the seed layer is disposed on the second surface of the substrate, and the conductive layer is disposed on a side of the seed layer away from the substrate.

[0103] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

[0104] In an exemplary embodiment, the second electrode plate 52 may have a sandwich laminate structure of Ti / Cu / Ti or a sandwich laminate structure of Ti / Al / Ti.

[0105] The following is an exemplary description of the preparation process of the filter. The "patterning process" mentioned in the present disclosure includes deposition of a film layer, coating of a photoresist on the film layer, mask exposure, development, etching, stripping of the photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the filter. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0106] In an exemplary embodiment, the preparation process of the filter of this embodiment may include the following steps.

[0107] (11) Forming a metallized TGV substrate. In an exemplary embodiment, forming a metallized TGV substrate may include:

[0108] (a1) providing a substrate 10, and forming a plurality of through holes on the substrate by laser induced etching, sandblasting, laser ablation or other processes, wherein the plurality of through holes may include at least a first through hole 91 and a second through hole 92, such as Figure 2A shown.

[0109] In an exemplary embodiment, the structures of the two through holes may be substantially the same, and both are through hole structures that penetrate the base substrate 10. On a plane parallel to the base substrate, the shape of the through hole may be circular or elliptical, and on a plane perpendicular to the base substrate, the cross-sectional shape of the through hole may be an hourglass shape, and the through hole is configured to accommodate a conductive column formed subsequently.

[0110] In an exemplary embodiment, the base substrate 10 may include a first surface and a second surface facing away from each other. In the following description, the lower surface of the base substrate 10 is the first surface, and the upper surface of the base substrate 10 is the second surface.

[0111] In an exemplary embodiment, the material of the base substrate may be alkali-free glass, quartz glass, etc., and the thickness of the base substrate may be about 0.2 mm to 0.3 mm. For example, the thickness of the base substrate may be about 0.25 mm.

[0112] In an exemplary embodiment, a diameter of each of the through holes may be about 1 μm to 50 μm.

[0113] (a2) First, a continuous through-hole adhesion layer and a through-hole seed layer are formed on the inner side walls of the plurality of through-holes by a deep-hole physical vapor deposition (PVD) process, and then a plurality of conductive pillars are formed in the plurality of through-holes by a double-sided electroplating process. The plurality of conductive pillars may include at least a first conductive pillar 31 filling the first through-hole 91 and a second conductive pillar 32 filling the second through-hole 92. Finally, the conductive material on the second surface and the first surface of the substrate 10 is removed by a chemical mechanical polishing (CMP) process, such as Figure 2B shown.

[0114] In an exemplary embodiment, the structures of the two conductive pillars may be substantially the same, and both are filling structures that penetrate the base substrate 10. On a plane parallel to the base substrate, the shape of the conductive pillar may be circular or elliptical, and on a plane perpendicular to the base substrate, the cross-sectional shape of the conductive pillar may be an hourglass shape, and the through hole is configured to accommodate the conductive pillar formed subsequently.

[0115] In an exemplary embodiment, the material of the through hole adhesion layer can be titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN), or other metals or metal nitrides with high adhesion to glass, and the thickness of the through hole adhesion layer can be about 30nm to 100nm.

[0116] In an exemplary embodiment, the material of the via seed layer may be copper (Cu), the material of each conductive pillar may be copper (Cu), and the thickness of the via seed layer may be about 30 nm to 100 nm.

[0117] (12) Forming a first structural layer. In an exemplary embodiment, forming the first structural layer may include:

[0118] (b1) A seed film is first deposited on one side of the first surface of the substrate 10 by a PVD process, and then a conductive layer is formed on the seed film by a full-surface electroplating process. Subsequently, a first conductive layer is formed on the first surface of the substrate 10 by a patterning process of coating a photoresist, exposing, developing, etching, and stripping. The first conductive layer may include at least a first connecting electrode 41 and a second connecting electrode 42 as a filter inductor wiring, wherein the first connecting electrode 41 is connected to the first conductive column 31, and the second connecting electrode 42 is connected to the second conductive column 32, as shown in FIG. Figure 3A shown.

[0119] In an exemplary embodiment, the seed layer may adopt a double-layer structure of Ti / Cu, the conductive layer may be made of Cu, the Ti layer contacts the substrate, the Cu layer contacts the conductive layer, and the Ti layer may effectively enhance the adhesion between Cu and the substrate.

[0120] In an exemplary embodiment, the thickness of the titanium layer may be about 10 nm to 200 nm, that is, the distance between the Cu layer in the first connection electrode 41 and the second connection electrode 42 and the Cu layer in the base substrate may be about 10 nm to 200 nm. For example, the thickness of the titanium layer may be about 100 nm to 150 nm. For another example, the thickness of the titanium layer may be about 133 nm.

[0121] In an exemplary embodiment, the seed layer may have a thickness of about 30 nm to 200 nm, and the conductive layer may have a thickness of more than 1 μm.

[0122] (b2) Forming a protective layer. Spin-coat a first protective film on one side of the first surface of the base substrate 10 by a spin coating process to form a protective layer 11 covering the first conductive layer. Figure 3B shown.

[0123] In an exemplary embodiment, the material of the protection layer 11 may be an insulating material such as polyimide (PI) or photoresist, and the thickness of the protection layer 11 may be about 1 μm to 10 μm.

[0124] In an exemplary embodiment, the dielectric constant of the material of the protection layer 11 may be about 3, and the dielectric loss may be about 0.001, which can effectively protect the first connection electrode 41 and prevent the connection electrode from being oxidized.

[0125] In an exemplary embodiment, the first conductive layer disposed on the first surface of the base substrate and the protective layer 11 disposed on a side of the first conductive layer away from the base substrate constitute a first structure layer.

[0126] (13) Forming a second conductive layer. In an exemplary embodiment, forming the second structural layer may include: first depositing a seed film on one side of the second surface of the base substrate 10 by a PVD process, and then forming a conductive layer on the seed film by a subtractive full-surface electroplating process. Subsequently, a second conductive layer is formed on the second surface of the base substrate 10 by a patterning process of coating a photoresist, exposing, developing, wet etching, and stripping. The second conductive layer may include at least a first electrode 51 and a third connecting electrode 43, a fourth connecting electrode 44, and a fifth connecting electrode 45 serving as a filter inductor wiring, wherein the fourth connecting electrode 44 is connected to the first conductive column 31, and the fifth connecting electrode 45 is connected to the second conductive column 32, as shown in FIG. Figure 4 shown.

[0127] In an exemplary embodiment, the seed layer may adopt a double-layer structure of Ti / Cu, the conductive layer may be made of Cu, the Ti layer contacts the substrate, the Cu layer contacts the conductive layer, and the Ti layer may effectively enhance the adhesion between Cu and the substrate.

[0128] In an exemplary embodiment, the thickness of the titanium layer may be about 10 nm to 200 nm, that is, the distance between the Cu layer in the third, fourth, and fifth connection electrodes 43 , 44 , and 45 and the Cu layer in the base substrate may be about 10 nm to 200 nm.

[0129] In an exemplary embodiment, the seed layer may have a thickness of about 30 nm to 200 nm, and the conductive layer may have a thickness of more than 1 μm.

[0130] In an exemplary embodiment, the third connection electrode 43, the fourth connection electrode 44, the first conductive pillar 31, the first connection electrode 41, the second connection electrode 42, the second conductive pillar 32 and the fifth connection electrode 45 may be sequentially connected to form a filter inductor of a three-dimensional spiral inductor structure.

[0131] In an exemplary embodiment, the first electrode plate 51 may serve as a lower electrode plate of the capacitor structure, and the first electrode plate 51 may include a stacked seed layer (Ti / Cu) and a conductive layer (Cu).

[0132] (14) Forming a surface insulating layer. In an exemplary embodiment, forming the surface insulating layer may include: depositing a surface insulating layer 12 on one side of the second surface of the substrate 10 by processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD), wherein the surface insulating layer 12 covers the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45 and the first electrode plate 51, and the surface insulating layer 12 covering the third connecting electrode 43, the fourth connecting electrode 44 and the fifth connecting electrode 45 serves as an insulating protection layer, and the surface insulating layer 12 covering the first electrode plate 51 serves as a capacitor dielectric layer of the capacitor structure, such as Figure 5 shown.

[0133] In an exemplary embodiment, the material of the surface insulating layer 12 can be silicon nitride (SiNx), silicon oxide (SiO2) or aluminum oxide (AL2O3) and the thickness of the surface insulating layer 12 (as a capacitor dielectric layer) covering the first electrode 51 area can be 100nm to 200nm.

[0134] (15) Forming a second electrode plate. In an exemplary embodiment, forming the second electrode plate may include: depositing a second electrode plate conductive film, patterning the second electrode plate conductive film through a patterning process, and forming a second electrode plate 52 on the capacitor dielectric layer 53, such as Figure 6 shown.

[0135] In an exemplary embodiment, the second electrode plate 52 may serve as an upper electrode plate of the capacitor structure, and the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 constitute a filter capacitor of the MIM structure.

[0136] In an exemplary embodiment, the second electrode 52 may have a sandwich structure of titanium layer / copper layer / titanium layer (Ti / Cu / Ti), or a sandwich structure of titanium layer / aluminum layer / titanium layer (Ti / Al / Ti), wherein the thickness of the Ti layer may be about 30 nm to 50 nm, and the thickness of the Cu layer or the Al layer may be about 200 nm to 400 nm.

[0137] In an exemplary embodiment, a second conductive layer disposed on the second surface of the base substrate, a surface insulating layer disposed on a side of the second conductive layer away from the base substrate, and a second electrode disposed on a side of the surface insulating layer away from the base substrate constitute a second structural layer.

[0138] (16) Forming a first insulating layer. In an exemplary embodiment, forming the first insulating layer may include: spin coating a first insulating film on one side of the second surface of the base substrate 10 by a spin coating process, patterning the first insulating film by a patterning process, forming a first insulating layer 61 covering the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45 and the capacitor structure, and the first insulating layer 61 is provided with a plurality of via holes, such as Figure 7 shown.

[0139] In an exemplary embodiment, the plurality of vias may include at least a first via K1, a second via K2, and a third via K3. The orthographic projection of the first via K1 on the substrate substrate may be located within the range of the orthographic projection of the third connection electrode 43 on the substrate substrate, and the first insulating film and the surface insulating layer 12 in the first via K1 are removed, exposing the surface of the third connection electrode 43. The orthographic projection of the second via K2 on the substrate substrate may be located within the range of the orthographic projection of the first electrode plate 51 on the substrate substrate, and the first insulating film and the surface insulating layer 12 in the second via K2 are removed, exposing the surface of the first electrode plate 51. The orthographic projection of the third via K3 on the substrate substrate may be located within the range of the orthographic projection of the second electrode plate 52 on the substrate substrate, and the first insulating film in the third via K3 is removed, exposing the surface of the second electrode plate 52.

[0140] In an exemplary embodiment, the material of the first insulating layer 61 may be an insulating material such as polyimide, and the thickness of the first insulating layer 61 may be about 1 μm to 10 μm.

[0141] (17) Forming a lead layer. In an exemplary embodiment, forming the lead layer may include: first depositing a lead adhesion film and a lead seed film in sequence on the first insulating layer 61 through a PVD process, and patterning the lead adhesion film and the lead seed film through a patterning process. Subsequently, electroplating a lead material on the lead seed film through an additive plating process, and forming a lead layer on the first insulating layer 61 through a wet etching process. The lead layer may include at least a first lead 71, a second lead 72, and a third lead 73, wherein the first lead 71 is connected to the third connection electrode 43 through a first via K1, the second lead 72 is connected to the first electrode plate 51 through a second via K2, and the third lead 73 is connected to the second electrode plate 52 through a third via K3, as shown in FIG. Figure 8 shown.

[0142] In an exemplary embodiment, the material of the wire adhesion layer may adopt Ti, the material of the wire seed layer may adopt Cu, and the material of the wire material may adopt Cu.

[0143] In an exemplary embodiment, the thickness of the first lead 71 , the second lead 72 , and the third lead 73 may be about 1 μm to 10 μm.

[0144] (18) Forming a second insulating layer. In an exemplary embodiment, forming the second insulating layer may include: spin coating a second insulating film on one side of the second surface of the base substrate 10 by a spin coating process, patterning the second insulating film by a patterning process, forming a second insulating layer 62 covering the first lead 71, the second lead 72, and the third lead 73, and the second insulating layer 62 is provided with a plurality of via holes, such as Fig. 9 shown.

[0145] In an exemplary embodiment, the plurality of vias may include at least a fourth via K4, a fifth via K5, and a sixth via K6. The orthographic projection of the fourth via K4 on the substrate substrate may be located within the range of the orthographic projection of the first lead 71 on the substrate substrate, and the second insulating film in the fourth via K4 is removed, exposing the surface of the first lead 71. The orthographic projection of the fifth via K5 on the substrate substrate may be located within the range of the orthographic projection of the second lead 72 on the substrate substrate, and the second insulating film in the fifth via K5 is removed, exposing the surface of the second lead 72. The orthographic projection of the sixth via K6 on the substrate substrate may be located within the range of the orthographic projection of the third lead 73 on the substrate substrate, and the second insulating film in the sixth via K6 is removed, exposing the surface of the third lead 73.

[0146] In an exemplary embodiment, the second insulating layer 62 may be made of an insulating material such as polyimide, and the thickness of the second insulating layer 62 may be approximately 1 μm to 10 μm.

[0147] (19) Forming a pad layer. In an exemplary embodiment, forming the pad layer may include: first depositing a pad adhesion film and a pad seed film in sequence on the second insulating layer 62 through a PVD process, and patterning the pad adhesion film and the pad seed film through a patterning process. Subsequently, electroplating a pad material on the pad seed film through an electroplating process, and forming a pad layer on the second insulating layer 62 through an etching and thermal annealing (Reflow) process. The pad layer may include at least a first pad 81, a second pad 82, and a third pad 83, wherein the first pad 81 is connected to the first lead 71 through a fourth via K4, the second pad 82 is connected to the second lead 72 through a fifth via K5, and the third pad 83 is connected to the third lead 73 through a sixth via K6, as shown in FIG. Figure 1 shown.

[0148] In an exemplary embodiment, on a plane parallel to the substrate, the cross-sectional shape of the first pad 81, the second pad 82 and the third pad 83 may be circular, elliptical, rectangular or polygonal, etc., and on a plane perpendicular to the substrate, the cross-sectional shape of the first pad 81, the second pad 82 and the third pad 83 may be semicircular, semi-elliptical or trapezoidal, etc. The first pad 81, the second pad 82 and the third pad 83 may be referred to as bumps.

[0149] In an exemplary embodiment, the material of the pad adhesion film can be Ti, the material of the pad seed film can be Cu, the pad layer can be a Cu / Ni / SnAg laminated structure, or a Cu / Ni / Sn laminated structure, the Ni layer can be about 30nm to 100nm thick, the Cu layer can be about 200nm to 600nm thick, and the tin-silver alloy (SnAg) layer or the tin (Sn) layer can be about 200nm to 500nm thick, which not only has good stretchability, but also has anti-corrosion performance. The present disclosure can effectively prevent Sn from penetrating into Cu by setting the Ni layer as a barrier layer.

[0150] At this point, the filter of this embodiment is prepared. In an exemplary embodiment, the filter of this embodiment may include: a substrate substrate, a first structural layer arranged on one side of the first surface of the substrate substrate, and a second structural layer arranged on one side of the second surface of the substrate substrate. The first structural layer may include: a first connecting electrode and a second connecting electrode arranged on one side of the first surface of the substrate substrate, and a protective layer covering the first connecting electrode and the second connecting electrode. The second structural layer may include: a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode and a capacitor structure arranged on one side of the second surface of the substrate substrate. The filter also includes a first insulating layer covering the third connecting electrode, the fourth connecting electrode, the fifth connecting electrode and the capacitor structure, a first lead, a second lead and a third lead arranged on the first insulating layer, a second insulating layer covering the first lead, the second lead and the third lead, and a first pad, a second pad and a third pad arranged on the second insulating layer.

[0151] In a filter, the first insulating layer and the second insulating layer are made of inorganic materials. Since the thickness of the first insulating layer and the second insulating layer is relatively thin, less than 300nm, on the one hand, it will cause a large parasitic capacitance to be formed between each conductive layer, which seriously affects the filter performance, and on the other hand, it will cause poor drilling and cause unstable device performance. Since the thickness of the first insulating layer and the second insulating layer is relatively thin, the coverage of the edge position of the connecting electrode is not ideal, and even cracks will appear. In the subsequent wet etching process, the etching liquid will etch the connecting electrode at the crack, resulting in poor drilling. The first insulating layer and the second insulating layer of the filter disclosed in the present invention are made of thicker organic materials, which can not only effectively reduce the parasitic capacitance between each conductive layer, but also effectively avoid poor drilling, thereby ensuring the performance stability and reliability of the filter and improving the performance of the filter.

[0152] The disclosed filter adopts a glass substrate, which can not only reduce the filter loss, but also reduce the production cost. The disclosed filter realizes the glass core TGV 3D spiral inductor through TGV technology, effectively improving the inductance and Q value per unit area, making the filter structure more compact, reducing the filter size, and making the filter easier to integrate.

[0153] The filter disclosed herein uses a seed layer including a titanium layer and a copper layer. The titanium layer is in contact with the base substrate. The thickness of the titanium layer is 10nm to 200nm, which can not only effectively enhance the adhesion between the connecting electrode and the base substrate, but also ensure seamless overlap between the connecting electrode and the conductive column.

[0154] The preparation process disclosed in the present invention can be realized by using existing mature preparation equipment, with little improvement on the existing process, and can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0155] Fig.10 FIG. 1 is a schematic diagram of another filter structure of an exemplary embodiment of the present disclosure. Fig.10 As shown, the main structure of the filter of the exemplary embodiment of the present disclosure may include a substrate substrate 10, a first structure layer 100 arranged on one side of the first surface of the substrate substrate 10, and a second structure layer 200 arranged on one side of the second surface of the substrate substrate 10. The main structure of the substrate substrate 10 and the first structure layer 100 of this embodiment is basically the same as that of the aforementioned embodiment.

[0156] In an exemplary embodiment, the second structure layer 200 may include at least a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, and a capacitor structure disposed on the second surface of the base substrate 10, the fourth connection electrode 44 is connected to the first conductive pillar 31, and the fifth connection electrode 45 is connected to the second conductive pillar 32. The capacitor structure may include a first electrode plate 51 disposed on the second surface of the base substrate 10, a capacitor dielectric layer 53 disposed on a side of the first electrode plate 51 away from the base substrate, and a second electrode plate 52 disposed on a side of the capacitor dielectric layer 53 away from the base substrate.

[0157] In an exemplary embodiment, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, the fourth connection electrode 44 and the fifth connection electrode 45 are configured as a filter inductor coil routing to form a filter inductor of a three-dimensional spiral inductor structure. The first electrode plate 51 can be used as a lower electrode plate of the capacitor structure, and the second electrode plate 52 can be used as an upper electrode plate of the capacitor structure. The first electrode plate 51, the capacitor dielectric layer 53 and the second electrode plate 52 constitute a filter capacitor of the MIM structure.

[0158] In an exemplary embodiment, the third connection electrode 43 , the fourth connection electrode 44 , the fifth connection electrode 45 and the first electrode plate 51 may be disposed in the same layer and simultaneously formed by the same damascene process.

[0159] In an exemplary embodiment, the filter may also include a first insulating layer 61 arranged on the side of the second structural layer 200 away from the substrate, a lead layer arranged on the side of the first insulating layer 61 away from the substrate, a second insulating layer 62 arranged on the side of the lead layer away from the substrate, and a pad layer arranged on the side of the second insulating layer 62 away from the substrate, and the main structure of the first insulating layer 61, the lead layer, the second insulating layer 62 and the pad layer are basically the same as those in the aforementioned embodiments.

[0160] In an exemplary embodiment, the first connection electrode 41 and the second connection electrode 42 may include a stacked seed layer and a conductive layer, wherein the seed layer is disposed on the first surface of the base substrate, and the conductive layer is disposed on a side of the seed layer away from the base substrate, and the thickness of the conductive layer may be greater than 1 μm.

[0161] In an exemplary embodiment, the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45 and the first electrode 51 may all include a stacked seed layer, a conductive layer and a conductive protective layer, the seed layer is arranged on the second surface of the substrate, the conductive layer is arranged on the side of the seed layer away from the substrate, the conductive protective layer is arranged on the side of the conductive layer away from the substrate, and the conductive protective layer is configured to prevent the conductive layer from diffusing into the capacitor dielectric layer and increase the adhesion between the conductive layer and the capacitor dielectric layer.

[0162] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, the thickness of the titanium layer is 10 nm to 200 nm, and the material of the conductive protection layer includes titanium.

[0163] In an exemplary embodiment, the second electrode plate 52 may have a sandwich laminate structure of Ti / Cu / Ti or a sandwich laminate structure of Ti / Al / Ti.

[0164] Fig.11 FIG. 1 is a schematic cross-sectional view of a capacitor structure of an exemplary embodiment of the present disclosure. Fig.11 As shown, the capacitor dielectric layer 53 and the second electrode 52 are both patterned by a dry etching process, and the orthographic projection of the second electrode 52 on the substrate can be located within the range of the orthographic projection of the capacitor dielectric layer 53 on the substrate, and the orthographic projection of the capacitor dielectric layer 53 on the substrate can be located within the range of the orthographic projection of the first electrode 51 on the substrate.

[0165] In an exemplary embodiment, along a direction away from the substrate, the areas of the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 decrease in sequence.

[0166] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, there is a first distance d1 between the edge of the first electrode 51 and the edge of the capacitor dielectric layer 53 , and the first distance d1 may be greater than or equal to 50 nm.

[0167] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, a second distance d2 is provided between an edge of the capacitor dielectric layer 53 and an edge of the second electrode plate 52 . The second distance d2 may be greater than or equal to 50 nm.

[0168] In an exemplary embodiment, the preparation process of the filter of this embodiment may include the following steps.

[0169] (21) Forming a metallized TGV substrate, the manufacturing process and the formed structure are basically the same as step (11) of the aforementioned embodiment.

[0170] (22) Forming a first structure layer and a second conductive layer. In an exemplary embodiment, forming the first structure layer and the second conductive layer may include:

[0171] (b1) A first photoresist layer is spin-coated on one side of the first surface of the substrate substrate 10 by a spin coating process, and a second photoresist layer is spin-coated on one side of the second surface of the substrate substrate 10. A first wiring pattern is formed on the first photoresist layer by a patterning process of exposure and development, and a second wiring pattern is formed on the second photoresist layer. The first photoresist layer at the location of the first wiring pattern is removed to expose the first surface of the substrate substrate 10, and the second photoresist layer at the location of the second wiring pattern is removed to expose the second surface of the substrate substrate 10, as shown in FIG. Fig. 12A shown.

[0172] In an exemplary embodiment, the material of the first photoresist layer and the second photoresist layer may be polyimide, and the thickness of the first photoresist layer and the second photoresist layer may be about 1 μm to 10 μm.

[0173] (b2) First, a seed film is deposited on one side of the first surface and one side of the second surface of the substrate 10 by a PVD process. The seed film at the location of the first wiring pattern is arranged on the first surface of the substrate 10, and the seed film in the area outside the first wiring pattern is arranged on the first photoresist layer. The seed film at the location of the second wiring pattern is arranged on the second surface of the substrate 10, and the seed film in the area outside the second wiring pattern is arranged on the second photoresist layer. Subsequently, a conductive layer is formed on the seed film on one side of the first surface and one side of the second surface of the substrate 10 by an additive electroplating process, and the conductive layer is higher than the photoresist layer. On the first surface side of the substrate 10, the distance between the surface of the conductive layer away from the substrate and the first surface is greater than the distance between the surface of the first photoresist layer away from the substrate and the first surface. On the second surface side of the substrate 10, the distance between the surface of the conductive layer away from the substrate and the second surface is greater than the distance between the surface of the second photoresist layer away from the substrate and the second surface. Fig. 12B shown.

[0174] In an exemplary embodiment, the seed layer can adopt a double-layer structure of Ti / Cu, the material of the conductive layer can be Cu, the Ti layer is in contact with the substrate, the thickness of the titanium layer is 10nm to 200nm, the Cu layer is in contact with the conductive layer, and the Ti layer can effectively enhance the adhesion between Cu and the substrate.

[0175] In exemplary embodiments, the seed layer may have a thickness of about 30 nm to 200 nm.

[0176] (b3) Using a CMP process, the first photoresist layer and the second photoresist layer are used as cut-off layers to remove all the conductive layers and seed films on the first photoresist layer and the second photoresist layer, respectively, to form a first conductive layer on the first surface of the substrate 10, and a transition conductive layer on the second surface of the substrate 10. The first conductive layer may include at least a first connecting electrode 41 and a second connecting electrode 42, wherein the first connecting electrode 41 is connected to the first conductive pillar 31, and the second connecting electrode 42 is connected to the second conductive pillar 32, as shown in FIG. Fig. 12C shown.

[0177] In an exemplary embodiment, the first connection electrode 41 and the second connection electrode 42 may include a stacked seed layer (Ti / Cu) and a conductive layer (Cu), and the thickness of the conductive layer may be greater than 1 μm.

[0178] (b4) Forming a protective layer. Spin-coat a first protective film on one side of the first surface of the base substrate 10 by a spin coating process to form a protective layer 11 covering the first conductive layer. Fig.12D shown.

[0179] In an exemplary embodiment, the material of the protection layer 11 may be an insulating material such as polyimide (PI) or photoresist, and the thickness of the protection layer 11 may be about 1 μm to 10 μm.

[0180] In an exemplary embodiment, the dielectric constant of the material of the protection layer 11 may be about 3, and the dielectric loss may be about 0.001, which can effectively protect the first connection electrode 41 and prevent the connection electrode from being oxidized.

[0181] In an exemplary embodiment, the first conductive layer disposed on the first surface of the base substrate and the protective layer 11 disposed on a side of the first conductive layer away from the base substrate constitute a first structure layer.

[0182] (b5) forming a second conductive layer. A protective conductive film is deposited on one side of the second surface of the base substrate 10 by a PVD process, and the protective conductive film is patterned by a patterning process to form a conductive protective layer on the transition conductive layer. The conductive protective layer and the transition conductive layer together constitute a second conductive layer. The second conductive layer may include at least a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45 and a first electrode plate 51. The fourth connecting electrode 44 is connected to the first conductive column 31, and the fifth connecting electrode 45 is connected to the second conductive column 32. Fig.12E shown.

[0183] In an exemplary embodiment, the material of the conductive protection layer can be Ti, and the thickness of the conductive protection layer can be about 30nm to 100nm. In an exemplary embodiment, the conductive protection layer can prevent the conductive layer (Cu) from diffusing to the subsequently formed capacitor dielectric layer on the one hand, and increase the adhesion between the conductive layer (Cu) and the subsequently formed capacitor dielectric layer on the other hand.

[0184] In an exemplary embodiment, the third connecting electrode 43, the fourth connecting electrode 44 and the fifth connecting electrode 45 are configured as filter inductor wiring, and may each include a stacked seed layer (Ti / Cu), a conductive layer (Cu) and a conductive protection layer (Ti), and the thickness of the conductive layer may be greater than 1 μm.

[0185] In an exemplary embodiment, the first electrode plate 51 may serve as a lower electrode plate of the capacitor structure. The first electrode plate 51 may include a stacked seed layer (Ti / Cu), a conductive layer (Cu) and a conductive protection layer (Ti). The thickness of the conductive layer may be greater than 1 μm.

[0186] In an exemplary embodiment, the first electrode plate 51 may be directly connected to the fifth connection electrode 45 or connected through a connection electrode.

[0187] In an exemplary embodiment, since the transition conductive layer in the second conductive layer is formed by a CMP process, the first electrode 51 formed in the present disclosure has good thickness uniformity, surface flatness and surface smoothness, which is beneficial to improving the uniformity of the subsequently formed capacitor dielectric layer and the uniformity of the capacitor structure.

[0188] (23) Forming a capacitor dielectric layer. In an exemplary embodiment, forming the capacitor dielectric layer may include: depositing a capacitor dielectric film on one side of the second surface of the substrate 10 by a process such as CVD, PECVD, LPCVD, or ALD, patterning the capacitor dielectric film by a patterning process, and forming a capacitor dielectric layer 53 on the first electrode 51, such as Fig.13 shown.

[0189] In an exemplary embodiment, the capacitor dielectric layer 53 may be patterned by dry etching, and the orthographic projection of the capacitor dielectric layer 53 on the substrate may be within the range of the orthographic projection of the first electrode plate 51 on the substrate.

[0190] In an exemplary embodiment, the material of the capacitor dielectric layer 53 may be silicon nitride (SiNx), silicon oxide (SiO2) or aluminum oxide (Al2O3), and the thickness of the capacitor dielectric layer 53 may be 100nm to 200nm. Since the first electrode 51 has good thickness uniformity and surface smoothness, the capacitor dielectric layer of the present disclosure has good thickness uniformity, which effectively improves the capacitance uniformity of the capacitor structure.

[0191] (24) Forming a second electrode plate. In an exemplary embodiment, forming the second electrode plate may include: depositing a second electrode plate conductive film on one side of the second surface of the substrate 10 by a PVD process, patterning the second electrode plate conductive film by a patterning process, and forming a second electrode plate 52 on the capacitor dielectric layer 53, such as Fig.14 shown.

[0192] In an exemplary embodiment, the second electrode plate 52 may be patterned by using a dry etching process, and the orthographic projection of the second electrode plate 52 on the substrate may be located within the range of the orthographic projection of the capacitor dielectric layer 53 on the substrate.

[0193] In an exemplary embodiment, the second electrode plate 52 may serve as an upper electrode plate of the capacitor structure, and the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 constitute a filter capacitor of the MIM structure.

[0194] In an exemplary embodiment, the second electrode 52 may have a sandwich structure of Ti / Cu / Ti or a sandwich structure of Ti / Al / Ti, wherein the thickness of the Ti layer may be about 30 nm to 50 nm, and the thickness of the Cu layer or the Al layer may be about 200 nm to 400 nm.

[0195] In an exemplary embodiment, a second conductive layer disposed on the second surface of the substrate, a capacitor dielectric layer disposed on a side of the second conductive layer away from the substrate, and a second electrode disposed on a side of the capacitor dielectric layer away from the substrate constitute a second structural layer.

[0196] Fig.15 FIG. 1 is a schematic diagram of a planar structure of a capacitor structure of an exemplary embodiment of the present disclosure. Fig.15 As shown, the capacitor structure of the MIM structure may include a first electrode 51, a capacitor dielectric layer 53 and a second electrode 52, the capacitor dielectric layer 53 is arranged on the side of the first electrode 51 away from the substrate, the capacitor dielectric layer 53 is arranged on the side of the capacitor dielectric layer 53 away from the substrate, and the first electrode 51, the capacitor dielectric layer 53 and the second electrode 52 are rectangular in shape.

[0197] In an exemplary embodiment, along a direction away from the base substrate 10 , the areas of the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 decrease in sequence.

[0198] In an exemplary embodiment, the capacitor dielectric layer 53 and the second electrode plate 52 are both patterned by a dry etching process with high etching accuracy, which not only effectively improves the dimensional accuracy and capacitance uniformity of the capacitor structure, but also ensures the dimensional accuracy of the capacitor dielectric layer 53 and the second electrode plate 52. In addition, by arranging the areas of the first electrode plate 51, the capacitor dielectric layer 53 and the second electrode plate 52 to decrease successively, the orthographic projection of the second electrode plate 52 on the substrate can be located within the range of the orthographic projection of the capacitor dielectric layer 53 on the substrate, and the orthographic projection of the capacitor dielectric layer 53 on the substrate can be located within the range of the orthographic projection of the first electrode plate 51 on the substrate, which further ensures the dimensional accuracy, can effectively ensure the effective area of ​​the electrode plate, and improves the performance consistency of the device.

[0199] In an exemplary embodiment, on a plane parallel to the base substrate 10, in at least one direction, there is a first distance d1 between the edge of the first electrode 51 and the edge of the capacitor dielectric layer 53, and there is a second distance d2 between the edge of the capacitor dielectric layer 53 and the edge of the second electrode 52. The first distance d1 may be greater than or equal to 50 nm, and the second distance d2 may be greater than or equal to 50 nm.

[0200] The present disclosure effectively ensures the processing accuracy of the capacitor structure and the effective area of ​​the capacitor structure by setting the stacking relationship of the first electrode plate, the capacitor dielectric layer and the second electrode plate, thereby improving the consistency of the filter performance.

[0201] (25)-(28) sequentially form a first insulating layer, a lead layer, a second insulating layer and a pad layer, and the manufacturing process and the formed structure are substantially the same as steps (15)-(18) of the aforementioned embodiment, such as Fig.10 shown.

[0202] In a capacitor structure of a filter, the lower plate is made by subtractive electroplating, and the upper plate is formed by a wet etching process. Due to the uneven and rough surface of the lower plate, the thickness of the capacitor dielectric layer is uneven, resulting in problems such as uneven capacitance in the capacitor structure. Due to the low precision of wet etching, the size deviation of the capacitor structure is large, resulting in problems such as low performance consistency in the filter. In the filter provided by the embodiment of the present disclosure, the first plate of the capacitor structure is prepared by a Damascus process including additive electroplating and CMP, and the first plate has good thickness uniformity, surface flatness and surface smoothness, so that the capacitor dielectric layer has good thickness uniformity, effectively improving the capacitance uniformity of the capacitor structure. The capacitor dielectric layer and the second plate of the capacitor structure of the present disclosure are prepared by a dry etching process with high etching precision, which not only effectively improves the dimensional accuracy and dimensional uniformity of the capacitor structure, but also effectively ensures the effective area of ​​the plate by setting the areas of the first plate, the capacitor dielectric layer and the second plate to be reduced in sequence, further improving the processing accuracy of the capacitor structure, ensuring the dimensional accuracy and dimensional uniformity, improving the consistency of the filter performance, and improving the product yield and product quality.

[0203] The present disclosure can ensure seamless overlap between the connecting electrode and the conductive column through optimized additive electroplating and CMP processes, reduce process steps, and effectively improve the working reliability and performance stability of the filter.

[0204] In a capacitor structure of a filter, the lower plate adopts a Ti / Cu laminated structure. Since Cu is in direct contact with the capacitor dielectric layer (SiNx), not only will Cu ions diffuse into SiNx, but the adhesion between the two is small, and peeling is prone to occur, resulting in abnormal filter characteristics or even failure. The first plate of the capacitor structure disclosed in the present invention adopts a Ti / Cu / Ti laminated structure, and the Ti layer is in contact with SiNx, which can not only prevent Cu ions from diffusing into SiNx, but also avoid peeling, effectively improving the reliability and stability of the filter.

[0205] The first insulating layer and the second insulating layer of the capacitor structure of the disclosed embodiment are made of organic materials, and the thickness is about 1 μm to 10 μm, which can not only effectively reduce the parasitic capacitance between the conductive layers, but also effectively avoid poor drilling and corrosion, ensure the performance stability and reliability of the filter, and improve the performance of the filter. The disclosed filter uses TGV technology to realize the glass core TGV 3D spiral inductor, effectively improving the inductance and Q value per unit area, making the filter structure more compact, reducing the filter size, and making the filter easier to integrate.

[0206] Fig.16 FIG. 1 is a schematic diagram of the structure of another filter of the exemplary embodiment of the present disclosure. Fig.10The embodiments shown are basically the same, except that the cross-sectional shape of the conductive pillar embedded in the substrate of this embodiment is a pillar shape or a cone shape. Fig.16 As shown, the main structure of the filter of the exemplary embodiment of the present disclosure may include a substrate 10, a first structure layer 100 and a second structure layer 200. The first structure layer 100 may be arranged on one side of the first surface of the substrate 10, and the second structure layer 200 may be arranged on one side of the second surface of the substrate 10. In the exemplary embodiment, the structures of the first structure layer 100 and the second structure layer 200 are similar to Fig.10 The embodiments shown are basically the same and will not be described in detail here.

[0207] In an exemplary embodiment, a plurality of conductive pillars are embedded in the base substrate 10, and the plurality of conductive pillars may include at least a first conductive pillar 31 and a second conductive pillar 32, and the structures of the two conductive pillars may be substantially the same. On a plane parallel to the base substrate, the shape of the conductive pillar may be circular or elliptical, and on a plane perpendicular to the base substrate, the cross-sectional shape of the conductive pillar may be a column shape or a cone shape.

[0208] In an exemplary embodiment, the base substrate 10 is obtained by first forming a metallized blind hole base substrate and then performing a thinning process.

[0209] In an exemplary embodiment, the preparation process of the filter of this embodiment may include the following steps.

[0210] (31) Forming a metallized blind via glass (BGV) substrate. In an exemplary embodiment, forming a metallized BGV substrate may include:

[0211] (a1) providing a substrate 10, and forming a plurality of blind holes on the substrate by laser induced etching, sandblasting, laser ablation or other processes, wherein the plurality of blind holes may include at least a first blind hole 93 and a second blind hole 94, such as Fig.17A shown.

[0212] In an exemplary embodiment, the structures of the two blind holes may be substantially the same, and both are blind hole structures that do not penetrate the base substrate 10. On a plane parallel to the base substrate, the shape of the blind hole may be circular or elliptical, and on a plane perpendicular to the base substrate, the cross-sectional shape of the blind hole may be a column shape or a cone shape, etc. The blind hole is configured to accommodate a conductive column formed subsequently.

[0213] In an exemplary embodiment, the cross-sectional shape of the blind hole may be a cone shape, and the cone angle is less than or equal to 5°.

[0214] In an exemplary embodiment, two blind holes may be disposed on the second surface of the base substrate 10 , and no blind holes are disposed on the first surface of the base substrate 10 .

[0215] In an exemplary embodiment, the material of the base substrate may adopt alkali-free glass, quartz glass, etc., and the thickness of the base substrate may be about 0.7 mm to 1.0 mm.

[0216] In an exemplary embodiment, the diameter of each blind hole may be about 1 μm to 50 μm.

[0217] (a2) First, a continuous blind hole adhesion layer and a blind hole seed layer are formed on the inner side walls of the plurality of blind holes by a PVD process, and then a plurality of conductive pillars are formed in the plurality of blind holes by an electroplating process. The plurality of conductive pillars may include at least a first conductive pillar 31 filling the first blind hole 93 and a second conductive pillar 32 filling the second blind hole 94. Finally, the conductive material on the second surface of the substrate 10 is removed by a CMP process, such as Fig. 17B shown.

[0218] In an exemplary embodiment, materials of the blind via adhesion layer, the blind via seed layer, and the conductive pillars, etc., are substantially the same as those of the aforementioned embodiment.

[0219] (32) Forming a second conductive layer. In an exemplary embodiment, forming the second conductive layer may include:

[0220] (b1) Spin-coat a photoresist layer on one side of the second surface of the substrate 10 by a spin coating process. A wiring pattern is formed on the photoresist layer by a patterning process of exposure and development, and the photoresist layer at the location of the wiring pattern is removed to expose the second surface of the substrate 10, such as Fig.18A shown.

[0221] (b2) First, a seed film is deposited on one side of the second surface of the substrate 10 by a PVD process. The seed film at the location of the wiring pattern is set on the second surface of the substrate 10, and the seed film in the area outside the wiring pattern is set on the photoresist layer. Subsequently, a conductive layer is formed on the seed film on the second surface of the substrate 10 by an additive electroplating process. The conductive layer is higher than the photoresist layer, that is, the distance between the surface of the conductive layer away from the substrate and the second surface is greater than the distance between the surface of the photoresist layer away from the substrate and the second surface, such as Fig.18B shown.

[0222] In an exemplary embodiment, the seed layer may adopt a double-layer structure of Ti / Cu, the conductive layer may be made of Cu, the Ti layer contacts the substrate, the Cu layer contacts the conductive layer, and the Ti layer may effectively enhance the adhesion between Cu and the substrate.

[0223] (b3) Using the CMP process, the photoresist layer is used as a cut-off layer to completely remove the conductive layer and the seed film on the photoresist layer, and a transition conductive layer is formed on the second surface of the substrate 10, such as Fig.18C shown.

[0224] (b4) forming a second conductive layer. A protective conductive film is deposited on one side of the second surface of the base substrate 10 by a PVD process, and the protective conductive film is patterned by a patterning process to form a conductive protective layer on the transition conductive layer. The conductive protective layer and the transition conductive layer together constitute a second conductive layer. The second conductive layer may include at least a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45 and a first electrode plate 51. The second connecting electrode 42 is connected to the second conductive column 32 and the third conductive column 33 at the same time. The third connecting electrode 43 is connected to the first conductive column 31. Fig.18D shown.

[0225] In an exemplary embodiment, the material of the conductive protection layer can be Ti, and the thickness of the conductive protection layer can be about 30nm to 100nm. In an exemplary embodiment, the conductive protection layer can prevent the conductive layer (Cu) from diffusing to the subsequently formed capacitor dielectric layer on the one hand, and increase the adhesion between the conductive layer (Cu) and the subsequently formed capacitor dielectric layer on the other hand.

[0226] In an exemplary embodiment, the third connection electrode 43 , the fourth connection electrode 44 , and the fifth connection electrode 45 may each include a stacked seed layer (Ti / Cu), a conductive layer (Cu), and a conductive protection layer (Ti), and the thickness of the conductive layer may be greater than 1 μm.

[0227] In an exemplary embodiment, the first electrode plate 51 may serve as a lower electrode plate of the capacitor structure, and the first electrode plate 51 may include a stacked seed layer (Ti / Cu), a conductive layer (Cu), and a conductive protection layer (Ti).

[0228] In an exemplary embodiment, since the transition conductive layer in the second conductive layer is formed by a CMP process, the first electrode 51 formed in the present disclosure has good thickness uniformity, surface flatness and surface smoothness, which is beneficial to improving the uniformity of the subsequently formed capacitor dielectric layer and the uniformity of the capacitor structure.

[0229] (33) Forming a capacitor dielectric layer. In an exemplary embodiment, the structure and process of forming the capacitor dielectric layer 53 are similar to Fig.10 The embodiments shown may be substantially the same, such as Fig.19 shown.

[0230] In the exemplary embodiment, since the first electrode plate 51 has good thickness uniformity and surface smoothness, the capacitor dielectric layer of the present disclosure has good thickness uniformity, which effectively improves the capacitance uniformity of the capacitor structure.

[0231] (34) Forming the second electrode plate. In an exemplary embodiment, the structure and process of forming the second electrode plate 52 are similar to those of Fig.10 The embodiments shown may be substantially the same, such as Fig. 20 shown.

[0232] In an exemplary embodiment, the capacitor dielectric layer 53 and the second plate 52 are both patterned by a dry etching process, and the orthographic projection of the second plate 52 on the substrate substrate can be located within the range of the orthographic projection of the capacitor dielectric layer 53 on the substrate substrate, and the orthographic projection of the capacitor dielectric layer 53 on the substrate substrate can be located within the range of the orthographic projection of the first plate 51 on the substrate substrate. The second plate 52 can serve as the upper plate of the capacitor structure, and the first plate 51, the capacitor dielectric layer 53 and the second plate 52 constitute a filter capacitor of the MIM structure.

[0233] In an exemplary embodiment, the areas of the first electrode 51, the capacitor dielectric layer 53, and the second electrode 52 decrease successively. In at least one direction, there is a first distance between the edge of the first electrode 51 and the edge of the capacitor dielectric layer 53, and there is a second distance between the edge of the capacitor dielectric layer 53 and the edge of the second electrode 52. The first distance can be greater than or equal to 50nm, and the second distance can be greater than or equal to 50nm.

[0234] (35)-(38) sequentially form a first insulating layer, a lead layer, a second insulating layer and a pad layer, and the manufacturing process and the formed structure are substantially the same as steps (15)-(18) of the aforementioned embodiment, such as Fig.21 shown.

[0235] (39) Forming a first structural layer. In an exemplary embodiment, forming the first structural layer may include:

[0236] (c1) Turning over the base substrate 10, and thinning the first surface of the base substrate 10 until two conductive pillars are exposed on the first surface, such as Fig.22A shown.

[0237] (c2) A photoresist layer is spin-coated on one side of the first surface of the substrate substrate 10 by a spin coating process, and a wiring pattern is formed on the photoresist layer by a patterning process of exposure and development. The photoresist layer at the location of the wiring pattern is removed to expose the first surface of the substrate substrate 10. A seed film is first deposited on one side of the first surface of the substrate substrate 10 by a PVD process. The seed film at the location of the wiring pattern is set on the first surface of the substrate substrate 10, and the seed film in the area outside the wiring pattern is set on the photoresist layer. Subsequently, a conductive layer is formed on the seed film on one side of the first surface of the substrate substrate 10 by an additive electroplating process, and the conductive layer is higher than the photoresist layer. By a CMP process, the photoresist layer is used as a cutoff layer, and the conductive layer and the seed film on the photoresist layer are completely removed to form a first conductive layer on the first surface of the substrate substrate 10. The first conductive layer may include at least a first connecting electrode 41, and the first connecting electrode 41 is simultaneously connected to the first conductive column 31 and the second conductive column 32, such as Fig. 22B shown.

[0238] (c3) Forming a protective layer. Spin-coat a first protective film on one side of the first surface of the base substrate 10 by a spin coating process to form a protective layer 11 covering the first conductive layer. Fig.16 shown.

[0239] At this point, the filter of this embodiment is completed. The main structure of the filter of this embodiment is basically the same as that of the previous embodiment. The difference is that the cross-sectional shape of the conductive column in the substrate of this embodiment is a column shape or a cone shape.

[0240] The filter of this embodiment not only has the advantages of the aforementioned embodiments, but also, compared with the hourglass-shaped holes in the substrate substrate of the aforementioned embodiments, the columnar holes or conical holes of this embodiment can effectively reduce the stress accumulation in the holes, and can effectively control the warping and fragmentation caused by stress, thereby reducing the process difficulty, improving the yield, and maximizing the consistency of the overall performance of the filter.

[0241] Fig.23 FIG. 1 is a schematic diagram of the structure of another filter of the exemplary embodiment of the present disclosure. Fig.10 The embodiments shown are basically the same, except that the first electrode plate of the capacitor structure in this embodiment is prepared using a patterning process. Fig.23 As shown, the main structure of the filter of the exemplary embodiment of the present disclosure may include a base substrate 10, a first structure layer 100 and a second structure layer 200. The first structure layer 100 may be arranged on one side of the first surface of the base substrate 10, and the second structure layer 200 may be arranged on one side of the second surface of the base substrate 10. In the exemplary embodiment, the structure of the connecting electrodes in the base substrate 10, the first structure layer 100 and the second structure layer 200 is similar to Fig.10The embodiments shown are basically the same and will not be described in detail here.

[0242] In an exemplary embodiment, the capacitor structure in the second structure layer 200 may include a first electrode 51 arranged on the second surface of the base substrate 10, a capacitor dielectric layer 53 arranged on the side of the first electrode 51 away from the base substrate, and a second electrode 52 arranged on the side of the capacitor dielectric layer 53 away from the base substrate. The first electrode 51 can be prepared by a patterning process.

[0243] In an exemplary embodiment, the first electrode plate 51 has a thickness of h1, and the third connection electrode 43, the fourth connection electrode 44, and the fifth connection electrode 45 have a thickness of h2, and h1 is smaller than h2.

[0244] In an exemplary embodiment, the first electrode 51 may include a stacked seed layer, a conductive layer and a conductive protective layer, the seed layer may include a titanium layer, the thickness of the titanium layer is 10nm to 200nm, the material of the conductive layer may include aluminum, and the material of the conductive protective layer may include titanium, forming a sandwich stacked structure of Ti / Al / Ti.

[0245] In an exemplary embodiment, the thickness of the aluminum layer may be less than 1 μm. For example, the thickness of the aluminum layer may be about 0.5 μm to 0.9 μm.

[0246] In an exemplary embodiment, the material of the capacitor dielectric layer 53 may be silicon nitride (SiNx), and the thickness of the capacitor dielectric layer 53 may be 100 nm to 200 nm.

[0247] In an exemplary embodiment, the material of the second electrode plate 52 includes Al, and the thickness of the second electrode plate 52 may be greater than or equal to 400 nm. Alternatively, the second electrode plate 52 may have a sandwich structure of Ti / Al / Ti.

[0248] In an exemplary embodiment, the connection electrode and the first electrode 51 in the second structure layer are formed respectively by different patterning processes. The first electrode 51 formed by the patterning process may include: after forming the third connection electrode 43, the fourth connection electrode 44 and the fifth connection electrode 45 of the second structure layer 200, a Ti layer, an Al layer and a Ti layer are sequentially deposited on one side of the second surface of the substrate 10 by a PVD process, a photoresist is applied, the photoresist is exposed and developed, the first electrode 51 is formed by a dry etching process, and the remaining photoresist is finally stripped. Since the thickness of the Al layer in the first electrode 51 is relatively thin and patterning is performed by a dry etching process, the first electrode 51 has good thickness uniformity and surface smoothness, which can effectively improve the capacitance uniformity of the capacitor structure. In addition, due to the patterning process, the overall process difficulty can be reduced while ensuring the flatness of the first electrode, thereby reducing production time and reducing production costs.

[0249] In an exemplary embodiment, a plurality of first vias and a plurality of third vias may be provided on the first insulating layer 61, the first lead 71 may be connected to the third connection electrode 43 through the plurality of first vias, and the third lead 73 may be connected to the second electrode plate 52 through the plurality of third vias. The present disclosure provides a plurality of vias and adopts a multi-contact via overlap method, which can effectively reduce contact resistance, effectively improve connection reliability, enhance capacitance performance, reduce capacitance loss, reduce the probability of process defects, and improve yield.

[0250] The structure and preparation process of the filter in the exemplary embodiment of the present disclosure are merely an exemplary description. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0251] The exemplary embodiment of the present disclosure also provides a method for preparing a filter to prepare the filter of the aforementioned embodiment. In an exemplary embodiment, the method for preparing the filter may include:

[0252] forming a metallized through-hole substrate, wherein the substrate substrate is provided with a conductive column penetrating the substrate substrate in a thickness direction;

[0253] A first structural layer is formed on one side of the first surface of the base substrate, a second structural layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on the side of the second structural layer away from the base substrate, a lead layer is arranged on the side of the first insulating layer away from the base substrate, a second insulating layer is arranged on the side of the lead layer away from the base substrate, and a pad layer is arranged on the side of the second insulating layer away from the base substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0254] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the substrate; the orthographic projection of the second electrode plate on the substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the substrate, and the orthographic projection of the capacitor dielectric layer on the substrate is located within the range of the orthographic projection of the first electrode plate on the substrate.

[0255] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are disposed in the same layer and are simultaneously formed by the same patterning process.

[0256] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are arranged in the same layer and are formed simultaneously through the same damascene process.

[0257] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode in the second structure layer.

[0258] In an exemplary embodiment, the capacitor dielectric layer and the second electrode plate are formed by a patterning process including a dry etching process.

[0259] The exemplary embodiment of the present disclosure also provides another method for preparing a filter to prepare the filter of the aforementioned embodiment. In an exemplary embodiment, the method for preparing a filter may include:

[0260] Forming a metallized blind hole substrate, wherein the substrate substrate is provided with a conductive column that does not penetrate the substrate substrate in a thickness direction;

[0261] A second structure layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on a side of the second structure layer away from the base substrate, a lead layer is arranged on a side of the first insulating layer away from the base substrate, a second insulating layer is arranged on a side of the lead layer away from the base substrate, and a pad layer is arranged on a side of the second insulating layer away from the base substrate;

[0262] Turning over the substrate, and performing a thinning process on the first surface of the substrate until the conductive pillars are exposed, wherein the first surface and the second surface are surfaces facing away from each other;

[0263] forming a first structural layer on one side of the first surface of the substrate;

[0264] The first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the materials of the first insulating layer and the second insulating layer include organic materials.

[0265] The present disclosure also provides an electronic device, comprising the filter of the above embodiment. The electronic device can be used in a radio frequency front-end device in a wireless communication device, such as a radio frequency filter.

[0266] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined by the attached claims.

Claims

1. A filter, characterized in that: The invention comprises a base substrate, wherein the base substrate is provided with a conductive column penetrating the base substrate in a thickness direction, a first structural layer is provided on a first surface of the base substrate, a second structural layer is provided on a second surface of the base substrate, a first insulating layer is provided on a side of the second structural layer away from the base substrate, a lead layer is provided on a side of the first insulating layer away from the base substrate, a second insulating layer is provided on a side of the lead layer away from the base substrate, and a pad layer is provided on a side of the second insulating layer away from the base substrate, wherein the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both comprise connecting electrodes connected to the conductive column, the second structural layer further comprises a capacitor structure, the lead layer comprises at least one lead connected to the capacitor structure, and the pad layer comprises at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer comprises an organic material.

2. The filter according to claim 1, characterized in that The capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

3. The filter according to claim 2, characterized in that The orthographic projection of the capacitor dielectric layer on the base substrate is located within the range of the orthographic projection of the first electrode plate on the base substrate.

4. The filter according to claim 3, characterized in that Along the direction away from the base substrate, the areas of the first electrode plate, the capacitor dielectric layer and the second electrode plate decrease in sequence.

5. The filter according to claim 3, characterized in that On a plane parallel to the substrate, in at least one direction, there is a first distance between an edge of the first electrode plate and an edge of the capacitor dielectric layer, and the first distance is greater than or equal to 50 nm.

6. The filter according to claim 3, characterized in that On a plane parallel to the substrate, in at least one direction, there is a second distance between the edge of the capacitor dielectric layer and the edge of the second electrode plate, and the second distance is greater than or equal to 50 nm.

7. The filter according to claim 2, characterized in that The first electrode includes a seed layer arranged on the second surface of the substrate and a conductive layer arranged on the side of the seed layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer arranged on the second surface of the substrate and a conductive layer arranged on the side of the seed layer away from the substrate.

8. The filter according to claim 7, characterized in that The seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

9. The filter according to claim 7, characterized in that The first electrode plate and the connecting electrode in the second structural layer are arranged in the same layer and are formed synchronously through the same patterning process.

10. The filter according to claim 7, characterized in that The orthographic projection of the connection electrode in the second structural layer on the base substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

11. The filter according to claim 2, characterized in that The first electrode plate includes a seed layer arranged on the second surface of the substrate, a conductive layer arranged on the side of the seed layer away from the substrate, and a conductive protective layer arranged on the side of the conductive layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer arranged on the second surface of the substrate, a conductive layer arranged on the side of the seed layer away from the substrate, and a conductive protective layer arranged on the side of the conductive layer away from the substrate.

12. The filter according to claim 11, characterized in that The seed layer includes a double-layer structure of a titanium layer and a copper layer. The material of the conductive protection layer includes titanium. The thickness of the titanium layer is 10 nm to 200 nm.

13. The filter according to claim 11, characterized in that The first electrode plate and the connecting electrode are arranged in the same layer and are formed synchronously through the same Damascene process.

14. The filter according to claim 11, characterized in that The first electrode plate and the connecting electrode are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode.

15. The filter according to claim 2, characterized in that The second electrode plate adopts a laminated structure of titanium layer / copper layer / titanium layer, or a laminated structure of titanium layer / aluminum layer / titanium layer.

16. The filter according to claim 15, characterized in that The thickness of the titanium layer is 30nm to 50nm, and the thickness of the copper layer or the aluminum layer is 200nm to 400nm.

17. The filter according to any one of claims 1 to 16, characterized in that: The connection electrode in the first structural layer includes a seed layer and a conductive layer arranged on a side of the seed layer away from the substrate. The seed layer includes a double-layer structure of a titanium layer and a copper layer. The thickness of the titanium layer is 10nm to 200nm.

18. The filter according to claim 17, characterized in that The first structural layer further includes a protective layer disposed on a side of the connecting electrode away from the base substrate. The material of the protective layer includes an organic material, and the thickness of the protective layer is 1 μm to 10 μm.

19. The filter according to any one of claims 1 to 16, characterized in that: In a direction perpendicular to the base substrate, a cross-sectional shape of the conductive pillar includes a pillar shape, a cone shape, or an hourglass shape.

20. An electronic device, characterized in that: A filter comprising the filter according to any one of claims 1 to 19.

21. A method for preparing a filter, characterized in that: include: forming a metallized through-hole substrate, wherein the substrate substrate is provided with a conductive column penetrating the substrate substrate in a thickness direction; A first structural layer is formed on one side of the first surface of the base substrate, a second structural layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on the side of the second structural layer away from the base substrate, a lead layer is arranged on the side of the first insulating layer away from the base substrate, a second insulating layer is arranged on the side of the lead layer away from the base substrate, and a pad layer is arranged on the side of the second insulating layer away from the base substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

22. The preparation method according to claim 21, characterized in that: The capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the base substrate, and the orthographic projection of the capacitor dielectric layer on the base substrate is located within the range of the orthographic projection of the first electrode plate on the base substrate.

23. The preparation method according to claim 22, characterized in that: The first electrode plate and the connecting electrode in the second structural layer are arranged in the same layer and are formed synchronously through the same patterning process.

24. The preparation method according to claim 22, characterized in that: The first electrode plate and the connecting electrode in the second structural layer are arranged in the same layer and are formed synchronously through the same Damascene process.

25. The preparation method according to claim 22, characterized in that: The first electrode plate and the connecting electrode in the second structure layer are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode in the second structure layer.

26. The preparation method according to claim 22, characterized in that: The capacitor dielectric layer and the second electrode plate are respectively formed by a patterning process including a dry etching process.

27. A method for preparing a filter, characterized in that: include: Forming a metallized blind hole substrate, wherein the substrate substrate is provided with a conductive column that does not penetrate the substrate substrate in a thickness direction; A second structure layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on a side of the second structure layer away from the base substrate, a lead layer is arranged on a side of the first insulating layer away from the base substrate, a second insulating layer is arranged on a side of the lead layer away from the base substrate, and a pad layer is arranged on a side of the second insulating layer away from the base substrate; Turning over the substrate, and performing a thinning process on the first surface of the substrate until the conductive pillars are exposed, wherein the first surface and the second surface are surfaces facing away from each other; forming a first structural layer on one side of the first surface of the substrate; The first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the materials of the first insulating layer and the second insulating layer include organic materials.

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