Storage device and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and provides a storage device, which comprises a substrate; the at least one memory device layer is arranged on the substrate, and the memory device layer at least comprises a memory unit, a write-in word line, a write-in bit line, a read word line and a read bit line; the storage unit comprises a write-in transistor and a read transistor; the write transistor comprises a first gate electrode, a first active layer, a first gate insulating layer and a first source electrode, and the first gate electrode is vertically arranged on the substrate; the reading transistor comprises a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode and a second drain electrode, and the second active layer is vertically arranged on the substrate; the second gate electrode further comprises a horizontal extension part connected with the drain end of the first active layer; in the vertical direction, the write word line is located on the side, away from the horizontal extension part, of the first source electrode. The invention further provides a preparation method of the storage device. The space in the vertical direction and the space in the horizontal direction are effectively utilized, and the storage density can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a storage device and a preparation method thereof. Background Art

[0002] With the miniaturization of technology nodes, DRAM (Dynamic Random Access Memory) has gradually changed from a 1T1C (1Transistor 1Capacitor) structure to a 2T0C (2Transistor0Transistor) structure. The 2T0C DRAM includes a write transistor (WTR) and a read transistor (RTR). The drain of the write transistor WTR is connected to the gate of the read transistor RTR, so that the gate capacitance of the read transistor RTR serves as a storage node (SN). A capacitor-less structure is adopted, which makes the structure and process flow of the 2T0C DRAM simpler, lower cost, and smaller in size.

[0003] However, in the related art, since transistors with horizontal channels are used as write transistors and read transistors, the write transistor WTR and the read transistor RTR are usually arranged on the same plane, resulting in a larger occupied space on the plane and less utilization of the vertical space. The storage density of the ultimately formed 2T0C DRAM is low, which is difficult to meet high storage requirements. Summary of the invention

[0004] An embodiment of the present invention provides a storage device, aiming to solve the technical problem in the prior art that a write transistor and a read transistor are arranged side by side on a plane, occupying a large plane space and making less use of the vertical space, resulting in a low storage density of the storage device.

[0005] The embodiment of the present invention is implemented as follows: a storage device includes:

[0006] a substrate comprising an insulating surface; and

[0007] At least one memory device layer disposed on the insulating surface, the memory device layer comprising memory cells, write word lines, write bit lines, read word lines, and read bit lines;

[0008] The memory cell includes a write transistor and a read transistor;

[0009] The write transistor comprises a first gate electrode, a first active layer, a first gate insulating layer and a first source electrode, wherein the first gate electrode is vertically disposed on the substrate, the first active layer is disposed at least partially around the first gate electrode, the first gate insulating layer is disposed between the first gate electrode and the first active layer, and the first source electrode is connected to a source terminal of the first active layer;

[0010] The read transistor includes a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode and a second drain electrode, the second active layer is vertically disposed on the substrate, the second gate electrode is disposed at least partially around the second active layer, the second gate insulating layer is disposed between the second gate electrode and the second active layer, the second source electrode is connected to the source terminal of the second active layer, and the second drain electrode is connected to the drain terminal of the second active layer;

[0011] The second gate electrode further includes a horizontal extension portion, and the horizontal extension portion is connected to the drain terminal of the first active layer;

[0012] The first gate electrode is connected to a write word line, the first source electrode is connected to a write bit line, the second source electrode is connected to a read word line, and the second drain electrode is connected to a read bit line;

[0013] In the vertical direction, the write word line is located at a side of the first source electrode away from the horizontal extension portion.

[0014] Furthermore, the first source electrode and the write bit line connected thereto are formed as one body, the second source electrode and the read word line connected thereto are formed as one body, and the second drain electrode and the read bit line connected thereto are formed as one body.

[0015] Furthermore, the memory device layer includes a plurality of the memory cells, and the plurality of memory cells are arranged in an array in a first horizontal direction and a second horizontal direction, and the first horizontal direction and the second horizontal direction intersect;

[0016] A plurality of the write word lines and the read bit lines are provided, and the write word lines and the read bit lines are arranged at intervals in the second horizontal direction and extend along the first horizontal direction, the write word lines are connected to the first gate electrodes of the plurality of the write transistors arranged in the first horizontal direction, and the read bit lines are connected to the second drain electrodes of the plurality of the read transistors arranged in the first horizontal direction;

[0017] The write bit lines and the read word lines are provided in plurality and are alternately spaced in the first horizontal direction and extend along the second horizontal direction. The write bit lines are connected to the first source electrodes of the plurality of write transistors arranged in the second horizontal direction, and the read word lines are connected to the second source electrodes of the plurality of read transistors arranged in the second horizontal direction.

[0018] Furthermore, the second source electrode and the first source electrode are located in the same layer.

[0019] Furthermore, in the vertical direction:

[0020] The second source electrode and the first source electrode are located in the same layer, and a distance between the second source electrode and the opposing surface of the second gate electrode is smaller than a distance between the first source electrode and the opposing surface of the horizontal extension portion; or

[0021] The second drain electrode is formed as a whole with the read bit line, and the distance between the second drain electrode and the opposite surface of the second gate electrode is smaller than the distance between the read bit line and the opposite surface of the second gate electrode.

[0022] Furthermore, in the storage unit:

[0023] The first active layer overlaps with the first source electrode and the orthographic projection of the horizontal extension portion on the substrate;

[0024] The second active layer overlaps with the orthographic projections of the second source electrode, the second gate electrode, and the second drain electrode on the substrate.

[0025] Furthermore, in the orthographic projection on the substrate:

[0026] The second gate electrode is parallel to two opposite sides of the extending direction of the read bit line, and overlaps with two opposite sides of the read bit line respectively.

[0027] Furthermore, in the orthographic projection of the substrate:

[0028] The second gate electrode overlaps with the write bit line and the read word line, and the second gate electrode is parallel to two opposite sides in the extension direction of the write bit line and the read word line, and overlaps with the sides of the write bit line and the read word line overlapping with the second gate electrode respectively.

[0029] Furthermore, the first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion; or

[0030] The first active layer is a tubular structure, and an end of the tubular structure corresponding to the drain end of the first active layer passes through the horizontal extension portion.

[0031] Furthermore, the storage device comprises a plurality of storage device layers, wherein the plurality of storage device layers are vertically stacked on the substrate;

[0032] The first active layer in at least one layer of the multi-layer memory device layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion; and the first active layer in at least another layer of the multi-layer memory device layer is a tubular structure, and the end of the tubular structure corresponding to the drain end of the first active layer passes through the horizontal extension portion.

[0033] Furthermore, the storage device comprises a plurality of storage device layers, wherein the plurality of storage device layers are vertically stacked on the substrate;

[0034] The storage device further comprises an insulating isolation layer, and the insulating isolation layer is arranged between two adjacent storage device layers.

[0035] Furthermore, the storage device comprises a plurality of storage device layers, wherein the plurality of storage device layers are vertically stacked on the substrate;

[0036] The plurality of memory device layers are divided into at least one common unit along the vertical direction, wherein the common unit includes two memory device layers adjacent to each other in the vertical direction;

[0037] In the shared unit, the adjacent memory device layers share the write word line or the read bit line;

[0038] And in one of the two adjacent memory device layers, the first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion of the one;

[0039] In the other of the two adjacent memory device layers, the first active layer is a tubular structure, and an end of the tubular structure corresponding to a drain end of the first active layer passes through the horizontal extension portion.

[0040] Furthermore, the storage device further includes an insulating isolation layer, and the insulating isolation layer is arranged between the common unit and the storage device layer adjacent to the common unit.

[0041] Furthermore, the materials of the write word line, the write bit line, the read word line, the read bit line, the first gate electrode, the first source electrode, the second gate electrode, the second source electrode and the second drain electrode are the same or different and include conductors;

[0042] The first active layer and the second active layer are made of the same or different materials and include oxide semiconductors.

[0043] Furthermore, the conductor includes at least one of aluminum, titanium, tungsten, titanium nitride and doped polysilicon;

[0044] The oxide semiconductor includes at least one of indium oxide, tin oxide, gallium oxide, indium tin oxide, zinc oxide, indium zinc oxide, and indium gallium zinc oxide.

[0045] The present invention also provides a method for preparing a storage device, which is used to prepare the storage device according to any one of the above items, comprising the following steps:

[0046] S1. Providing a first substrate;

[0047] S2. Preparing at least one layer of the memory device layer on the first surface of the first substrate;

[0048] S3. The first substrate is the substrate, and the first surface is the insulating surface, or the memory device layer formed in step S2 is transferred to the insulating surface of the substrate.

[0049] Furthermore, the preparing at least one storage device layer on the first surface includes preparing at least one first storage device layer, and the preparing at least one first storage device layer includes the following steps:

[0050] S21. On the first surface, a first conductor layer, a first insulating layer, and a second conductor layer are sequentially prepared, and a first patterning process is performed to form a first gap penetrating the second conductor layer, the first insulating layer, and the first conductor layer to form the read bit line, the second drain electrode, and the first patterned conductor layer, and a first isolation insulating layer is prepared, wherein the first isolation insulating layer covers the upper surface of the first patterned conductor layer;

[0051] S22. forming a first hole penetrating the first isolation insulating layer, the first patterned conductor layer and the first insulating layer, and sequentially forming the second gate insulating layer and the second active layer on the sidewall of the first hole;

[0052] S23. Prepare a third conductor layer on the upper surface of the first isolation insulating layer, perform a second patterning process to form a second slit penetrating the third conductor layer, and a third slit penetrating the third conductor layer, the first isolation insulating layer, and the first patterned conductor layer to form the second gate electrode, the write bit line, the read word line, the first source electrode, and the second source electrode, and prepare a second isolation insulating layer, wherein the second isolation insulating layer covers the upper surface of the first source electrode;

[0053] S24. forming a second hole penetrating the second isolation insulating layer, the first source electrode and the first isolation insulating layer, and sequentially forming the first active layer, the first gate insulating layer and the first gate electrode on the sidewall of the second hole;

[0054] S25. Prepare a fourth conductor layer and perform a third patterning process on the fourth conductor layer to form the write word line, wherein the write word line is isolated from the read word line.

[0055] Furthermore, in the step S22, the step of sequentially forming the second gate insulating layer and the second active layer on the sidewall of the first hole comprises the following steps:

[0056] S221. depositing a second gate insulating layer material, the second gate insulating layer material covering the upper surface of the first isolation insulating layer, the sidewall and the bottom surface of the first hole, and performing anisotropic etching to remove a portion of the second gate insulating layer material located on the upper surface of the first isolation insulating layer and the bottom surface of the first hole, to form a second gate insulating layer located on the sidewall of the first hole;

[0057] S222. Fill the second active layer material in the groove surrounded by the side wall of the second gate insulating layer and the bottom surface of the first hole, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the first isolation insulating layer to form the second active layer.

[0058] Furthermore, the step of preparing at least one storage device layer on the first surface includes preparing at least one first storage device layer, and the step of preparing at least one first storage device layer further includes the following steps:

[0059] S26. Prepare a first conductor layer and perform a first patterning process on the first conductor layer to form the write word line, prepare a first insulating layer to cover the write word line, prepare a second conductor layer on a surface of the first insulating layer away from the write word line and perform a second patterning process to form the write bit line, the read word line, the first source electrode and the second source electrode, prepare a first isolation insulating layer to cover the write bit line, the read word line, the first source electrode and the second source electrode;

[0060] S27. Preparing a third conductor layer on a surface of the first isolation insulating layer away from the write word line;

[0061] performing a third patterning process on the third conductor layer to form a second patterned conductor layer, the second patterned conductor layer overlapping with orthographic projections of the first source electrode and the second source electrode on the first substrate;

[0062] forming a third hole penetrating the second patterned conductor layer or the third conductor layer, the first isolation insulating layer, and the first source electrode, forming the first active layer on the sidewall of the third hole, forming a fourth hole extending from the upper surface of the second patterned conductor layer or the third conductor layer to the bottom of the third hole and exposing the write word line, and sequentially forming the first gate insulating layer and the first gate electrode connected to the write word line on the sidewall of the fourth hole;

[0063] S28. forming a second insulating layer covering the second patterned conductor layer and the first gate electrode, forming a fifth hole penetrating the second insulating layer, the second patterned conductor layer, the first isolation insulating layer and exposing the second source electrode, and sequentially forming the second gate insulating layer and the second active layer connected to the second source electrode on the sidewall of the fifth hole;

[0064] S29. Form a fourth conductor layer on a side of the second insulating layer away from the write word line, and perform a third patterning process to form a fourth gap penetrating the fourth conductor layer, the second insulating layer, and the second patterned conductor layer to form the read bit line and the second gate electrode.

[0065] Furthermore, in the step S28, the step of sequentially forming the second gate insulating layer on the sidewall of the fifth hole and the second active layer connected to the second source electrode comprises the following steps:

[0066] S281. depositing a second gate insulating layer material, the second gate insulating layer material covers the upper surface of the second insulating layer, the sidewalls and the bottom surface of the fifth hole, and performing anisotropic etching to remove a portion of the second gate insulating layer material located on the upper surface of the second insulating layer and the bottom surface of the fifth hole, to form a second gate insulating layer located on the sidewalls of the fourth hole;

[0067] S282. Fill the second active layer material in the groove surrounded by the side wall of the second gate insulating layer and the bottom surface of the fifth hole, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the second insulating layer to form the second active layer.

[0068] In the storage device of the embodiment of the present invention, both the write transistor and the read transistor are vertical channel transistors. Compared with the horizontal channel transistors in the prior art, the device density of the vertical channel transistor is higher, and the write transistor and the read transistor are arranged horizontally and overlap in the vertical direction. Compared with the two vertical channel transistors directly stacked vertically in the 2T0C of the prior art, the horizontal space is utilized and the vertical space is saved. The present invention arranges the vertical channel transistors in the horizontal direction and designs them to overlap to a certain extent in the vertical direction, thereby improving the space utilization in the vertical and horizontal directions, thereby effectively improving the storage density of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 is a three-dimensional schematic diagram of a storage device according to an embodiment of the present invention;

[0070] Figure 2a is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0071] Figure 2b is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0072] Figure 3a is a schematic structural diagram of a write transistor according to an embodiment of the present invention;

[0073] Figure 3b is a schematic structural diagram of a write transistor according to an embodiment of the present invention;

[0074] Figure 4 is a schematic structural diagram of a read transistor according to an embodiment of the present invention;

[0075] Figure 5a is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0076] Figure 5b is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0077] Figure 6 is a schematic structural diagram of a storage device according to an embodiment of the present invention;

[0078] Figure 7a is a schematic structural diagram of a storage device according to an embodiment of the present invention;

[0079] Figure 7b is a schematic structural diagram of a storage device according to an embodiment of the present invention;

[0080] Figure 8 is a schematic structural diagram of a storage device according to an embodiment of the present invention;

[0081] Fig. 9is a schematic structural diagram of a storage device according to an embodiment of the present invention;

[0082] Fig.10 is a schematic flow chart of a method for preparing a storage device according to an embodiment of the present invention;

[0083] Fig.11 , Fig.12a , Figure 12b , Fig.12c , Fig.13a , Fig.13b , Fig.14a , Fig.14b , Fig.14c , Fig.15a , Fig.15b , Fig.16a and Fig.16b is a schematic diagram of a process flow of a method for preparing a storage device according to an embodiment of the present invention;

[0084] Fig.17 is a schematic flow chart of a method for preparing a storage device according to another embodiment of the present invention;

[0085] Fig.18 , Fig.19 , Fig.20a , Fig.20b , Fig.21 , Fig. 22 , Fig.23a , Figure 23b , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29a , Fig.29b , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34a , Fig.34b and Fig.34c is a schematic diagram of a process flow of a method for preparing a storage device according to another embodiment of the present invention;

[0086] Fig.35 Schematic diagram of a storage unit connection circuit according to an embodiment of the present invention.

[0087] Description of main reference numerals:

[0088] Memory device-1000; semiconductor substrate-200; memory device layer-100; memory cell-110; write transistor-111; first gate electrode-1111; first active layer-1112; first gate insulating layer-1113; first source electrode-1114; read transistor-112; second gate electrode-1121; horizontal extension-11211; second active layer-1122; second gate insulating layer-1123; second source electrode-1124; second drain electrode-1125; write word line-120; write bit Line-130; read word line-140; read bit line-150; insulating isolation layer-160; common unit-300; first substrate-1; first conductor layer-2; first insulating layer-3; second conductor layer-4; first patterned conductor layer-5; first isolation insulating layer-6; first hole-7; third conductor layer-8; second isolation insulating layer-9; second hole-10; fourth conductor layer-11; second patterned conductor layer-12; third hole-13; fourth hole-14; spacing insulating layer-15; second insulating layer-16; fifth hole-17. DETAILED DESCRIPTION

[0089] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0090] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated in the description of the direction and positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0091] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0092] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, the above materials are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0093] The 3D-DRAM storage device includes one or more layers of storage device layers stacked in a direction vertical or approximately vertical to the substrate (e.g., the Z-axis direction), and each storage device layer includes a plurality of storage cells distributed in an array. Each storage cell may include a 2T0C-DRAM, that is, the storage cell includes 2 transistors and 0 capacitors. The 2 transistors are a write transistor and a read transistor, respectively. The drain of the write transistor is connected to the gate of the read transistor, and the read word line (Read World Line, RWL), the read bit line (Read Bit Line, RBL), the write word line (Write Word Line, WWL) and the write bit line (Write Bit Line, WBL) are respectively arranged at corresponding positions and connected to corresponding positions on the transistor.

[0094] For example, the gate of the write transistor is connected to the write word line, the source of the write transistor is connected to the write bit line, the source of the read transistor is connected to the read word line, and the drain of the read transistor is connected to the read bit line.

[0095] See also Figure 1 and Figure 2a , 2b The storage device 1000 of the present invention includes a substrate 200 and at least one storage device layer 100 disposed on the substrate 200. In the embodiment shown in the above figure, the substrate 200 may include a semiconductor substrate 201 and an insulating layer 202 located on a side of the semiconductor substrate 201 close to the storage device layer 100, and a surface of the insulating layer 202 away from the semiconductor substrate 201 is formed as an insulating surface of the substrate 200.

[0096] The semiconductor substrate 201 may include a semiconductor material, for example, at least one of silicon (eg, single crystal silicon Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC).

[0097] In one embodiment, the substrate 200 may be a single-layer structure, for example, a single-layer structure made of at least one of silicon, germanium, gallium arsenide, and the like.

[0098] In another embodiment, the substrate 200 may also be a multilayer structure, for example, a composite substrate including a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, silicon on insulator, germanium on insulator, or silicon germanium on insulator.

[0099] By way of example, the semiconductor substrate 201 may be a single crystal silicon substrate. Optionally, the semiconductor substrate 201 includes a logic circuit.

[0100] In other embodiments, the substrate 200 is an insulating substrate. The insulating substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer. Alternatively, the substrate 200 may also be an insulating dielectric material such as silicon dioxide (SiO2) or silicon nitride (SiN).

[0101] In one embodiment, the insulating layer 202 may include an insulating material commonly used in the art, such as silicon dioxide (SiO2), silicon nitride (SiN x )wait.

[0102] The memory device layer 100 at least includes a memory cell 110 , a write word line 120 , a write bit line 130 , a read word line 140 and a read bit line 150 . The memory cell 110 includes a write transistor 111 and a read transistor 112 .

[0103] See also Figure 2a and Figure 3a In the illustrated embodiment, the write transistor 111 includes a first gate electrode 1111, a first active layer 1112, a first gate insulating layer 1113 and a first source electrode 1114. The first gate electrode 1111 is arranged along the Z-axis direction, that is, vertically on the substrate 200. The first active layer 1112 is arranged at least partially around the first gate electrode 1111. The first gate insulating layer 1113 is arranged between the first gate electrode 1111 and the first active layer 1112. The first source electrode 1114 is connected to the source terminal of the first active layer 1112.

[0104] See also Figure 2b and Figure 3b In another embodiment of the present invention shown, the write transistor 111 includes: a first gate electrode 1111, a first active layer 1112, a first gate insulating layer 1113 and a first source electrode 1114, the first gate electrode 1111 is arranged along the Z-axis direction, that is, vertically on the substrate 200, the first active layer 1112 is arranged on at least part of the periphery of the first gate electrode 1111, the first gate insulating layer 1113 is arranged between the first gate electrode 1111 and the first active layer 1112, and the first source electrode 1114 is connected to the source terminal of the first active layer 1112.

[0105] See also Figure 2a , Figure 2b and Figure 4 The read transistor 112 includes a second gate electrode 1121, a second active layer 1122, a second gate insulating layer 1123, a second source electrode 1124 and a second drain electrode 1125. The second active layer 1122 is arranged on the substrate 200 along the Z-axis direction, that is, vertically. The second gate electrode 1121 is arranged on at least a portion of the periphery of the second active layer 1122. The second gate insulating layer 1123 is arranged between the second gate electrode 1121 and the second active layer 1122. The second source electrode 1124 is connected to the source terminal of the second active layer 1122, and the second drain electrode 1125 is connected to the drain terminal of the second active layer 1122.

[0106] See also Figures 2a to 4 The second gate electrode 1121 further includes a horizontal extension portion 11211 , and the horizontal extension portion 11211 is connected to the drain terminal of the first active layer 1112 .

[0107] In an embodiment of the present invention, the second gate electrode 1121 also includes a horizontal extension portion 11211, and the horizontal extension portion 11211 is connected to the drain end of the first active layer 1112 to realize the electrical connection between the write transistor 111 and the read transistor 112, that is, the horizontal extension portion 11211 includes the first drain electrode of the write transistor 111, thereby making the storage unit 110 simple in structure and reducing the process difficulty and production cost.

[0108] The horizontal extension portion 1121 is parallel or approximately parallel to the substrate 200 . Preferably, the second gate electrode 1121 is parallel or approximately parallel to the substrate 200 .

[0109] The first gate electrode 1111 is connected to the write word line 120, the first source electrode 1114 is connected to the write bit line 130, the second source electrode 1124 is connected to the read word line 140, and the second drain electrode 1125 is connected to the read bit line 150. In the Z-axis direction, that is, the vertical direction, the write word line 120 is located on the side of the first source electrode 1114 away from the horizontal extension portion 11211. When the first source electrode 1114 and the write bit line 130 are formed as one body, the write word line 120 is located on the side of the write bit line 130 away from the horizontal extension portion 11211.

[0110] It should be noted that the write word line 120 and the write bit line 130 are signal lines at corresponding positions of the storage device 100 and provide corresponding functions. Specifically:

[0111] The write word line 120 is electrically connected to the gate of the write transistor 111 in the memory cell 110, and when a write operation is performed, a voltage is applied through the write word line 120 to turn on the write transistor 111. That is, the write word line 120 is a signal line electrically connected to the gate of the write transistor 111, and a voltage is applied during a write operation to turn on the write transistor;

[0112] The write bit line 130 is electrically connected to the source of the write transistor 111 in the memory cell 110, and when the write transistor 111 is turned on, a voltage is applied through the write bit line 130 to charge or discharge the storage node SN through the write transistor 111, so that the storage node SN presents a high voltage or a low voltage, representing data 1 and 0, respectively, thereby completing the write operation. That is, the write bit line 130 is a signal line electrically connected to the source of the write transistor 111, and a voltage is applied when the write transistor 111 is turned on to charge or discharge the storage node SN through the write transistor 111.

[0113] In addition, specifically for the read word line 140 and the read bit line 150:

[0114] The read word line 140 is a signal line for applying a read voltage to the second source electrode 1124 of the read transistor 112 connected thereto during a read operation, and the read bit line 150 is a signal line for writing data from the read storage node SN by detecting the magnitude of the current therein during a read operation; or

[0115] The read bit line 150 is a signal line that applies a read voltage to the second drain electrode 1125 of the read transistor 112 connected thereto during a read operation. The read word line 150 is a signal line that is connected to the second source electrode 1124 and writes data from the read storage node SN by detecting the magnitude of the current therein during a read operation.

[0116] The second source electrode 1124 and the first source electrode 1114 are located on the same side of the second gate electrode 1121, and the second drain electrode 1125 is located on the side of the second gate electrode 1121 away from the first source electrode 1114. It can be understood that for the reading transistor 112, the second source electrode 1124 and the second drain electrode 1125 do not limit the flow direction of the channel current of the reading transistor 112 during the reading operation.

[0117] In a storage unit 110 of an embodiment of a storage device 1000 of the present invention, a first gate electrode 1111 of a write transistor 111 is vertically disposed on a substrate 200, a first active layer 1112 is disposed at least partially around the first gate electrode 1111, a second active layer 1122 of a read transistor 112 is vertically disposed on the substrate 200, a second gate electrode 1121 is disposed at least partially around the second active layer 1122, and the second gate electrode 1121 further includes a horizontal extension portion 11211, and the horizontal extension portion 11211 is connected to the drain terminal of the first active layer 1112.

[0118] That is, the write transistor 111 and the read transistor 112 in the memory cell 110 of the present invention are both vertical channel transistors, and the storage density is higher than the horizontal channel transistors in the prior art. In addition, the write transistor 111 and the read transistor 112 are arranged horizontally and overlap in the vertical direction, which saves space in the vertical direction compared to the two vertical channel transistors stacked vertically in the 2T0C of the prior art. Therefore, the present invention arranges the vertical channel transistors in the horizontal direction and designs the two to overlap in the vertical direction, thereby improving the space utilization in the vertical and horizontal directions, thereby effectively improving the storage density of the memory cell 110.

[0119] The first gate electrode 1111 may be a solid column structure. In other embodiments, the first gate electrode 1111 may also be a hollow structure, such as a groove or a tube structure, in which case a dielectric layer may be filled in the hollow of the first gate electrode 1111, the dielectric layer includes an insulating material, the dielectric layer may be a single-layer structure or a multi-layer structure, and the dielectric layer may include an air gap, which is not specifically limited here.

[0120] The first active layer 1112 is disposed at least partially around the first gate electrode 1111 , which can be understood as the first active layer 1112 is disposed circumferentially around the first gate electrode 1111 , and may completely surround the first gate electrode 1111 , or may only partially surround the first gate electrode 1111 .

[0121] Preferably, the first active layer 1112 completely surrounds the first gate electrode 1111 , thereby increasing the channel width of the write transistor and increasing the write current when the write transistor is turned on.

[0122] The second active layer 1122 may be a solid column structure. In other embodiments, the second active layer 1122 may also be a hollow structure, such as a groove or a tube structure, in which case a dielectric layer may be filled in the hollow of the second active layer 1122, the dielectric layer includes an insulating material, the dielectric layer may be a single-layer structure or a multi-layer structure, and the dielectric layer may include an air gap, which is not specifically limited here.

[0123] The second gate electrode 1121 is disposed at least partially around the second active layer 1122 , which can be understood as the second gate electrode 1121 is disposed circumferentially around the second active layer 1122 , and may completely surround the second active layer 1122 or partially surround the second active layer 1122 .

[0124] Preferably, the second gate electrode 1121 completely surrounds the second active layer 1122, thereby increasing the channel width of the read transistor, and obtaining a larger read current in the read operation, thereby improving the read margin.

[0125] like Figure 1In the illustrated embodiment, the memory device layer 100 includes a plurality of memory cells 110, and the plurality of memory cells 110 are distributed in an array in the memory device layer 100. For example, the plurality of memory cells 110 in the memory device layer 100 are arranged in an array along a first horizontal direction and a second horizontal direction.

[0126] A plurality of write word lines 120 and read bit lines 150 are provided and are arranged at intervals in the second horizontal direction and extend along the first horizontal direction. The write word line 120 is connected to the first gate electrodes 1111 of the plurality of write transistors 111 arranged in the first horizontal direction, and the read bit line 150 is connected to the second drain electrodes 1125 of the plurality of read transistors 112 arranged in the first horizontal direction.

[0127] The write bit line 130 and the read word line 140 are prepared in the same layer and are arranged in multiple numbers. They are alternately arranged in the first horizontal direction and extend in the second horizontal direction. The write bit line 130 is connected to the first source electrodes 1114 of the multiple write transistors 111 arranged in the second horizontal direction, and the read word line 140 is connected to the second source electrodes 1124 of the multiple read transistors 112 arranged in the second horizontal direction.

[0128] The write bit lines 130 and the read word lines 140 are alternately arranged in a first horizontal direction and include:

[0129] like Figure 1 In the illustrated embodiment, the write bit lines 130 and the read word lines 140 are alternately spaced one by one;

[0130] In other embodiments, two adjacent memory cells 110 in the first horizontal direction are symmetrically arranged, and the write bit lines 130 and read word lines 140 connected to the two symmetrical memory cells 100 are also symmetrically arranged, that is, the write bit lines 130 and the read word lines 140 are alternately spaced in pairs.

[0131] It can be understood that the first and second horizontal directions are two directions extending parallel or approximately parallel to the substrate 200, and the first and second horizontal directions intersect. For example, the first horizontal direction is perpendicular to the second horizontal direction, but the present invention does not specifically limit the angle between the first and second horizontal directions, and they can intersect.

[0132] exist Figure 1 In the illustrated embodiment, the first horizontal direction is the X-axis direction, and the second horizontal direction is the Y-axis direction.

[0133] In this way, a write word line 120 can be connected to a plurality of write transistors 111 arranged at intervals along the first horizontal direction, a write bit line 130 can be connected to a plurality of write transistors 111 arranged at intervals along the second horizontal direction, a read word line 140 can be connected to a plurality of read transistors 112 arranged at intervals along the second horizontal direction, and a read bit line 150 can be connected to a plurality of read transistors 112 arranged at intervals along the first horizontal direction.

[0134] Since there is an intersection between the write word line 120 and the write bit line 130 and an intersection between the read word line 140 and the read bit line 150, the transistor at the intersection can be selected through the intersection of the signal lines, so that any storage unit 110 in the storage device layer 100 can be selected for read and write operations.

[0135] In the memory cell 110 , the arrangement direction of the write transistor 111 and the read transistor 112 may be the same as or different from the first and second horizontal directions, which is not specifically limited in the present invention.

[0136] Furthermore, in an embodiment of the present invention, the materials of the write word line 120, the write bit line 130, the read word line 140, the read bit line 150, the first gate electrode 1111, the first source electrode 1114, the second gate electrode 1121, the second source electrode 1124 and the second drain electrode 1125 are the same or different and include conductors.

[0137] The conductor includes at least one of aluminum, titanium, tungsten, titanium nitride and doped polysilicon.

[0138] In one embodiment, the material of the write bit line 130 may be the same as that of the first source electrode 1114 , the material of the read bit line 150 may be the same as that of the second drain electrode 1125 , and the material of the read word line 140 may be the same as that of the second source electrode 1124 .

[0139] Therefore, the above-mentioned components made of the same material can be prepared in the same layer and formed as one body, that is, the write bit line 130 can be formed as one body with the first source electrode 1114 connected thereto, the read bit line 150 can be formed as one body with the second drain electrode 1125 connected thereto, and the read word line 140 can be formed as one body with the second source electrode 1124 connected thereto, thereby simplifying the manufacturing process and reducing production costs.

[0140] It can be understood that the write bit line 130 can be formed as a whole with the source electrode 1114 connected thereto, the read bit line 150 can be formed as a whole with the second drain electrode 1125 connected thereto, and the read word line 140 can be formed as a whole with the second source electrode 1124 connected thereto, respectively: a portion of the write bit line 130 can be formed as the first source electrode 1114, a portion of the read bit line 150 can be formed as the second drain electrode 1125, and a portion of the read word line 140 can be formed as the second source electrode 1124.

[0141] In a preferred embodiment of the present invention, the write bit line 130 is made of the same material and the same layer as the first source electrode 1114, the read word line 140, and the second source electrode 1124. The write bit line 130 and the first source electrode 1114 are formed as one body, and the read word line 140 and the second source electrode 1124 are formed as one body. Thus, the preparation of the write bit line 130, the first source electrode 1114, the read word line 140, and the second source electrode 1124 can be completed in a single patterned film preparation process, thereby simplifying the manufacturing process and reducing production costs.

[0142] In addition, the material of the write word line 120 can be the same as or different from the material of the first gate electrode 1111, and the material of the read bit line 150 and the read word line 140 can be the same as or different from the material of the second gate electrode 1121. The materials of the first gate electrode 1111 and the second gate electrode 1121 can be set according to actual needs to achieve good electrical characteristics of the write transistor 111 and the read transistor 112.

[0143] It is worth noting that when the material of the write word line 120 is the same as that of the first gate electrode 1111 , the two can be prepared simultaneously and thus formed into one.

[0144] Please combine Figure 1 , Figure 2a and Figure 2b In the memory cell 110 in the embodiment of the present invention, the first active layer 1112 is arranged on the periphery of the first gate electrode 1111, the first source electrode 1114 is connected to the source end of the first active layer 1112, the write bit line 130 is connected to the first source electrode 1114, and the read word line 140 is connected to the second source electrode 1124.

[0145] Thus, the write bit line 130 and the read word line 140 can be set in the same layer, and the two can be set at an interval and extend in the same direction to be respectively connected to the write transistor 111 and the read transistor 112, thereby further reducing the height of the storage unit 110 in the Z-axis direction, and allowing the write bit line 130 and the read word line 140 to be prepared in the same process step, reducing the process difficulty and production cost.

[0146] It is worth mentioning that although Figure 1 , Figure 2a , Figure 2b ,as well as Figures 6 to 9 Although not fully shown, an insulating spacer layer is also filled between the write transistor 111 and the read transistor 112, and between the write word line 120, the write bit line 130, the read word line 140, the read bit line 150 and the second gate electrode 1121 (including the horizontal extension portion 11211). The insulating spacer layer includes an insulating material, such as silicon oxide SiO2, silicon nitride Si3N4, etc., and can also be TEOS (tetraethoxysilane) or a low dielectric constant material.

[0147] In addition, the first active layer 1112 and the second active layer 1122 include oxide semiconductor materials, and the materials of the first active layer 1112 and the second active layer 1122 may be the same or different. The oxide semiconductor material includes at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, zinc oxide ZnO, and indium zinc oxide IZO.

[0148] In the embodiment of the present invention, the material of the first active layer 1112 and the second active layer 1122 is indium gallium zinc oxide (IGZO).

[0149] Furthermore, the first gate insulating layer 1113 and the second gate insulating layer 1123 include insulating materials, such as silicon oxide SiOx, silicon nitride SiN x , high dielectric constant materials, etc., or combination materials, laminated materials, or combined laminated materials of the above materials.

[0150] See also Figure 1 , Figure 2a , Figure 2b , Figures 6 to 9 Furthermore, the memory device layer 100 includes a plurality of memory cells 110, and the plurality of memory cells 110 are distributed in an array in the memory device layer 100. For example, the plurality of memory cells 110 in the memory device layer 100 are arranged in an array in a first horizontal direction and a second horizontal direction.

[0151] There are multiple write word lines 120 and read bit lines 150, which are arranged in a spaced-apart manner in the second horizontal direction and extend along the first horizontal direction. The write word line 120 is connected to the first gate electrodes 1111 of the multiple write transistors 111 arranged in the first horizontal direction, and the read bit line 150 is connected to the second drain electrodes 1125 of the multiple read transistors 112 arranged in the first horizontal direction.

[0152] A plurality of write bit lines 130 and a plurality of read word lines 140 are provided and are alternately spaced in the first horizontal direction and extend in the second horizontal direction. The write bit lines 130 are connected to the first source electrodes 1114 of the plurality of write transistors 111 arranged in the second horizontal direction, and the read word lines 140 are connected to the second source electrodes 1124 of the plurality of read transistors 112 arranged in the second horizontal direction.

[0153] In some embodiments, the first source electrode 1114 and the second source electrode 1124 are located in the same layer. When the first source electrode and the write bit line 130 are formed as one, and the second source electrode 1124 and the read word line 140 are formed as one, the write bit line 130 and the read word line 140 are located in the same layer.

[0154] In some embodiments, the write bit lines 130 and the read word lines 140 are located in different layers, but are still alternately arranged in a first horizontal direction and extend in a second horizontal direction.

[0155] In one embodiment, the second source electrode 1124 and the first source electrode 1114 are prepared in the same layer, that is, they are located in the same layer, and in the vertical direction, the distance between the relative surfaces of the second source electrode 1124 and the second gate electrode 1121 is smaller than the distance between the relative surfaces of the first source electrode 1114 and the horizontal extension portion 11211.

[0156] In this way, the distance between the first source electrode 1114 and the relative surface of the horizontal extension portion 11211 can be increased, that is, the distance between the first source electrode 1114 and the first drain electrode can be extended, and the impedance between the source and drain terminals of the write transistor 111 can be increased, thereby reducing the leakage current.

[0157] The second source electrode 1124 and the first source electrode 1114 are located in the same layer. If the distance between the surfaces of the second source electrode 1124 and the second gate electrode 1121 is the same, the leakage current of the write transistor 111 is reduced while the impedance between the source and drain terminals of the read transistor 112 is increased when the read transistor 112 is turned on, thereby reducing the read margin. In the vertical direction, the distance between the opposing surfaces of the second source electrode 1124 and the second gate electrode 1121 is smaller than the distance between the opposing surfaces of the first source electrode 1114 and the horizontal extension 11211, thereby improving the leakage current of the write transistor 111 and the read margin of the memory cell 110 at the same time.

[0158] like Figure 5aIn the illustrated embodiment, the distance between the relative surfaces of the second source electrode 1124 and the second gate electrode 1121 is smaller than the distance between the relative surfaces of the first source electrode 1114 and the horizontal extension portion 1121, that is, the distance between the surface of the second active layer 1122 away from the second gate electrode 1121 and the surface of the second gate electrode 1121 close to the first source electrode 1114 is smaller than the distance between the relative surfaces of the first source electrode 1114 and the second gate electrode 1121.

[0159] For example, see Figure 5a , Figures 13a to 14c The second active layer 1122 is prepared in the first hole 7, and by making the surface of the second active layer 1122 away from the second gate electrode 1121 closer to the second gate electrode 1121 than the opening of the first hole 7, that is, the second active layer 1122 only fills a partial depth of the first hole 7 from bottom to top, it can be achieved that the first source electrode 1114 and the second source electrode 1124 are located in the same layer, and the distance between the relative surfaces of the second source electrode 1124 and the second gate electrode 1121 is smaller than the distance between the first source electrode 1114 and the relative surfaces of the horizontal extension portion 11211.

[0160] For example, the surface of the second active layer 1122 away from the second gate electrode 1121 may be closer to the second gate electrode 1121 than the opening of the first hole 7, as shown in FIG. Figure 5a or, so that the surface of the second active layer 1122 away from the second gate electrode 1121 and the end of the second gate insulating layer away from the second gate electrode 1121 are closer to the second gate electrode 1121 than the opening of the first hole 7.

[0161] In a specific implementation, the distance between the second source electrode 1124 and the opposite surface of the second gate electrode 1121 and the distance between the first source electrode 1114 and the opposite surface of the horizontal extension portion 11211 can be adjusted according to actual needs.

[0162] In addition, if the channel length of the write transistor 111 is to be increased, the thickness of the insulating spacer between the write bit line 130 and the horizontal extension portion 11211 may be increased to increase the distance between the first source electrode 1114 and the horizontal extension portion 11211 .

[0163] In another embodiment, see Figure 5b and Fig.31 The read bit line 150 is formed as a whole with the second drain electrode 1125, and the second active layer 1122 is prepared in the fifth hole 17, by making the surface of the second active layer 1122 away from the second gate electrode 1121 closer to the second gate electrode 1121 than the opening of the fifth hole 17, that is, the second active layer 1122 only fills a partial depth of the fifth hole 17 from bottom to top.

[0164] Thus, the distance between the second drain electrode 1125 and the relative surface of the second gate electrode 1121 can be made smaller than the distance between the read bit line 150 and the relative surface of the second gate electrode 1121, thereby achieving independent adjustment of the channel length of the read transistor 112 while reducing the coupling between the read bit line 150 and the second gate electrode 1121.

[0165] For example, the surface of the second active layer 1122 away from the second gate electrode 1121 may be closer to the second gate electrode 1121 than the opening of the fifth hole 17, as shown in FIG. Figure 5b or, by making the second active layer 1122 away from the surface of the second gate electrode 1121 and the second gate insulating layer away from one end of the second gate electrode 1121, both are closer to the second gate electrode 1121 than the opening of the fifth hole 17.

[0166] In specific implementations, the distance between the second drain electrode 1125 and the opposite surface of the second gate electrode 1121 and the distance between the first source electrode 1114 and the opposite surface of the horizontal extension portion 11211 can be adjusted according to actual needs.

[0167] See also Figures 2a to 4 , Figures 14a to 15b , further, in the storage unit 110:

[0168] The first active layer 1112 overlaps with the orthographic projections of the first source electrode 1114 and the horizontal extension portion 11211 on the substrate 200, the first source electrode 1114 and the horizontal extension portion 11211 are connected to the first active layer 1112, and when the first source electrode 1114 and the write bit line 130 are formed as one body, the first active layer 1112 overlaps with the orthographic projections of the write bit line 130 and the horizontal extension portion 11211 on the substrate 200;

[0169] The second active layer 1122 overlaps with the orthographic projections of the second source electrode 1124 and the second drain electrode 1125 on the substrate 200, the second source electrode 1124 and the second drain electrode 1125 are connected to the second active layer 1122, and when the second source electrode 1124 and the read word line 140 are formed as one body, and the second drain electrode 1125 and the read bit line 150 are formed as one body, the orthographic projections of the second active layer 1122, the read word line 140, and the read bit line 150 on the substrate overlap;

[0170] At the same time, the structure formed by the second active layer 1122 and the second gate insulating layer 1123 overlaps with the orthographic projection of the second gate electrode 1211 on the substrate 200 , so that the second gate electrode 1121 is at least partially located at the periphery of the second active layer 1122 .

[0171] Optionally, the second active layer 1122 overlaps with an orthographic projection of the second gate electrode 1211 on the substrate 200 .

[0172] Preferably, the orthographic projection of the first active layer 1112 on the substrate 200 falls within the overlapping range of the orthographic projections of the first source electrode 1114 and the horizontal extension portion 11211 on the substrate 200, and the orthographic projection of the structure composed of the second active layer 1122 and the second gate insulating layer 1123 on the substrate 200 falls within the overlapping range of the orthographic projections of the second source electrode 1124, the second gate electrode 1121 and the second drain electrode 1125 on the substrate 200.

[0173] When the first source electrode 1114 is integrated with the write bit line 130, the second source electrode 1124 is integrated with the read word line 140, and the second drain electrode 1125 is integrated with the read bit line 150, the orthographic projection of the first active layer 1112 on the substrate 200 falls within the overlapping range of the orthographic projections of the write bit line 130 and the horizontal extension portion 11211 on the substrate 200, and the orthographic projection of the structure composed of the second active layer 1122 and the second gate insulating layer 1123 on the substrate 200 falls within the overlapping range of the orthographic projections of the read word line 140, the second gate electrode 1121 and the read bit line 150 on the substrate 200.

[0174] Please continue reading Figures 2a to 4 , Figures 12a to 12c , Fig.14a , Fig.14b and Figures 34a to 34c , further, in the orthographic projection on the substrate 200:

[0175] The second gate electrode 1121 is parallel to the two opposite sides in the extension direction of the read bit line 150 and overlaps with the two opposite sides of the read bit line 150; the second gate electrode 1121 overlaps with the write bit line 130 and the read word line 140, and the second gate electrode 1121 is located on the two opposite sides in the extension direction of the write bit line 130 and the read word line 140, and overlaps with the sides of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121 respectively.

[0176] It can be understood that in the process of preparing the second gate electrode 1211, the two sides of the second gate electrode 1211 extending along the X-axis direction can be prepared in the same patterning process as the two sides of the read bit line 150 extending along the X-axis direction. Therefore, in the orthographic projection on the substrate 200: the two opposite sides of the second gate electrode 1121 parallel to the extension direction of the read bit line 150 overlap with the two opposite sides of the read bit line 150.

[0177] Furthermore, the width of the second gate electrode 1121 in the Y-axis direction is equal to the width of the read bit line 150 .

[0178] Similarly, in the process of preparing the second gate electrode 1211, the two sides of the second gate electrode 1211 extending along the Y-axis direction can be prepared in the same patterning process as the two sides of the write bit line 130 and the read word line 140 that are far away from each other. Therefore, in the orthographic projection on the substrate 200: the second gate electrode 1121 is located on the two opposite sides in the extension direction of the write bit line 130 and the read word line 140, and overlaps with the sides of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121.

[0179] It is worth mentioning that the overlap mentioned above is not limited to complete overlap.

[0180] For example, during the preparation of the second gate electrode 1211, the two sides of the second gate electrode 1211 extending along the X-axis direction can be prepared in the same patterning process as the two opposite sides in the extension direction of the read bit line 150, and the two sides of the second gate electrode 1211 extending along the Y-axis direction can be prepared in the same patterning process as the two sides away from each other of the write bit line 130 and the read word line 140, but the second gate electrode 1121 and the read bit line 150, the write bit line 130 and the read word line 140 are in different layers, so there may be a certain error, but this error is within the overlap range, that is, the overlap includes complete overlap and approximate overlap.

[0181] Similarly, equal width also includes completely equal and approximately equal.

[0182] See also Figure 2a Figure 3a Furthermore, the first active layer 1112 is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion 11211 .

[0183] Among them, the groove-shaped structure can be understood as a U-shaped bottom structure, that is, the first active layer 1112 has a surface bottom that is in contact with the horizontal extension part 11211 with a large area, thereby realizing effective contact connection between the first active layer 1112 and the horizontal extension part 11211, and reducing the connection impedance between the first active layer 1112 and the horizontal extension part 11211; so that the bottom end of the groove-shaped structure is buried in the horizontal extension part 11211, which can further reduce the connection impedance and reduce the process difficulty of preparing the storage unit 100.

[0184] See also Figure 2b Figure 3b The first active layer 1112 is a cylindrical structure, and the end of the drain end of the first active layer 1112 of the cylindrical structure passes through the horizontal extension portion 11211. The cylindrical structure can be understood as a hollow bottomless structure.

[0185] Preferably, in the same storage device layer 100, all first active layers 1112 are groove-shaped structures or all are cylindrical structures to simplify the manufacturing process.

[0186] See also Figure 6 The memory device 1000 includes a plurality of memory device layers 100 which are vertically (along the Z-axis direction) stacked on a substrate 200 . The memory device 1000 also includes an insulating isolation layer 160 which is disposed between two adjacent memory device layers 100 .

[0187] Among them, the insulating isolation layer 160 is used to insulate and isolate adjacent storage device layers 100 to avoid short circuits between adjacent storage device layers 100. Adjacent storage device layers 100 can be independently controlled and independently read and write operations. The insulating isolation layer 160 can be made of insulating materials, such as silicon oxide SiO2, silicon nitride Si3N4, TEOS (tetraethoxysilane) or low dielectric constant materials. Therefore, by stacking multiple layers of storage device layers 100 in the vertical direction to form a storage device 1000, the storage density per unit area can be increased.

[0188] It should be noted that Figure 6 In the storage device 1000 shown in FIG. 1 , each storage device layer 100 includes Figure 3a The memory device layer 100 of the memory unit shown in FIG. 1 is a memory device layer 100, but the present invention is not limited thereto. The multiple memory device layers 100 in the memory device 1000 may all include the following: Figure 3a The memory device layer 100 of the memory cell shown in FIG. 1 may include: Figure 3b The memory device layer 100 of the memory cell shown in the figure, or part of the memory device layers 100 in the plurality of memory device layers 100 in the memory device 1000, includes the following: Figure 3a The memory device layer 100 of the memory cell shown in FIG. 1 and a portion of the memory device layer 100 includes Figure 3b The memory cell shown has a memory device layer 100 ; an insulating isolation layer 160 is disposed between two adjacent memory device layers 100 .

[0189] In different memory device layers 100 , the first horizontal directions may be the same or different, and the second horizontal directions may be the same or different.

[0190] See also Figures 7a to 9 In the embodiment shown, the storage device 1000 includes a multi-layer storage device layer 100, wherein the first active layer 1112 in at least one layer of the multi-layer storage device layer 100 is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or buries the horizontal extension portion 11211, that is, at least one layer of the storage device layer 100 includes the following: Figure 3aThe memory device layer 100 of the memory cell shown in the figure, and the first active layer 1112 in at least another layer of the multi-layer memory device layer 100 is a tubular structure, and the end of the tubular structure corresponding to the drain end of the first active layer 1112 passes through the horizontal extension portion 11211, that is, at least one memory device layer 100 includes Figure 3b The memory device layer 100 of the memory cell shown in the figure; the multiple memory device layers 100 are divided into at least one common unit 300 along the vertical direction, and the common unit 300 includes two memory device layers 100 adjacent to each other in the vertical direction. In the common unit 300, the two adjacent memory device layers 100 share the write word line 120, such as Figure 7a or two adjacent memory device layers 100 share a read bit line 150, such as Figure 7b shown.

[0191] Specifically, each shared unit 300 may include at least two memory cells 110 arranged in a mirror image in the vertical direction, and the two memory cells 110 share the same write word line 120 or read bit line 150. Compared with a memory structure in which the memory cells 110 are directly stacked in an array in the horizontal and vertical directions, the design of the shared unit 300 can reduce the setting of one layer of write word line 120 or read bit line 150 without affecting the storage density of the memory device 1000, thereby simplifying the structure of the memory device 1000, reducing the production cost, and further improving the storage density of the memory device 1000.

[0192] It is worth noting that although the two storage cells 110 in the shared unit 300 are mirror-imaged, the structures in the two storage cells 110 may not be exactly the same, but are only mirror-imaged in terms of "functional structure", that is, there are corresponding structures in the two storage cells 110, but the actual composition of the corresponding structures is not necessarily the same. For example, the structures of the first active layer 1112 in the two write transistors 111 may be different.

[0193] For example, Figure 7a , 7b As shown, the shared unit 300 includes adjacent memory device layers 100 sharing a write word line 120 or a write bit line 150, and one of the two adjacent memory device layers 100 includes: Figure 3a The memory device layer 100 of the memory cell shown in the figure has a groove-shaped first active layer 1112, and another memory device layer 100 includes Figure 3b The storage device layer 100 of the storage unit shown has a first active layer 1112 with a tubular structure. The end of the tubular structure corresponding to the drain end of the first active layer 1112 passes through the horizontal extension portion 11211. The two storage device layers 100 are arranged in mirror images of each other.

[0194] See also Figure 8Furthermore, the storage device 1000 further includes an insulating isolation layer 160, which is disposed between the common cell 300 and the storage device layer 100 adjacent to the common cell 300. For example, the common cells 300 are stacked vertically on the substrate 200 after being separated by the insulating isolation layer 160; for example, the common cells 300 and the storage device layer 100 are stacked vertically on the substrate 200 after being separated by the insulating isolation layer 160.

[0195] The insulating isolation layer 160 is used to insulate and isolate the common unit 300 and the storage device layer 100 adjacent to the common unit 300, so as to avoid short circuit between the storage device layer 100 in the common unit 300 and the storage device layer 100 adjacent to the common unit 300 located on both sides of the insulating isolation layer 160, and the storage device layer 100 in the common unit 300 and the storage device layer 100 adjacent to the common unit 300 can be independently controlled and read and write operations can be performed independently. The insulating isolation layer 160 can be made of insulating materials, such as silicon oxide SiO2, silicon nitride Si3N4, TEOS (tetraethoxysilane) or low dielectric constant materials.

[0196] In addition, since the write transistor 111 and the read transistor 112 need to be connected to the peripheral circuit to achieve read and write control, it is necessary to form an electrical connection between the peripheral circuit and the write transistor 111 and the read transistor 112, that is, it is necessary to form an electrical connection between the peripheral circuit and the write word line 120, the write bit line 130, the read word line 140 and the read bit line 150.

[0197] For example, the ends of the write word line 120, the write bit line 130, the read word line 140 and the read bit line 150 are formed into a step structure, and vertical through holes are prepared to connect to the step structure, so as to lead out the signal lines of the storage device 1000 (i.e., the write word line 120, the write bit line 130, the read word line 140 and the read bit line 150), which is convenient for the electrical connection of the peripheral circuit.

[0198] In some embodiments, the peripheral circuit is disposed in the semiconductor substrate 201 , but the present invention does not specifically limit this, and the location of the peripheral circuit can be specifically set according to actual needs.

[0199] See also Fig. 9 The shared cell 300 and the storage device layer 100 adjacent to the shared cell 300 share a write word line 120 or a read bit line 150, the shared cells 300 share a read bit line 150 and are vertically stacked on the substrate 200, and the shared cell 300 and the storage device layer 100 adjacent to the shared cell 300 share a read bit line 150 and are vertically stacked on the substrate 200.

[0200] In other embodiments, specifically, the shared cell 300 may include two storage cells 110 that are adjacent in the vertical direction and arranged in a mirror image, and the two storage cells 110 share a read bit line 150, while two storage cells 110 that are adjacent in the vertical direction and arranged in a mirror image and are respectively located in two adjacent shared cells 300 share a write word line 120, or two storage cells 110 that are respectively located in the shared cell 300 and in the storage device layer 100 adjacent to the shared cell 300 and are arranged in a mirror image and are respectively located in the write word line 120.

[0201] Compared to a storage structure in which the storage cells 110 are directly stacked in an array in the horizontal and vertical directions, the design of sharing the read bit line 150 or the write word line 120 between the shared cells 300 can reduce the setting of one layer of write word line 120 or read bit line 150 without affecting the storage density of the storage device 1000, thereby simplifying the structure of the storage device 1000, reducing the production cost, and further improving the storage density of the storage device 1000.

[0202] The method for preparing the storage device 1000 according to the embodiment of the present invention is used to prepare the storage device 1000 according to any one of the above items, and comprises the following steps:

[0203] Step S1: providing a first substrate 1.

[0204] Specifically, the first substrate 1 may be a temporary substrate or a substrate 200. The present invention does not specifically limit the material of the temporary substrate; if the first substrate 1 is the substrate 200, the substrate 200 here is the same as the substrate 200 in the storage device 1000 above, and the technical contents such as the material and structure thereof are not repeated here.

[0205] Step S2 : preparing at least one memory device layer 100 on the first surface 101 of the first substrate 1 .

[0206] That is, the memory device layer 100 in the memory device 1000 in the above embodiment is prepared on the above first substrate 1, and the detailed process will be described below. In some embodiments, the first substrate 1 is the substrate 200, and preparing at least one memory device layer 100 on the first substrate 1 includes preparing at least one memory device layer 100 on the insulating surface of the substrate 200, that is, on the surface of the insulating layer 202 away from the semiconductor substrate 201.

[0207] Step S3 : the first substrate 1 is the substrate 200 in the above embodiment, the first surface 101 is the insulating surface of the substrate 200 , or the memory device layer 100 formed in step S2 is transferred to the insulating surface of the substrate 200 .

[0208] That is, the memory device layer 100 can be prepared on the substrate 200, or transferred onto the substrate 200 after forming a temporary substrate (i.e., the first substrate 1 as a temporary substrate). In some embodiments, transferring the memory device layer 100 formed in step S2 to the insulating surface of the substrate 200 includes transferring the memory device layer 100 to the insulating layer 202 of the substrate 200. The transfer method exemplarily includes bonding, and the present invention does not specifically limit the transfer method.

[0209] See also Fig.10 Furthermore, the step S2 of preparing at least one storage device layer 100 on the first surface 101 may specifically include preparing at least one first storage device layer 100 on the first surface 101. The preparing at least one first storage device layer 100 may specifically include the following steps:

[0210] See also Figure 11 to Figure 12c ( Figure 12b for Fig.12a The cross-section view along the AA direction. Fig.12c for Fig.12a Step S21: sequentially prepare a first conductor layer 2, a first insulating layer 3, and a second conductor layer 4 on the first surface 101, perform a first patterning process to form a first gap penetrating the second conductor layer 4, the first insulating layer 3, and the first conductor layer 2 to form a read bit line 150, a second drain electrode 1125, and a first patterned conductor layer 5, prepare a first isolation insulating layer 6, and the first isolation insulating layer 6 covers the upper surface of the first patterned conductor layer 5.

[0211] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes directly preparing the first conductor layer on the first surface 101 .

[0212] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes, after preparing at least one storage device layer 100 on the first surface 101 of the first substrate 1, preparing an insulating isolation layer 160 on the top surface of the storage device layer 100, and then preparing the first conductor layer 2 on the surface of the insulating isolation layer 160 away from the first substrate 1.

[0213] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing at least one memory device layer 100 on the first surface 101 of the first substrate 1 , and preparing a conductor layer where the read bit line 150 of the topmost memory device layer 100 is located.

[0214] The first conductor layer 2 and the second conductor layer 4 may include layers of materials such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a stack of layers of the above materials, or a layer formed by any combination of the above materials, or a stack of layers formed by any combination of the above materials. The materials of the first conductor layer 2 and the second conductor layer 4 may be the same or different.

[0215] The material of the first insulating layer 3 can be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material or a combination of the above materials, a stacked material, or a combined stacked material.

[0216] In some embodiments, the first conductor layer 2, the first insulating layer 3 and the second conductor layer 4 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). It is understood that any suitable material and deposition process may be used to form the first insulating layer 3, the first conductor layer and the second conductor layer 4.

[0217] In an embodiment of the present invention, the first patterning process includes etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching.

[0218] See also Figure 12b and Fig.12c , the extension direction of the first slit is the X-axis direction, so that the first conductor layer 2 and the second conductor layer 4 are divided by the first slit into a plurality of read bit lines 150 and a first patterned conductor layer 5 in strips extending along the X-axis direction, the plurality of read bit lines 150 and the plurality of first patterned conductor layers 5 are spaced apart on their respective layers along the Y-axis direction, the first patterned conductor layer 5 is used to subsequently form the second gate electrode 1121, in the orthographic projection on the first substrate 1, the first patterned conductor layer 5 is parallel to the opposite sides of the read bit line 150 in the extension direction and overlaps the opposite sides of the read bit line 150. It can be understood that the second drain electrode 1125 is a part of the read bit line 150.

[0219] In one embodiment, the first isolation insulating layer 6 may be formed on the upper surface of the first patterned conductive layer 5 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0220] The material of the first isolation insulating layer 6 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material or a combination of the above materials, a stacked material, or a combined stacked material.

[0221] In an embodiment of the present invention, the first isolation insulating layer 6 covers the upper surface of the first patterned conductor layer 5, and its thickness can be adjusted to adjust the distance between the subsequently formed second gate electrode 1121 and the write bit line 130, thereby adjusting the channel length of the subsequently formed write transistor to meet different electrical requirements for the write transistor.

[0222] In some embodiments, the first isolation insulating layer 6 fills the first gap to improve the structural stability of the memory device layer 100 .

[0223] In some embodiments, the first isolation insulating layer 6 does not fill up the first gap, so that an air gap (not shown) is formed in the first gap, which reduces the crosstalk between adjacent conductors in the memory device layer 100 .

[0224] It can be understood that the top of the air gap is lower than the upper surface of the first isolation insulating layer 6, so as to facilitate the subsequent process steps. Preferably, the upper surface of the first isolation insulating layer 6 is flat.

[0225] See also Fig.13a and Fig.13b ( Fig.13b for Fig.13a Step S22: forming a first hole 7 penetrating the first isolation insulating layer 6, the first patterned conductor layer 5 and the first insulating layer 3, and forming a second gate insulating layer 1123 and a second active layer 1122 on the sidewalls of the first hole 7 in sequence.

[0226] The first hole 7 is used to accommodate the second gate insulating layer 1123 and the second active layer 1122 of the read transistor 112 , and the first hole 7 can be formed by an etching process, such as dry etching, wet etching or a combination of dry etching and wet etching.

[0227] Optionally, the first hole 7 is partially sunken into the upper surface of the read bit line 150 , which can reduce the difficulty of the etching process and reduce the contact resistance between the drain terminal of the read transistor and the second drain electrode 1125 .

[0228] After forming the first hole 7, an insulating material is first deposited on the bottom wall and side wall of the first hole 7 to form a second gate insulating layer 1123. The deposition method may be chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD), and the present invention does not make any specific limitation.

[0229] In the embodiment of the present invention, the insulating material used for the second gate insulating layer 1123 may include silicon oxide, silicon nitride, TEOS or a high dielectric constant material, etc., which is not specifically limited in the present invention.

[0230] Afterwards, the insulating material on the bottom wall of the first hole 7 (i.e., the upper surface of the read bit line 150) is removed, and a semiconductor material is deposited on the surface of the second gate insulating layer 1123 to form a second active layer 1122. The second active layer 1122 is electrically connected to the read bit line 150, and the second drain electrode 1125 includes the portion of the read bit line 150 opposite to the second active layer 1122.

[0231] In some embodiments, the second active layer 1122 and the second drain electrode 1125 are in direct contact to form an electrical connection. In other embodiments, another conductor layer or a doped semiconductor layer is provided between the second active layer 1122 and the second drain electrode 1125, which is not specifically limited in the present invention.

[0232] The deposition method may be chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). In some embodiments, after depositing the semiconductor material to form the second active layer 1122, the step further includes removing the portion of the semiconductor material layer outside the first hole 7.

[0233] The material of the second active layer 1122 includes an oxide semiconductor, such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, zinc oxide ZnO, and indium zinc oxide IZO.

[0234] In the embodiment of the present invention, the material of the second active layer 1122 is indium gallium zinc oxide (IGZO).

[0235] In some embodiments, the second active layer 1122 is a hollow structure, such as a groove or tube structure. After the second active layer 1122 is formed, an insulating material is deposited in the hollow of the second active layer 1122 to fill it, thereby forming a dielectric layer in the hollow. The dielectric layer is the same as before and will not be repeated here.

[0236] See also Fig.14a , Fig.14b and Fig.14c ( Fig.14b for Fig.14a Cross-section along the DD direction, Fig.14c for Fig.14aEE cross-sectional view), step S23: prepare a third conductor layer on the upper surface of the first isolation insulating layer 6, perform a second patterning process to form a second gap penetrating the third conductor layer, and a third gap penetrating the third conductor layer, the first isolation insulating layer 6, and the first patterned conductor layer 5 to form a second gate electrode 1121, a write bit line 130, a read word line 140, a first source electrode 1114, and a second source electrode 1124, and prepare a second isolation insulating layer 9, and the second isolation insulating layer 9 covers the upper surface of the first source electrode 1114.

[0237] Among them, the material of the third conductor layer can be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt and other materials, or a stack of layers of the above materials, or a layer formed by any combination of the above materials, or a stack of layers formed by any combination of the above materials. The material of the third conductor layer can be the same as or different from any of the first conductor layer 2 and the second conductor layer 4.

[0238] In one embodiment, the third conductor layer can be formed on the upper surface of the first isolation insulating layer 6 by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. It is understood that any suitable material and deposition process can be used to prepare the third conductor layer.

[0239] In an embodiment of the present invention, the second patterning process may be etching, such as dry etching, wet etching, or a combination of dry etching and wet etching. The second patterning process forms a second gap and a third gap, and the second gap and the third gap have different depths and penetrate different film layers. The second patterning process may be performed in two etchings, or the second patterning process may be performed in one etching by combining a grayscale mask or a stacked mask, which is not specifically limited in the present invention.

[0240] By way of example, the second patterning process can be divided into two etchings, including the first etching to form the second gap or the third gap, filling the second gap or the third gap with an insulating material layer, the second etching to form the third gap or the second gap, filling the third gap or the second gap with an insulating material layer, and the insulating material layer forms a part of the second isolation insulating layer 9.

[0241] See also Fig.14a and Fig.14b The second gap extends in the Y-axis direction and penetrates the third conductor layer. Figures 14a to 14cThe third slit extends in the Y-axis direction and penetrates the third conductor layer, the first isolation insulating layer 6 and the first patterned conductor layer 5. The second slit and the third slit divide the third conductor layer into strip-shaped write bit lines 130 and read word lines 140 extending in the Y-axis direction and spaced apart in the X-axis direction; the third slit also divides the first patterned conductor layer 5 into a plurality of second gate electrodes 1121.

[0242] In addition, in the orthographic projection on the substrate 200: the two opposite sides of the second gate electrode 1121 parallel to the extension direction of the read bit line 150 overlap with the two opposite sides of the read bit line 150, and the two opposite sides of the second gate electrode 1121 parallel to the extension direction of the write bit line 130 and the read word line 140 overlap with the sides of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121, respectively.

[0243] Preferably, the second gap extends to a partial depth of the first isolation insulating layer 6, and the third gap extends to a partial depth of the first insulating layer 3, so as to improve the reliability of the third conductor layer and the first patterned conductor layer 5 being patterned to be disconnected, while reducing the difficulty of the etching process.

[0244] The second gate electrode 1121 is located at the lower layer of the write bit line 130 and the read word line 140, and a plurality of second gate electrodes 1121 are distributed in an array on the X axis and the Y axis. The first source electrode 1114 and the second source electrode 1124 are located on the write bit line 130 and the read word line 140, respectively, and are a part of the write bit line 130 and the read word line 140.

[0245] At this time, the second active layer 1122 , the second gate insulating layer 1123 , the second gate electrode 1121 , the second source electrode 1124 and the second drain electrode 1125 together constitute the read transistor 112 .

[0246] In one embodiment, the second isolation insulating layer 9 covering the upper surface of the first source electrode 1114 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0247] Among them, the material of the second isolation insulating layer 9 can be silicon oxide SiOx, silicon nitride SiNx, TEOS, low dielectric constant materials, etc., or a combination of the above materials, a laminated material, or a combined laminated material. In some embodiments, the second isolation insulating layer 9 does not fill the second gap, so that an air gap (not shown) is formed in the second gap to reduce the crosstalk between adjacent conductors in the memory device layer 100. It can be understood that the top of the air gap is lower than the upper surface of the second isolation insulating layer 9 to facilitate the subsequent process steps. Preferably, the upper surface of the second isolation insulating layer 9 is flat.

[0248] See also Fig.15a and Fig.15b ( Fig.15b for Fig.15a Step S24: forming a second hole 10 penetrating the second isolation insulating layer 9, the first source electrode 1114 and the first isolation insulating layer 6, and forming a first active layer 1112, a first gate insulating layer 1113 and a first gate electrode 1111 in sequence on the sidewalls of the second hole 10.

[0249] The second hole 10 is used to accommodate the first active layer 1112, the first gate insulating layer 1113 and the first gate electrode 1111 of the write transistor 111. The second hole 10 can be formed by an etching process, such as dry etching, wet etching or a combination of dry etching and wet etching. The depth of the second hole 10 at least reaches the second gate electrode 1121.

[0250] Preferably, the second hole 10 is sunken to a partial depth of the second gate electrode 1121 to increase the contact area between the drain end of the first active layer 1112 and the second gate electrode 1121, reduce the connection impedance between the drain end of the first active layer 1112 and the second gate electrode 1121, and reduce the difficulty of the etching process of the second hole 10.

[0251] After forming the second hole 10, a first active layer 1112, a first gate insulating layer 1113 and a first gate electrode 1111 are sequentially deposited on the sidewall of the second hole 10, and the deposition method can be chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) and other deposition methods.

[0252] For example, a semiconductor material layer is deposited in the second hole 10, a portion of the semiconductor material layer outside the second hole 10 is removed to form a first active layer 1112, an insulating material layer and a conductive material layer are sequentially deposited in the second hole 10, a patterning process is performed to form a first gate insulating layer 1113 and a first gate electrode 1111, an insulating material layer is deposited and a planarization process is performed so that the first gate electrode 1111 is exposed, and the remaining insulating material layer is formed as a portion of the second insulating isolation layer 9, to obtain the following: Fig.15a The structure shown.

[0253] The material of the first active layer 1112 may include an oxide semiconductor, such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, zinc oxide ZnO, and indium zinc oxide IZO.

[0254] In the embodiment of the present invention, the material of the first active layer 1112 is indium gallium zinc oxide (IGZO).

[0255] In the embodiment of the present invention, the material of the first gate insulating layer 1113 may be silicon oxide, silicon nitride, TEOS or a high dielectric constant material, etc., which is not specifically limited in the present invention.

[0256] In an embodiment of the present invention, the material of the first gate electrode 1111 may be a conductive material, such as a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide (ITO), indium zinc oxide (IZO), copper Cu, ruthenium Ru, silver Ag, platinum Pt or the like, or a stack of layers of the above materials, or a layer formed by any combination of the above materials, or a stack of layers formed by any combination of the above materials.

[0257] At this time, the first active layer 1112 is electrically connected to the write bit line 130 and the second gate electrode 1211 , and the first source electrode 1114 includes a portion of the write bit line 130 that is opposite to the first active layer 1112 .

[0258] In some embodiments, the first active layer 1112 and the first source electrode 1114 are in direct contact with each other to form an electrical connection.

[0259] In other embodiments, other conductor layers or doped semiconductor layers are disposed between the first active layer 1112 and the first source electrode 1114 , which is not specifically limited in the present invention.

[0260] In some embodiments, the first active layer 1112 and the second gate electrode 1211 are in direct contact with each other to form an electrical connection.

[0261] In other embodiments, other conductor layers or doped semiconductor layers are disposed between the first active layer 1112 and the second gate electrode 1211 , which is not specifically limited in the present invention.

[0262] In the embodiment of the present invention, the first gate electrode 1111 , the first gate insulating layer 1113 , the first active layer 1112 and the first source electrode 1114 together constitute the write transistor 111 .

[0263] like Fig.15a As shown, the first gate insulating layer 1113 and the first active layer 1112 are a groove structure with a bottom, so that the first active layer 1112 and the horizontal extension portion 11211 have a larger contact area and a smaller contact impedance.

[0264] In some embodiments, the first gate insulating layer 1113 and the first active layer 1112 are bottomless cylindrical structures, so that the first gate insulating layer 1113 is located between the first active layer 1112 and the first gate electrode 1111 and between the first gate electrode 1111 and the second gate electrode 1121 for insulation.

[0265] In some embodiments, the first gate electrode 1111 is a hollow structure, such as a groove or tube structure. After forming the second active layer 1122, an insulating material is deposited in the hollow of the first gate electrode 1111 to fill it, thereby forming a dielectric layer in the hollow. The dielectric layer is the same as before and will not be repeated here.

[0266] See also Fig.16a and Fig.16b ( Fig.16b for Fig.16a Step S25: preparing a fourth conductor layer and performing a third patterning process on the fourth conductor layer to form a write word line 120, and the write word line 120 is isolated from the read word line 140.

[0267] The material of the fourth conductor layer may be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt or the like, or a stack of layers of the above materials, or a layer formed by any combination of the above materials, or a stack of layers formed by any combination of the above materials. The material of the fourth conductor layer may be the same as or different from that of the other conductor layers.

[0268] In one embodiment, the fourth conductor layer can be formed on the upper surface of the first isolation insulating layer 6 by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. It is understood that any suitable material and deposition process can be used to prepare the fourth conductor layer.

[0269] In an embodiment of the present invention, the third patterning process may be etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching. Fig.16b , the fourth conductor layer is etched by the third patterning process to form a strip-shaped write word line 120 extending along the X-axis direction, and a plurality of write word lines 120 are distributed at intervals along the Y-axis direction. Optionally, after the fourth conductor layer is etched by the third patterning process to form the write word line 120, there is also a step of: preparing an insulating isolation layer 160, and the insulating isolation layer 160 is at least filled between adjacent write word lines 120.

[0270] Furthermore, in step S22, sequentially forming the second gate insulating layer 1123 and the second active layer 1122 on the sidewall of the first hole 7 includes the following steps:

[0271] Step S221: deposit a second gate insulating layer 1123 material, the second gate insulating layer 1123 material covers the upper surface of the first isolation insulating layer 6, the side walls and the bottom surface of the first hole 7, and anisotropically etch to remove the second gate insulating layer 1123 material located on the upper surface of the first isolation insulating layer 6 and the bottom surface of the first hole 7, thereby forming a second gate insulating layer 1123 located on the side walls of the first hole 7.

[0272] Specifically, the second active layer 1122 in the embodiment of the present invention is formed in the inner wall of the second gate insulating layer 1123. Therefore, it is necessary to first prepare the second gate insulating layer 1123 into a cylindrical structure, and then it is necessary to remove the second gate insulating layer 1123 deposited on the bottom surface of the first hole 7. The removal process is anisotropic etching. Preferably, the second gate insulating layer 1123 deposited on the bottom surface of the first hole 7 is removed while removing the second gate insulating layer 1123 deposited on the upper surface of the first isolation insulating layer 6. After the removal is completed, the second gate insulating layer 1123 formed on the side wall of the first hole 7 is a cylindrical structure.

[0273] The detailed deposition process and the material of the second gate insulating layer 1123 may refer to the description in step S2 above, which will not be elaborated here.

[0274] Step S222: Fill the second active layer 1122 material in the groove surrounded by the side wall of the second gate insulating layer 1123 and the bottom surface of the first hole 7, and etch the second active layer 1122 material back until the top surface of the second active layer 1122 material is lower than the upper surface of the first isolation insulating layer 6 to form the second active layer 1122.

[0275] After the cylindrical second gate insulating layer 1123 is prepared, the second active layer 1122 material is deposited and filled in the space surrounded by the second gate insulating layer 1123. At this time, the second active layer 1122 material is etched back to the top surface of which is lower than the upper surface of the first isolation insulating layer 6, and the second active layer 1122 material is prepared. Figure 5a The second active layer 1122 of the illustrated embodiment can thus adjust the channel length of the read transistor 112 according to the depth of the etch back.

[0276] In some embodiments, the second gate insulating layer 1123 is also etched back while the second active layer 1122 is etched back, so that the top surfaces of the formed second gate insulating layer 1123 and the second active layer 1122 are lower than the upper surface of the first isolation insulating layer 6 .

[0277] The material of the second active layer 1122 can refer to the description in step S2 above, and will not be elaborated here.

[0278] See also Fig.17Furthermore, the step S2 of preparing at least one storage device layer 100 on the first surface 101 may specifically include preparing at least one first storage device layer 100 on the first surface 101, and preparing at least one first storage device layer 100 specifically includes the following steps:

[0279] See also Figure 18 to Figure 23b , step S26: prepare a first conductor layer 2 and perform a first patterning process on the first conductor layer 2 to form a write word line 120, prepare a first insulating layer 3 to cover the write word line 120, prepare a second conductor layer 4 on the surface of the first insulating layer 3 away from the write word line 120, and perform a second patterning process to form a write bit line 130, a read word line 140, a first source electrode 1114 and a second source electrode 1124, and prepare a first isolation insulating layer 6 to cover the write bit line 130, the read word line 140, the first source electrode 1114 and the second source electrode 1124.

[0280] For example, preparing the first conductor layer 2 includes preparing the first conductor layer 2 on the first surface 101 of the first substrate 1, such as Fig.18 As shown, this embodiment takes this as an example to simplify the description.

[0281] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes directly preparing the first conductor layer on the first surface 101 .

[0282] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes, after preparing at least one storage device layer 100 on the first surface 101 of the first substrate 1, preparing an insulating isolation layer 160 on the top surface of the storage device layer 100, and then preparing the first conductor layer 2 on the surface of the insulating isolation layer 160 away from the first substrate 1.

[0283] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes: preparing at least one storage device layer 100 on the first surface 101 of the first substrate 1 , and preparing a conductor layer where the write word line 120 of the topmost storage device layer 100 is located.

[0284] Among them, the materials of the first conductor layer 2 and the second conductor layer 4 can be layers of materials such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or stacks of layers of the above materials, or layers formed by any combination of the above materials, or stacks of layers formed by any combination of the above materials.

[0285] The material of the first insulating layer 3 can be silicon oxide SiOx, silicon nitride SiNx, TEOS, low dielectric constant materials, or a combination of the above materials, a stacked material, or a combined stacked material. There are gaps between adjacent write word lines 120. In some embodiments, the first insulating layer 3 fills the gaps to improve the structural stability of the memory device layer 100.

[0286] In some embodiments, the first insulating layer 3 does not fill the gap, so that an air gap (not shown) is formed in the gap to reduce the crosstalk between adjacent conductors in the memory device layer 100. It can be understood that the top of the air gap is lower than the upper surface of the first insulating layer 3 to facilitate the subsequent process steps. Preferably, the upper surface of the first insulating layer 3 is flat.

[0287] In one embodiment, the first insulating layer 3 , the first conductive layer 2 and the second conductive layer 4 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0288] It can be understood that any suitable material and deposition process can be used to form the first insulating layer 3, the first conductor layer 2 and the second conductor layer 4 respectively, and the materials of the first conductor layer 2 and the second conductor layer 4 can be the same or different.

[0289] In the embodiment of the present invention, the first patterning process and the second patterning process may be etching, such as dry etching, wet etching or an etching process combining dry etching and wet etching.

[0290] like Fig.20b ( Fig.20b for Fig.20a As shown in the cross-sectional schematic diagram along the HH direction, the first conductor layer 2 is divided into a plurality of write word lines 120 in strip shape extending along the X-axis direction through the first patterning process, and the plurality of write word lines 120 are distributed at intervals along the Y-axis direction.

[0291] like Figure 23b ( Figure 23b for Fig.23a As shown in the cross-sectional schematic diagram along the II direction in the middle, the second conductor layer 4 is divided into a plurality of write bit lines 130 and read bit lines 150 in strips extending along the Y-axis direction through the second patterning process, and the plurality of write bit lines 130 and read bit lines 150 are spaced apart along the X-axis direction. The first source electrode 1114 is located on the write bit line 130 and is a part of the write bit line 130. The second source electrode 1124 is located on the read word line 140 and is a part of the read word line 140.

[0292] In one embodiment, the first isolation insulating layer 6 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0293] The material of the first isolation insulating layer 6 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material or a combination of the above materials, a stacked material, or a combined stacked material.

[0294] There is a gap between any adjacent write bit lines 130 and read bit lines 150 . In some embodiments, the first isolation insulating layer 6 fills the gap to improve the structural stability of the storage device layer 100 .

[0295] In some embodiments, the first isolation insulating layer 6 does not fill the gap, so that an air gap (not shown) is formed in the gap to reduce the crosstalk between adjacent conductors in the memory device layer 100. It can be understood that the top of the air gap is lower than the upper surface of the first isolation insulating layer 6 to facilitate the subsequent process steps. Preferably, the upper surface of the first isolation insulating layer 6 is flat.

[0296] See also Figure 24 to Figure 29b , step S27: preparing a third conductor layer 8 on a surface of the first isolation insulating layer 6 away from the write word line 120;

[0297] Performing a third patterning process on the third conductor layer 8 to form a second patterned conductor layer 12 , the second patterned conductor layer 12 overlapping with the orthographic projections of the first source electrode 1114 and the second source electrode 1124 on the first substrate 1 ;

[0298] A third hole 13 is formed through the second patterned conductor layer 12 or the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114, a first active layer 1112 is formed on the side wall of the third hole 13, a fourth hole 14 is formed from the upper surface of the second patterned conductor layer 12 or the third conductor layer 8 to extend through the bottom of the third hole 13 and expose the write word line 120, and a first gate insulating layer 1113 and a first gate electrode 1111 connected to the write word line 120 are sequentially formed on the side wall of the fourth hole 14.

[0299] It is worth mentioning that the order of the above-mentioned some steps in step S27 can be swapped, that is, the step of "performing a third patterning process on the third conductor layer 8 to form a second patterned conductor layer 12" and the step of "forming a third hole 13 to form a first gate electrode 1111" can be swapped. Therefore, the above preparation steps are written as "forming a third hole 13 penetrating the second patterned conductor layer 12 or the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114" and "forming a fourth hole 14 extending from the upper surface of the second patterned conductor layer 12 or the third conductor layer 8 to penetrate the bottom of the third hole 13 and expose the write word line 120."

[0300] If the order of the above two steps is swapped, that is, the step of forming the third hole 13 and the fourth hole 14 is before the step of forming the second patterned conductor layer 12, then the above preparation steps are actually "forming a third hole 13 penetrating the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114" and "forming a fourth hole 14 extending from the upper surface of the third conductor layer 8 to penetrating the bottom of the third hole 13 and exposing the write word line 120". If the preparation order currently provided above is used, the above preparation steps are actually "forming a third hole 13 penetrating the second patterned conductor layer 12, the first isolation insulating layer 6, and the first source electrode 1114" and "forming a fourth hole 14 extending from the upper surface of the second patterned conductor layer 12 to penetrating the bottom of the third hole 13 and exposing the write word line 120".

[0301] For ease of description, the following description will first be based on the step of forming the second patterned conductor layer 12 .

[0302] Among them, the material of the third conductor layer 8 can be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt and other materials, or a stack of layers of the above materials, or a layer formed by any combination of the above materials, or a stack of layers formed by any combination of the above materials. The material of the third conductor layer 8 can be the same as or different from any of the first conductor layer 2 and the second conductor layer 4.

[0303] In one embodiment, the third conductor layer 8 may be formed on the upper surface of the first isolation insulating layer 6 by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or other deposition methods.

[0304] It can be understood that any suitable material and deposition process can be used to prepare the third conductor layer 8 .

[0305] In the embodiment of the present invention, the third patterning process may be etching, such as dry etching, wet etching or an etching process combining dry etching and wet etching.

[0306] The second patterned conductor layer 12 is used to form a subsequent second gate electrode 1121 (including a horizontal extension portion 11211), so the second patterned conductor layer 12 overlaps with the orthographic projections of the first source electrode 1114 and the second source electrode 1124 on the first substrate 1, so that the subsequently formed second gate electrode 1121 can cover the area between the write bit line 130 and the read word line 140 in the orthographic projection. As a result, a vertical channel write transistor 111 and a read transistor can be prepared in subsequent process steps.

[0307] Optionally, after forming the second patterned conductor layer 12, a spacer insulating layer 15 is prepared, such as Fig.25 , Fig.29b ( Fig.29b for Fig.29a As shown in the cross-sectional schematic diagram along the JJ axis, the second patterned conductor layers 12 extend along the Y-axis direction and are arranged at intervals along the X-axis direction, and the spacing insulating layer 15 is at least filled between adjacent patterned conductor layers 12.

[0308] Among them, see Fig.26 The third hole 13 extends vertically downward from the surface of the second patterned conductor layer 12 to penetrate the first source electrode 1114, that is, the third hole 13 penetrates the second patterned conductor layer 12 and the write bit line 130. When the first active layer 1112 is deposited on the side wall of the third hole 13, the contact connection between the first active layer 1112 and the write word line 120 can be achieved, that is, the contact connection between the first active layer 1112 and the first source electrode 1114 can be achieved. Fig. 27 shown.

[0309] In the embodiment of the present invention, the third hole 13 can be formed by etching, such as dry etching, wet etching or a combination of dry etching and wet etching. Preferably, the third hole 13 extends to a partial depth of the first insulating layer 3 to reduce the difficulty of the etching process.

[0310] In the embodiment of the present invention, the first active layer 1112 is formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and the like.

[0311] Afterwards, etching is performed downward at the bottom of the first active layer 1112, that is, the bottom of the third hole 13, to form a fourth hole 14 penetrating downward to the surface of the write word line 120, so as to obtain Fig.28 In the structure shown in FIG. 1 , a first gate insulating layer 1113 and a first gate electrode 1111 are sequentially deposited in the fourth hole 14, and the first gate electrode 1111 can be directly connected to the write word line 120. Since the third hole 13 penetrates the write bit line 130 and the first gate insulating layer 1113 is prepared along the hole wall of the fourth hole 14, the first gate electrode 1111 and the write bit line 130 are prevented from being short-circuited. Fig.29a shown.

[0312] In the embodiment of the present invention, the fourth hole 14 may be formed by etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching.

[0313] In the embodiment of the present invention, the first gate insulating layer 1113 and the first gate electrode 1111 may be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like.

[0314] Among them, the material of the first gate insulating layer 1113 can be silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium oxide Y2O3 and other materials or a combination material, stacked material, or combined stacked material of the above materials, and can also be TEOS.

[0315] The material of the first gate electrode 1111 can be a conductive material, such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide (ITO), indium zinc oxide (IZO), copper Cu, ruthenium Ru, silver Ag, platinum Pt and the like, or any combination of the above materials.

[0316] In the embodiment of the present invention, the third hole 13 is used to accommodate the first gate electrode 1111, the first gate insulating layer 1113 and the first active layer 1112 of the write transistor 111, and the first gate electrode 1111, the first gate insulating layer 1113, the first active layer 1112 and the first source electrode 1114 constitute the write transistor 111.

[0317] See also Figure 30 to Figure 32 , step S28: forming a second insulating layer 16 covering the second patterned conductor layer 12 and the first gate electrode 1111, forming a fifth hole 17 penetrating the second insulating layer 16, the second patterned conductor layer 12, the first isolation insulating layer 6 and exposing the second source electrode 1124, and sequentially forming a second gate insulating layer 1123 and a second active layer 1122 connected to the second source electrode 1124 on the side walls of the fifth hole 17.

[0318] The second insulating layer 16 can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In some embodiments, the coupling between the read bit line 150 and the second gate electrode 1121 can be reduced by increasing the thickness of the second insulating layer 16.

[0319] The material of the second insulating layer 16 can be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination of the above materials, a stacked material, or a combined stacked material.

[0320] In the embodiment of the present invention, the fifth hole 17 is used to accommodate the second active layer 1122 and the second gate insulating layer 1123 of the read transistor 112. Preferably, the fifth hole 17 extends to a partial depth of the second source electrode 1124. The fifth hole 17 can be formed by etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching.

[0321] In the embodiment of the present invention, the second gate insulating layer 1123 and the second active layer 1122 can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. When the second active layer 1122 is deposited on the sidewall of the fifth hole 17, the second active layer 1122 can directly form a contact connection with the second source electrode 1124 at the bottom of the fifth hole 17.

[0322] The material of the second active layer 1122 includes an oxide semiconductor, such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, indium gallium tin oxide ITZO, and zinc oxide ZnO.

[0323] In the embodiment of the present invention, the material of the second active layer 1122 is indium gallium zinc oxide (IGZO).

[0324] Among them, the material of the second gate insulating layer 1123 can be silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium oxide Y2O3 and other materials or a combination material, stacked material, or combined stacked material of the above materials, and can also be TEOS.

[0325] See also Figure 33 to Figure 34c ( Fig.34b for Fig.34a Schematic diagram of the cross section along the KK axis. Fig.34c for Fig.34a Step S29: forming a fourth conductor layer 11 on the side of the second insulating layer 16 away from the write word line 120, and performing a third patterning process to form a fourth gap passing through the fourth conductor layer 11, the second insulating layer 16, and the second patterned conductor layer 12 to form a read bit line 150 and a second gate electrode 1121.

[0326] See also Figures 34a to 34c Optionally, an insulating isolation layer 160 is filled in the fourth gap.

[0327] The material of the fourth conductor layer 11 may be titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt or any combination thereof.

[0328] In one embodiment, the fourth conductor layer 11 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other deposition methods.

[0329] It can be understood that any suitable material and deposition process can be used to prepare the fourth conductor layer 11 .

[0330] In the embodiment of the present invention, the third patterning process may be etching, such as dry etching, wet etching or an etching process combining dry etching and wet etching.

[0331] The fourth slit formed by the third patterning process extends in the X-axis direction, dividing the fourth conductor layer 11 into a plurality of read bit lines 150 in a strip shape extending along the X-axis direction. Fig.34b As shown, the second patterned conductor layer 12 is divided into a plurality of second gate electrodes 1121, and the plurality of second gate electrodes 1121 are arranged in an array along the X and Y directions, as shown in FIG. Fig.34c shown.

[0332] In addition, in the orthographic projection on the substrate 200 , two opposite sides of the second gate electrode 1121 parallel to the extending direction of the read bit line 150 overlap with two opposite sides of the read bit line 150 .

[0333] The portion where the read bit line 150 is connected and in contact with the second gate electrode 1121 is the second drain electrode 1125 .

[0334] At this time, the second active layer 1122 , the second gate insulating layer 1123 , the second gate electrode 1121 , the second source electrode 1124 and the second drain electrode 1125 together constitute the read transistor 112 .

[0335] In some embodiments, the order of some steps in the above method can be reversed.

[0336] For example, see Fig.21, forming a second conductor layer 4, performing a patterning process so that the second conductor layer 4 is formed into a third patterned conductor layer, the third patterned conductor layer extends along the Y-axis direction, a fifth gap extending along the Y-axis direction is formed between adjacent third patterned conductor layers, a first isolation insulating layer 6 is formed to fill the fifth gap and cover the third patterned conductor layer, a third conductor layer 8 is formed above the first isolation insulating layer 6, performing patterning so that the third conductor layer 8 is formed into a second patterned conductor layer 12, a sixth gap is formed between adjacent second patterned conductor layers 12, the sixth gap extends along the Y-axis direction, and the sixth gap also penetrates the first isolation insulating layer 6 and the third patterned conductor layer, and the fifth gap and the sixth gap enable the second conductor layer 4 to be patterned to form a write bit line 130 and a read word line 140. Optionally, the spacer insulating layer 15 is filled in the sixth gap. Thus, the difficulty of the patterning process can be reduced.

[0337] In this embodiment, two opposite sides of the second gate electrode 1121 extending along the second horizontal direction overlap with sides of the write bit line 130 and the read word line 140 overlapping with the second gate electrode 1121 on the orthographic projection of the first substrate 1 .

[0338] Furthermore, in step S28, sequentially forming the second gate insulating layer 1123 and the second active layer 1122 connected to the second source electrode 1124 on the sidewall of the fifth hole 17 includes the following steps:

[0339] Step S281: deposit a second gate insulating layer 1123 material, the second gate insulating layer 1123 material covers the upper surface of the second insulating layer 16, the side walls and the bottom surface of the fifth hole 17, and anisotropically etch to remove the second gate insulating layer 1123 material located on the upper surface of the second insulating layer 16 and the bottom surface of the fifth hole 17, thereby forming a second gate insulating layer 1123 located on the side walls of the fifth hole 17.

[0340] Specifically, the second active layer 1122 in the embodiment of the present invention is formed in the inner wall of the second gate insulating layer 1123. Therefore, the second gate insulating layer 1123 needs to be prepared as a cylindrical structure first, and the second gate insulating layer 1123 deposited on the bottom surface of the fifth hole 17 needs to be removed. The removal process is anisotropic etching removal. Preferably, the second gate insulating layer 1123 deposited on the bottom surface of the fifth hole 17 is removed while the second gate insulating layer 1123 deposited on the upper surface of the first isolation insulating layer 6 is removed. The second gate insulating layer 1123 formed on the side wall of the fifth hole 17 after the removal is completed is a cylindrical structure.

[0341] The detailed deposition method and the material of the second gate insulating layer 1123 can refer to the description of step S2 above, which will not be repeated here. The advantages of the cylindrical second active layer 1122 have been described above, which will not be repeated here.

[0342] Step S282: Fill the groove surrounded by the side wall of the second gate insulating layer 1123 and the bottom surface of the fifth hole 17 with the second active layer 1122 material, and etch back the second active layer 1122 material until the top surface of the second active layer 1122 material is lower than the upper surface of the second insulating layer 16 to form the second active layer 1122.

[0343] After the cylindrical second gate insulating layer 1123 is prepared, the second active layer 1122 material is deposited and filled in the space surrounded by the second gate insulating layer 1123. At this time, the second active layer 1122 material is etched back to a position where the top surface is lower than the upper surface of the second insulating layer 16. Figure 5b The second active layer 1122 of the illustrated embodiment can thus adjust the channel length of the read transistor 112 according to the depth of the etch back.

[0344] In some embodiments, the second gate insulating layer 1123 is also etched back while the second active layer 1122 is etched back, so that the top surfaces of the formed second gate insulating layer 1123 and the second active layer 1122 are lower than the upper surface of the second insulating layer 16 .

[0345] The material of the second active layer 1122 can refer to the description in step S2 above, and will not be described in detail here. The advantages of the cylindrical second active layer 1122 have been described above, and will not be described in detail here.

[0346] See also Fig.35 The circuit diagram of the memory cell 110, the write word line 120, the write bit line 130, the read word line 140 and the read bit line 150 shown is connected:

[0347] The step of performing a write operation on the memory cell 110 provided in an embodiment of the present invention may include: applying a voltage to the write word line 120 to turn on the write transistor 111, and applying a voltage to the write bit line 130 to charge the storage node SN, so that the storage node SN presents a high voltage or a low voltage, representing data 1 and 0 respectively; optionally, in the process of performing a write operation on the storage node SN, no voltage is applied to the read word line 140;

[0348] The steps of performing a read operation on a storage cell 110 provided in an embodiment of the present invention may include: when reading "1", applying a voltage to a read word line 140 to provide a voltage signal to a second source electrode 1124 electrically connected to the read word line 140. Since a certain charge is stored in the storage node SN, a current flows between the read bit line 150 and the read word line 140, and the storage node SN is read by detecting the magnitude of the current in the read bit line 150; when reading "0", applying a read voltage to the read word line 140 in the read transistor. Since there is no charge in the storage node SN, no current flows or a small current flows between the read bit line 150 and the read word line 140, and no current can be read on the read bit line 150, that is, the reading process of data 0 is completed.

[0349] In the description of this specification, the description with reference to the terms "Example 1", "Example 2", etc. means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0350] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A storage device, characterized in that: include: a substrate comprising an insulating surface; and At least one memory device layer disposed on the insulating surface, the memory device layer comprising memory cells, write word lines, write bit lines, read word lines, and read bit lines; The memory cell includes a write transistor and a read transistor; The write transistor comprises a first gate electrode, a first active layer, a first gate insulating layer and a first source electrode, wherein the first gate electrode is vertically disposed on the substrate, the first active layer is disposed at least partially around the first gate electrode, the first gate insulating layer is disposed between the first gate electrode and the first active layer, and the first source electrode is connected to a source terminal of the first active layer; The read transistor includes a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode and a second drain electrode, the second active layer is vertically disposed on the substrate, the second gate electrode is disposed at least partially around the second active layer, the second gate insulating layer is disposed between the second gate electrode and the second active layer, the second source electrode is connected to the source terminal of the second active layer, and the second drain electrode is connected to the drain terminal of the second active layer; The second gate electrode further includes a horizontal extension portion, and the horizontal extension portion is connected to the drain terminal of the first active layer; The first gate electrode is connected to a write word line, the first source electrode is connected to a write bit line, the second source electrode is connected to a read word line, and the second drain electrode is connected to a read bit line; In the vertical direction, the write word line is located at a side of the first source electrode away from the horizontal extension portion.

2. The storage device according to claim 1, characterized in that The first source electrode and the write bit line connected thereto are formed as one body, the second source electrode and the read word line connected thereto are formed as one body, and the second drain electrode and the read bit line connected thereto are formed as one body.

3. The storage device according to claim 1 or 2, characterized in that: The memory device layer includes a plurality of memory cells, the plurality of memory cells are arranged in an array in a first horizontal direction and a second horizontal direction, and the first horizontal direction and the second horizontal direction intersect; A plurality of the write word lines and the read bit lines are provided, and the write word lines and the read bit lines are arranged at intervals in the second horizontal direction and extend along the first horizontal direction, the write word lines are connected to the first gate electrodes of the plurality of the write transistors arranged in the first horizontal direction, and the read bit lines are connected to the second drain electrodes of the plurality of the read transistors arranged in the first horizontal direction; The write bit lines and the read word lines are provided in plurality and are alternately spaced in the first horizontal direction and extend along the second horizontal direction. The write bit lines are connected to the first source electrodes of the plurality of write transistors arranged in the second horizontal direction, and the read word lines are connected to the second source electrodes of the plurality of read transistors arranged in the second horizontal direction.

4. The storage device according to claim 1 or 2, characterized in that: The second source electrode and the first source electrode are located in the same layer.

5. The storage device according to claim 1 or 2, characterized in that: In the vertical direction: The second source electrode and the first source electrode are located in the same layer, and a distance between the second source electrode and the opposing surface of the second gate electrode is smaller than a distance between the first source electrode and the opposing surface of the horizontal extension portion; or The second drain electrode is formed as a whole with the read bit line, and the distance between the second drain electrode and the opposite surface of the second gate electrode is smaller than the distance between the read bit line and the opposite surface of the second gate electrode.

6. The storage device according to claim 1 or 2, characterized in that: In the storage unit: The first active layer overlaps with the first source electrode and the orthographic projection of the horizontal extension portion on the substrate; The second active layer overlaps with the orthographic projections of the second source electrode, the second gate electrode, and the second drain electrode on the substrate.

7. The storage device according to claim 2, characterized in that: In the orthographic projection onto the substrate: The second gate electrode is parallel to two opposite sides of the extending direction of the read bit line, and overlaps with two opposite sides of the read bit line respectively.

8. The storage device according to claim 2, characterized in that: In the orthographic projection of the substrate: The second gate electrode overlaps with the write bit line and the read word line, and the second gate electrode is parallel to two opposite sides in the extension direction of the write bit line and the read word line, and overlaps with the sides of the write bit line and the read word line overlapping with the second gate electrode respectively.

9. The storage device according to claim 1, characterized in that: The first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion; or The first active layer is a tubular structure, and an end of the tubular structure corresponding to the drain end of the first active layer passes through the horizontal extension portion.

10. The storage device according to claim 1, characterized in that: The memory device comprises a plurality of memory device layers, wherein the plurality of memory device layers are vertically stacked on the substrate; The first active layer in at least one layer of the multi-layer memory device layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion; and the first active layer in at least another layer of the multi-layer memory device layer is a tubular structure, and the end of the tubular structure corresponding to the drain end of the first active layer passes through the horizontal extension portion.

11. The storage device according to claim 9 or 10, characterized in that: The memory device comprises a plurality of memory device layers, wherein the plurality of memory device layers are vertically stacked on the substrate; The storage device further comprises an insulating isolation layer, and the insulating isolation layer is arranged between two adjacent storage device layers.

12. The storage device according to claim 1, characterized in that: The memory device comprises a plurality of memory device layers, wherein the plurality of memory device layers are vertically stacked on the substrate; The plurality of memory device layers are divided into at least one common unit along the vertical direction, wherein the common unit includes two memory device layers adjacent to each other in the vertical direction; In the shared unit, the adjacent memory device layers share the write word line or the read bit line; And in one of the two adjacent memory device layers, the first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is buried in the horizontal extension portion of the one; In the other of the two adjacent memory device layers, the first active layer is a tubular structure, and an end of the tubular structure corresponding to a drain end of the first active layer passes through the horizontal extension portion.

13. The storage device according to claim 12, characterized in that: The memory device further includes an insulating isolation layer disposed between the common cell and the memory device layer adjacent to the common cell.

14. The storage device according to claim 1, characterized in that: The materials of the write word line, the write bit line, the read word line, the read bit line, the first gate electrode, the first source electrode, the second gate electrode, the second source electrode and the second drain electrode are the same or different and include conductors; The first active layer and the second active layer are made of the same or different materials and include oxide semiconductors.

15. The storage device according to claim 14, characterized in that: The conductor includes at least one of aluminum, titanium, tungsten, titanium nitride, and doped polysilicon; The oxide semiconductor includes at least one of indium oxide, tin oxide, gallium oxide, indium tin oxide, zinc oxide, indium zinc oxide, and indium gallium zinc oxide.

16. A method for preparing a storage device, for preparing the storage device according to any one of claims 1 to 15, characterized in that: The steps include: S1. Providing a first substrate; S2. Preparing at least one layer of the memory device layer on the first surface of the first substrate; S3. The first substrate is the substrate, and the first surface is the insulating surface, or the memory device layer formed in step S2 is transferred to the insulating surface of the substrate.

17. The preparation method according to claim 16, characterized in that: The step of preparing at least one storage device layer on the first surface includes preparing at least one first storage device layer, and the step of preparing at least one first storage device layer includes the following steps: S21. On the first surface, a first conductor layer, a first insulating layer, and a second conductor layer are sequentially prepared, and a first patterning process is performed to form a first gap penetrating the second conductor layer, the first insulating layer, and the first conductor layer to form the read bit line, the second drain electrode, and the first patterned conductor layer, and a first isolation insulating layer is prepared, wherein the first isolation insulating layer covers the upper surface of the first patterned conductor layer; S22. forming a first hole penetrating the first isolation insulating layer, the first patterned conductor layer and the first insulating layer, and sequentially forming the second gate insulating layer and the second active layer on the sidewall of the first hole; S23. Prepare a third conductor layer on the upper surface of the first isolation insulating layer, perform a second patterning process to form a second slit penetrating the third conductor layer, and a third slit penetrating the third conductor layer, the first isolation insulating layer, and the first patterned conductor layer to form the second gate electrode, the write bit line, the read word line, the first source electrode, and the second source electrode, and prepare a second isolation insulating layer, wherein the second isolation insulating layer covers the upper surface of the first source electrode; S24. forming a second hole penetrating the second isolation insulating layer, the first source electrode and the first isolation insulating layer, and sequentially forming the first active layer, the first gate insulating layer and the first gate electrode on the sidewall of the second hole; S25. Prepare a fourth conductor layer and perform a third patterning process on the fourth conductor layer to form the write word line, wherein the write word line is isolated from the read word line.

18. The preparation method according to claim 17, characterized in that: In the step S22, the step of sequentially forming the second gate insulating layer and the second active layer on the sidewall of the first hole comprises the following steps: S221. depositing a second gate insulating layer material, the second gate insulating layer material covering the upper surface of the first isolation insulating layer, the sidewall and the bottom surface of the first hole, and performing anisotropic etching to remove a portion of the second gate insulating layer material located on the upper surface of the first isolation insulating layer and the bottom surface of the first hole, to form a second gate insulating layer located on the sidewall of the first hole; S222. Fill the second active layer material in the groove surrounded by the side wall of the second gate insulating layer and the bottom surface of the first hole, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the first isolation insulating layer to form the second active layer.

19. The preparation method according to claim 16, characterized in that: The step of preparing at least one storage device layer on the first surface includes preparing at least one first storage device layer, and the step of preparing at least one first storage device layer also includes the following steps: S26. Prepare a first conductor layer and perform a first patterning process on the first conductor layer to form the write word line, prepare a first insulating layer to cover the write word line, prepare a second conductor layer on a surface of the first insulating layer away from the write word line and perform a second patterning process to form the write bit line, the read word line, the first source electrode and the second source electrode, prepare a first isolation insulating layer to cover the write bit line, the read word line, the first source electrode and the second source electrode; S27. Preparing a third conductor layer on a surface of the first isolation insulating layer away from the write word line; performing a third patterning process on the third conductor layer to form a second patterned conductor layer, the second patterned conductor layer overlapping with orthographic projections of the first source electrode and the second source electrode on the first substrate; forming a third hole penetrating the second patterned conductor layer or the third conductor layer, the first isolation insulating layer, and the first source electrode, forming the first active layer on the sidewall of the third hole, forming a fourth hole extending from the upper surface of the second patterned conductor layer or the third conductor layer to the bottom of the third hole and exposing the write word line, and sequentially forming the first gate insulating layer and the first gate electrode connected to the write word line on the sidewall of the fourth hole; S28. forming a second insulating layer covering the second patterned conductor layer and the first gate electrode, forming a fifth hole penetrating the second insulating layer, the second patterned conductor layer, the first isolation insulating layer and exposing the second source electrode, and sequentially forming the second gate insulating layer and the second active layer connected to the second source electrode on the sidewall of the fifth hole; S29. Form a fourth conductor layer on a side of the second insulating layer away from the write word line, and perform a third patterning process to form a fourth gap penetrating the fourth conductor layer, the second insulating layer, and the second patterned conductor layer to form the read bit line and the second gate electrode.

20. The preparation method according to claim 19, characterized in that: In the step S28, the step of sequentially forming the second gate insulating layer on the sidewall of the fifth hole and the second active layer connected to the second source electrode comprises the following steps: S281. depositing a second gate insulating layer material, the second gate insulating layer material covers the upper surface of the second insulating layer, the sidewalls and the bottom surface of the fifth hole, and performing anisotropic etching to remove a portion of the second gate insulating layer material located on the upper surface of the second insulating layer and the bottom surface of the fifth hole, to form a second gate insulating layer located on the sidewalls of the fourth hole; S282. Fill the second active layer material in the groove surrounded by the side wall of the second gate insulating layer and the bottom surface of the fifth hole, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the second insulating layer to form the second active layer.

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