Electronic package and fabrication method thereof
By designing an electronic package containing an electronic module integrating electronic components and a photonic component with interval settings, the problems of difficult reduction in the package substrate layout, difficult warping control and large insertion loss in the prior art are solved, and the size is reduced and efficient packaging structure.
Patent Information
- Application Number
- CN202311171089.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-18
- Filing Date
- 2023-09-12
- Publication Date
- 2025-02-21
AI Technical Summary
In existing semiconductor packages, the adjacent arrangement of the conversion chip and the optical engine module leads to the difficulty of reducing the area of the package substrate, warping control is difficult, and high-speed calculations can easily cause large insertion loss, and external optical fibers of the photonic chip are easily interfered with the package substrate. .
Design an electronic package, including a load-bearing structure, an electronic module and a photonic component. The electronic module connects the bearing structure through the first connection area, and makes the second connection area protrude the bearing structure, and the photonic element is connected to the second connection area of the electronic module, and is spaced from the bearing structure.
By integrating multiple electronic components into the electronic module and keeping the photonic components and the bearing structure spaced, the problem of difficult reduction in the area of the package substrate and difficult warping control is solved, the insertion loss is reduced, and the photonic chip and the package substrate are avoided interference.
Smart Images
Figure CN119493222A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device, in particular to an electronic package with a photonic element and a manufacturing method thereof. Background Art
[0002] In response to the huge demand for data transmission, silicon photonics (CPO. Co-Package Optic) packaging has become an inevitable development trend.
[0003] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a conventional semiconductor package 1 having a photonic element. Figure 1 As shown, a switch die 12 and a light engine module 1a are disposed on a packaging substrate 18. The light engine module 1a comprises a cladding layer 15, an electronic integrated circuit (EIC) chip 11 and a plurality of conductive pillars 13 embedded in the cladding layer 15, a circuit structure 10 disposed on the upper side of the cladding layer 15, a wiring structure 14 disposed on the lower side of the cladding layer 15, and a photon chip (Photo IC) 16 disposed on the circuit structure 10, so that the light engine module 1a is disposed on the packaging substrate 18 with its wiring structure 14 through a plurality of solder balls 17, and the light engine module 1a is externally connected to an optical fiber 50 with its photon chip 16. In addition, a plurality of solder balls 19 may be disposed on the lower side of the packaging substrate 18.
[0004] However, in the existing semiconductor package 1, the conversion chip 12 and the light engine module 1a are arranged adjacent to each other on the layout of the package substrate 18, occupying a large layout area of the package substrate 18, resulting in problems such as difficulty in reducing the layout area of the package substrate 18 and difficulty in controlling warpage. In addition, the conversion chip 12 is spaced far apart from the light engine module 1a, which can easily cause large insertion loss under high-speed computing. In addition, since the photonic chip 16 needs to be connected to an external optical fiber 50, if the position of the photonic chip 16 is not well designed, interference with the package substrate 18 will occur.
[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention
[0006] In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can at least partially solve the problems of the prior art.
[0007] The electronic package of the present invention comprises: a supporting structure; an electronic module, which defines a first connection area and a second connection area separated from each other, the electronic module is connected to the supporting structure by the first connection area, and the second connection area protrudes from the supporting structure; and a photonic element, which is connected to the second connection area of the electronic module and maintains a spacing with the supporting structure.
[0008] The present invention also provides a method for manufacturing an electronic package, comprising: providing an electronic module, which defines a first connection area and a second connection area that are separated from each other; electrically connecting a photonic element to the second connection area of the electronic module; and connecting the first connection area of the electronic module to a supporting structure, and making the second connection area protrude from the supporting structure to maintain a spacing between the photonic element and the supporting structure.
[0009] In the aforementioned electronic packaging component and its manufacturing method, the photonic element is externally connected to an optical fiber.
[0010] In the aforementioned electronic package and its manufacturing method, the electronic module is electrically connected to the supporting structure through a plurality of first conductive elements disposed on the first connection area, and is electrically connected to the photonic element through a plurality of second conductive elements disposed on the second connection area.
[0011] In the aforementioned electronic package and the manufacturing method thereof, the size of the first conductive element located in the first connection area is greater than the size of the second conductive element located in the second connection area.
[0012] In the aforementioned electronic package and its manufacturing method, the interval between the supporting structure and the photonic element is at least 100 um.
[0013] In the aforementioned electronic package and its manufacturing method, the supporting structure has a concave portion, and the photonic element is disposed in the concave portion of the supporting structure.
[0014] In the aforementioned electronic package and its manufacturing method, the electronic module includes a plurality of electronic components.
[0015] In the aforementioned electronic package and its manufacturing method, the plurality of electronic components include a memory chip, an electronic integrated circuit chip and a conversion chip.
[0016] In the aforementioned electronic package and its manufacturing method, the electronic module further comprises a packaging layer covering the plurality of electronic components.
[0017] In the aforementioned electronic package and its manufacturing method, in the electronic module, the distances between the side end surfaces of the plurality of electronic components and the side surfaces of the adjacent packaging layers are different.
[0018] As can be seen from the above, the electronic package and the manufacturing method of the present invention are mainly achieved by integrating multiple electronic components into the electronic module, overlapping the electronic module with the photon component, and making the electronic module connected to the bearing structure with the first connection area so as to partially protrude from the bearing structure, and arranging the photon component in the protruding second connection area of the electronic module. Thus, it is convenient to join the photon component without interfering with the bearing structure, and the layout area of the bearing structure can be reduced to meet the requirements of miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package with a photonic element.
[0020] Figures 2A to 2G It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.
[0021] Figure 2H FIG. 4 is a cross-sectional schematic diagram of another embodiment of the electronic package of the present invention.
[0022] Figure 3 FIG. 4 is a bottom schematic diagram of another embodiment of the electronic package of the present invention.
[0023] Main component symbols
[0024] 1 Semiconductor Package
[0025] 1a Light Engine Module
[0026] 10,20 Line Structure
[0027] 11 Electronic integrated circuit chips
[0028] 12 Conversion Chip
[0029] 13,23 Conductive column
[0030] 14,24 Wiring structure
[0031] 15,25 Coating
[0032] 16 Photonic Chip
[0033] 17 Solder Ball
[0034] 18 Package substrate
[0035] 19,29 solder balls
[0036] 2 Electronic packaging
[0037] 2a Electronic module
[0038] 200 Insulation
[0039] 201 Line redistribution layer
[0040] 202 Electrical contact pad
[0041] 21 Bridge element
[0042] 21a Action surface
[0043] 21b Non-active surface
[0044] 210 Electrode pads
[0045] 211 Protective film
[0046] 212 Conductors
[0047] 212a,23a,23b End face
[0048] 213 Bonding layer
[0049] 22 Electronic components
[0050] 22a First Electronic Components
[0051] 22b Second electronic component
[0052] 22c Third electronic component
[0053] 220 Conductive bump
[0054] 221,261,31 Primer
[0055] 24 Wiring Structure
[0056] 25a First surface
[0057] 25b Second surface
[0058] 26 Photonic components
[0059] 27a First conductive element
[0060] 27b Second conductive element
[0061] 28 Encapsulation layer
[0062] 30 Load-bearing structure
[0063] 30a First side
[0064] 30b Second side
[0065] 30s side
[0066] 32 recess
[0067] 40 Bus
[0068] 50 Fiber
[0069] 9 Loading plate
[0070] 90 Release layer
[0071] 91 Insulation layer
[0072] A. First connection area
[0073] B Second connection area
[0074] S Cutting path
[0075] W1,W2 distance
[0076] D interval. DETAILED DESCRIPTION
[0077] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0078] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", "third", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.
[0079] Figures 2A to 2G It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.
[0080] like Figure 2A As shown, a plurality of conductive pillars 23 are formed on a carrier board 9 , and at least one (two are shown in this example) bridge element 21 is disposed on the carrier board 9 , wherein the bridge element 21 is combined with and electrically connected to a plurality of conductors 212 .
[0081] The carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90 and an insulating layer 91 such as a dielectric material or a solder mask are sequentially formed by, for example, coating, so that the plurality of conductive pillars 23 are disposed on the insulating layer 91.
[0082] The bridge element 21 is an active element, a passive element or a combination of the two. The active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor and an inductor.
[0083] In this embodiment, the bridge element 21 is a semiconductor chip, such as a driver or a transimpedance amplifier (TIA), which has an active surface 21a and an inactive surface 21b opposite to each other. The inactive surface 21b of the bridge element 21 is bonded to the insulating layer 91 through a bonding layer 213, and the active surface 21a has a plurality of electrode pads 210 and is covered with a protective film 211 such as a passivation material, and a plurality of the conductors 212 are disposed in the protective film 211.
[0084] In addition, the material forming the conductive column 23 is a metal material such as copper or a solder material, and the conductor 212 is a spherical shape such as a conductive line, a solder ball, or a columnar shape of a metal material such as a copper column, a solder bump, or a stud conductive part made by a wire bonding machine, but is not limited thereto.
[0085] like Figure 2B As shown, a coating layer 25 is formed on the insulating layer 91 of the carrier board 9 so that the coating layer 25 covers the bridge elements 21 and the conductive pillars 23, wherein the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, so that the coating layer 25 is bonded to the insulating layer 91 of the carrier board 9 with its second surface 25b, and the protective film 211, the end surfaces 212a of the plurality of conductors 212 and the end surfaces 23a of the plurality of conductive pillars 23 are exposed on the first surface 25a of the coating layer 25.
[0086] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or a packaging colloid or molding compound such as epoxy. For example, the coating layer 25 can be formed on the insulating layer 91 by a process such as liquid compound, injection, lamination, or compression molding.
[0087] Furthermore, a flattening process may be performed to make the first surface 25a of the cladding layer 25 flush with the protective film 211, the end surface 23a of the conductive column 23, and the end surface 212a of the conductor 212, so that the end surface 23a of the conductive column 23 and the end surface 212a of the conductor 212 are exposed on the first surface 25a of the cladding layer 25. For example, the flattening process removes part of the material of the protective film 211, part of the material of the conductive column 23, part of the material of the conductor 212, and part of the material of the cladding layer 25 by grinding.
[0088] In addition, the other end surfaces 23 b of the conductive pillars 23 are also flush with the second surface 25 b of the cladding layer 25 .
[0089] like Figure 2C As shown, a circuit structure 20 is formed on the first surface 25 a of the cladding layer 25 , and the circuit structure 20 is electrically connected to the plurality of conductive pillars 23 and the plurality of conductive bodies 212 .
[0090] In this embodiment, the circuit structure 20 includes a plurality of insulating layers 200 and a plurality of redistribution layers (RDL) 201 disposed on the plurality of insulating layers 200, and the outermost insulating layer 200 can be used as a solder mask, and a portion of the outermost redistribution layer 201 is exposed from the solder mask to serve as an electrical contact pad 202. Alternatively, the circuit structure 20 may include only a single insulating layer 200 and a single redistribution layer 201.
[0091] Furthermore, the material forming the circuit redistribution layer 201 is copper, and the material forming the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or a solder mask such as green paint and ink.
[0092] like Figure 2D As shown, at least one (three in this embodiment) electronic component 22 is disposed on the circuit structure 20, and multiple electronic components 22 are electrically connected to the circuit structure 20, and then a packaging layer 28 is used to cover the multiple electronic components 22. In addition, the multiple electronic components 22 can be electrically connected to each other through the circuit structure 20 and the bridge component 21.
[0093] In this embodiment, the plurality of electronic components 22 include a first electronic component 22a, a second electronic component 22b, and a third electronic component 22c disposed between the first electronic component 22a and the second electronic component 22b. In this embodiment, the first electronic component 22a is, for example, a high bandwidth memory (HBM) chip, the second electronic component 22b is, for example, an electronic integrated circuit (EIC) chip, and the third electronic component 22c is, for example, a switch die. However, the present invention is not limited to the above, and the first electronic component 22a, the second electronic component 22b, and the third electronic component 22c may also be other functional chips, and the first electronic component 22a, the second electronic component 22b, and the third electronic component 22c may also be arranged in other ways.
[0094] Furthermore, the electronic component 22 is electrically connected to the redistribution layer 201 of the circuit structure 20 by a flip chip method through a plurality of conductive bumps 220 such as solder balls, copper pillars or the like. Alternatively, the electronic component 22 can also be electrically connected to the redistribution layer 201 by a wire bonding method through a plurality of wires (not shown). There are many ways for the electronic component 22 to be electrically connected to the redistribution layer 201, and they are not limited to the above.
[0095] In addition, the packaging layer 28 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy, or molding compound, which can be formed on the circuit structure 20 by lamination or molding. It should be understood that the material forming the packaging layer 28 can be the same as or different from the material of the covering layer 25.
[0096] In addition, a flattening process may be performed to make the upper surface of the packaging layer 28 flush with the upper surfaces of the plurality of electronic components 22, so that the upper surfaces of the plurality of electronic components 22 are exposed from the packaging layer 28. For example, the flattening process removes part of the material of the packaging layer 28 and part of the material of the plurality of electronic components 22 by grinding.
[0097] In addition, the underfill 221 may be formed between the electronic components 22 and the circuit structure 20 to cover the conductive bumps 220, and then the packaging layer 28 may be formed to cover the underfill 221 and the electronic components 22. Alternatively, the conductive bumps 220 may be directly covered by the packaging layer 28.
[0098] like Figure 2EAs shown, the carrier plate 9 and the release layer 90 thereon are removed, and the insulating layer 91 is retained, and a wiring structure 24 electrically connected to the plurality of conductive pillars 23 is formed on the insulating layer 91, and a plurality of first conductive element bumps 27a and a plurality of second conductive elements 27b are combined on the wiring structure 24. Figure 2D The cutting path S shown is used for singulation process to obtain a plurality of electronic modules 2a. The electronic module 2a is defined with a first connection area A and a second connection area B separated from each other, and a plurality of first conductive elements 27a are combined on the wiring structure 24 of the first connection area A, and a plurality of second conductive elements 27b are combined on the wiring structure 24 of the second connection area B, wherein the first conductive elements 27a and the second conductive elements 27b may be copper pillars or solder balls, and the size of the first conductive element 27a is larger than the second conductive element 27b, for example, the size of the first conductive element 27a is greater than 130um, and the size of the second conductive element 27b is less than 40um.
[0099] In the present embodiment, the cutting path S is set so that the distances between the side end surfaces of the plurality of electronic components 22 located on opposite sides of the cut electronic module 2a and the side surfaces of the packaging layer 28 (or the electronic module 2a) adjacent thereto are different. That is, the distance W1 between the side end surface of the first electronic component 22a and the side surface of the packaging layer 28 adjacent thereto is different from the distance W2 between the side end surface of the second electronic component 22b and the side surface of the packaging layer 28 adjacent thereto. In the present embodiment, the distance W1 between the side end surface of the first electronic component 22a and the side surface of the packaging layer 28 adjacent thereto may be at least 1400um, and the distance W2 between the side end surface of the second electronic component 22b and the side surface of the packaging layer 28 adjacent thereto may be at least 700um.
[0100] Furthermore, the insulating layer 91 may be formed with a plurality of openings, for example, by laser processing, so that the end surfaces 23 b of the conductive pillars 23 are exposed from the openings for combining with the wiring structure 24 .
[0101] In addition, by providing a carrier plate 9 with an insulating layer 91, the insulating layer 91 can be used to form the wiring structure 24 after removing the carrier plate 9, so there is no need to arrange a dielectric layer, thereby saving process time and process steps, thereby achieving the purpose of reducing process costs.
[0102] like Figure 2F As shown, at least one photonic element 26 such as a photonic chip is connected to the second conductive element 27 b of the second connection area B of the electronic module 2 a.
[0103] In this embodiment, the second conductive elements 27 b may be coated with a primer 261 ; alternatively, the photonic element 26 may directly contact the wiring structure 24 .
[0104] Furthermore, the photonic element 26 and the plurality of electronic elements 22 can transmit signals to each other through the wiring structure 24 , the plurality of conductive pillars 23 and the circuit structure 20 .
[0105] like Figure 2G As shown, the electronic module 2a is connected to a supporting structure 30 through the first conductive elements 27a of the first connection area A, and the first conductive elements 27a are coated with a primer 31 to obtain the electronic package 2 of the present invention.
[0106] In this embodiment, the second connection area B of the electronic module 2a is suspended outside the side 30s of the supporting structure 30, and there is a gap d between the photonic element 26 connected to the second connection area B of the electronic module 2a and the side 30s of the supporting structure 30, and the gap d can be at least 100um.
[0107] In the present embodiment, the supporting structure 30 is in the form of a substrate having a first side 30a and a second side 30b opposite to each other, so that the electronic module 2a is disposed on the first side 30a of the supporting structure 30. For example, the supporting structure 30 is a package substrate having a core layer and a circuit structure or a coreless circuit structure, and the circuit structure includes at least one insulating layer and at least one circuit layer combined with the insulating layer, such as at least one fan-out type redistribution layer (RDL). It should be understood that the supporting structure 30 can also be other plates, such as a lead frame, a wafer, or other carriers with metal routing, etc., and is not limited to the above.
[0108] like Figure 2H As shown, a bus 40 such as an optical fiber cable can be externally connected to the photonic element 26 for signal transmission.
[0109] See also Figure 3 , Figure 3 FIG. 2 is a bottom schematic diagram of another embodiment of the electronic package of the present invention, wherein the electronic module 2a shielded by the supporting structure 30 and the photonic element 26 is indicated by a dotted line. Figure 3 As shown, the supporting structure 30 may have a concave portion 32 and be in a U-shape, the photon element 26 may be disposed in the concave portion 32 of the supporting structure 30, and the electronic module 2a may be connected between the supporting structure 30 and the photon element 26. However, the present invention is not limited to the above, the supporting structure 30 may also be rectangular without the concave portion 32, and the photon element 26 may be disposed outside the supporting structure 30.
[0110] In addition, a plurality of solder balls 29 may be disposed on the second side 30 b of the supporting structure 30 so as to be connected to an electronic device (not shown) such as a circuit board.
[0111] Therefore, in the manufacturing method of the present invention, the electronic module 2a is mainly connected to the supporting structure 30 with the first connection area A so as to partially protrude from the supporting structure 30, and the photonic element 26 is arranged in the protruding second connection area B of the electronic module 2a, so as to reduce the layout area of the supporting structure 30, thereby meeting the demand for miniaturization. In addition, because the second connection area B of the electronic module 2a protrudes outward from the supporting structure 30, the photonic element 26 and the optical fiber are easily joined, avoiding interference with the supporting structure 30.
[0112] In addition, the number of the bridge element 21 , the electronic element 22 , and the photonic element 26 can be designed according to requirements.
[0113] The present invention also provides an electronic package 2, comprising: a supporting structure 30, an electronic module 2a connected to the supporting structure 30 via a first connection area A, and a photonic element 26 electrically connected to a second connection area B of the electronic module 2a, wherein the first connection area A is separated from the second connection area B.
[0114] The electronic module 2a includes a coating layer 25, at least one bridging element 21 embedded in the coating layer 25, at least one conductive column 23 embedded in the coating layer 25, a circuit structure 20 disposed on a first surface 25a of the coating layer 25 and electrically connected to the bridging element 21, and at least one electronic element 22 disposed on the circuit structure 20 and electrically connected to the circuit structure 20, wherein the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, so that the circuit structure 20 is disposed on the first surface 25a of the coating layer 25, and the conductive column 23 is electrically connected to the circuit structure 20.
[0115] In one embodiment, the photonic device 26 is a photonic chip.
[0116] In one embodiment, the photonic chip is externally connected to an optical fiber.
[0117] In one embodiment, the electronic module 2 a is electrically connected to the supporting structure 30 and the photonic element 26 via the first conductive element 27 a and the second conductive element 27 b .
[0118] In one embodiment, the size of the first conductive element 27 a located in the first connection region A is greater than the size of the second conductive element 27 b located in the second connection region B.
[0119] In one embodiment, the distance d between the supporting structure 30 and the photonic element 26 is at least 100 um.
[0120] In one embodiment, the supporting structure 30 has a recess 32 , and the photonic element 26 is disposed in the recess 32 of the supporting structure 30 .
[0121] In one embodiment, the electronic module 2 a includes a plurality of electronic components 22 .
[0122] In one embodiment, the plurality of electronic components 22 are memory chips, electronic integrated circuit chips, and conversion chips.
[0123] In one embodiment, the electronic module 2 a further includes a packaging layer 28 encapsulating the plurality of electronic components 22 .
[0124] In one embodiment, in the electronic module 2 a , the distances W1 and W2 between the side surfaces of the electronic components 22 and the side surfaces adjacent to the packaging layer 28 are different.
[0125] In summary, the electronic package and the manufacturing method of the present invention integrate multiple electronic components into the electronic module, overlap the electronic module with the photon component, and make the electronic module connect to the support structure with the first connection area and partially protrude from the support structure, and place the photon component in the protruding second connection area of the electronic module. Thus, the layout area of the support structure can be reduced to meet the requirements of miniaturization.
[0126] Furthermore, since a plurality of electronic components are integrated into the electronic module, it is possible to avoid too large an insertion loss under high-speed computing due to the long distance between the conversion chip and other chips, and also to avoid the warping of the supporting structure.
[0127] In addition, since the electronic module is configured to protrude outward from the supporting structure, the photonic element and the optical fiber can be easily joined to avoid interference with the supporting structure.
[0128] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.
Claims
1. An electronic package, comprising: load-bearing structure; An electronic module is defined with a first connection area and a second connection area separated from each other, wherein the electronic module is connected to the supporting structure with the first connection area and the second connection area protrudes from the supporting structure; as well as The photonic element is connected to the second connection area of the electronic module and maintains a distance from the supporting structure.
2. The electronic package of claim 1, wherein: The photonic component is externally connected to an optical fiber.
3. The electronic package of claim 1, wherein: The electronic module is electrically connected to the supporting structure through a plurality of first conductive elements arranged on the first connection area, and is electrically connected to the photon element through a plurality of second conductive elements arranged on the second connection area.
4. The electronic package as claimed in claim 3, wherein: The size of the first conductive element located in the first connection region is greater than the size of the second conductive element located in the second connection region.
5. The electronic package of claim 1, wherein: The spacing between the supporting structure and the photonic element is at least 100 um.
6. The electronic package of claim 1, wherein: The supporting structure has a concave portion, and the photon element is arranged in the concave portion of the supporting structure.
7. The electronic package of claim 1, wherein: The electronic module includes a coating layer having a first surface and a second surface relative to each other, a bridging element embedded in the coating layer, a conductive column embedded in the coating layer, a circuit structure arranged on the first surface of the coating layer and electrically connecting the bridging element and the conductive column, and an electronic element arranged on the circuit structure and electrically connected to the circuit structure.
8. The electronic package of claim 7, wherein: The electronic module includes a plurality of electronic components.
9. The electronic package of claim 8, wherein: The plurality of electronic components are memory chips, electronic integrated circuit chips and conversion chips.
10. The electronic package of claim 8, wherein: The electronic module further includes a packaging layer covering the plurality of electronic components.
11. The electronic package of claim 10, wherein: The distances between the side end surfaces of the plurality of electronic components in the electronic module and the side surfaces of the adjacent packaging layers are different.
12. A method for manufacturing an electronic package, comprising: Providing an electronic module, which defines a first connection area and a second connection area separated from each other; electrically connecting the photonic element to the second connection region of the electronic module; as well as The first connection area of the electronic module is connected to a carrying structure, and the second connection area is made to protrude from the carrying structure so as to maintain a spacing between the photon element and the carrying structure.
13. The method for manufacturing an electronic package according to claim 12, wherein: The photonic component is externally connected to an optical fiber.
14. The method for manufacturing an electronic package according to claim 12, wherein: The electronic module is electrically connected to the supporting structure through a plurality of first conductive elements disposed on the first connection area, and is electrically connected to the photon element through a plurality of second conductive elements disposed on the second connection area.
15. The method for manufacturing an electronic package according to claim 14, wherein: The size of the first conductive element located in the first connection region is greater than the size of the second conductive element located in the second connection region.
16. The method for manufacturing an electronic package according to claim 12, wherein: The spacing between the supporting structure and the photonic element is at least 100 um.
17. The method for manufacturing an electronic package according to claim 12, wherein: The supporting structure has a concave portion, and the photon element is arranged in the concave portion of the supporting structure.
18. The method for manufacturing an electronic package according to claim 12, wherein: The electronic module includes a coating layer having a first surface and a second surface relative to each other, a bridging element embedded in the coating layer, a conductive column embedded in the coating layer, a circuit structure arranged on the first surface of the coating layer and electrically connecting the bridging element and the conductive column, and an electronic element arranged on the circuit structure and electrically connected to the circuit structure.
19. The method for manufacturing an electronic package according to claim 18, wherein: The electronic module includes a plurality of electronic components.
20. The method for manufacturing an electronic package according to claim 19, wherein: The plurality of electronic components include a memory chip, an electronic integrated circuit chip and a conversion chip.
21. The method for manufacturing an electronic package as claimed in claim 19, wherein: The electronic module further includes a packaging layer covering the plurality of electronic components.
22. The method for manufacturing an electronic package according to claim 21, wherein: The distances between the side end surfaces of the plurality of electronic components in the electronic module and the side surface of the packaging layer adjacent thereto are different on both sides.