Charge pump circuit using high-voltage domain isolation type clock
By using the design of high-voltage domain isolated clock and isolation device in the charging pump circuit, the problem of small capacitance value of high-voltage capacitors under the CMOS process is solved, and a wider range of use and cost advantages in high-voltage applications are achieved.
Patent Information
- Application Number
- CN202411616976.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-02-25
AI Technical Summary
Under the CMOS process, the capacitance value of the high-voltage capacitor is very small, which results in the voltage difference between the upper and lower stages of the capacitor in high-voltage applications. It is necessary to use a low-voltage capacitor with a voltage of 5V withstand in the CMOS process in the design.
The charging pump circuit that adopts a high-voltage domain isolated clock uses a combination of clock circuit, driving circuit, capacitor Cfly, diode D1 and diode D2, and uses isolation devices and buried layers as the design of isolation islands to achieve capacitance isolation in the high-voltage domain.
No capacitive withstand voltage limit, it has a wider range of use in VIN high voltage applications, and does not require special high-voltage withstand capacitors, which has cost advantages.
Smart Images
Figure CN119519420A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of charge pumps, and in particular to a charge pump circuit using a high-voltage domain isolated clock. Background Art
[0002] like Figure 1 As shown, a traditional charge pump circuit consists of a diode, capacitor, clock circuit (OSC), and driver circuit. Its basic function is: when the driver output CK is low, the input voltage VIN charges the VX node and the output terminal VCP through the diode, VX = VIN - Vpn, VCP = VIN - 2 * Vpn, where Vpn is the diode voltage drop. When the driver circuit's drive signal CK rises from low to 5V, the VX node is raised by 5V by capacitor Cfly, VX = VIN - Vpn + 5, VCP = VIN - 2 * Vpn + 5. Due to the reverse blocking characteristic of the diode, the VX node and the output terminal VCP do not leak through the diode. After multiple cycles of the drive signal CK, the output terminal VCP can reach a voltage higher than VIN by (5 - 2 * Vpn). In applications where the input voltage VIN is high, this circuit structure requires the capacitor to withstand high voltages, but the capacitance of high-voltage capacitors in CMOS processes is very small. Therefore, it is necessary to design a circuit with a low-voltage capacitor with a voltage resistance of 5V that is compatible with the CMOS process. Summary of the Invention
[0003] The present invention aims to provide a charge pump circuit using a high-voltage domain isolation type clock to solve the problem of small high-voltage capacitor capacitance under CMOS technology.
[0004] The present invention provides a charge pump circuit using a high-voltage domain isolated clock, comprising a clock circuit, a drive circuit, a capacitor Cfly, a diode D1, and a diode D2. The power supply is connected to an input voltage VIN, and the ground is connected to an input voltage VIN-x, forming a VIN voltage domain. The clock circuit and the drive circuit operate in the VIN voltage domain. The output end of the clock circuit is connected to the electrical connection point between the diode D1 and the diode D2 via the drive circuit and the capacitor Cfly in sequence. The input voltage VIN-x is connected to the output end VCP via the positive and negative electrodes of the diode D1 and the positive and negative electrodes of the diode D2 in sequence. Both the clock circuit and the drive circuit use isolated devices.
[0005] In some embodiments, the clock circuit is implemented as a ring oscillator composed of a flip-flop and an RC charging circuit.
[0006] In some embodiments, the clock circuit includes a rectifier bridge, a trigger, an RC charging circuit and a NOT gate, and the RC charging circuit includes a first RC charging circuit and a second RC charging circuit; the first branch of the rectifier bridge is connected to the first input end of the trigger via the first RC charging circuit, and the input signal is recorded as vn; the second branch of the rectifier bridge is connected to the second input end of the trigger via the second RC charging circuit, and the input signal is recorded as vp; the output end of the trigger is connected to the control end of the second branch of the rectifier bridge on the one hand, and the output signal is recorded as outp; on the other hand, it is connected to the control end of the first branch of the rectifier bridge via the NOT gate, and the output signal is recorded as outn.
[0007] In some embodiments, a clock circuit is isolated in a CMOS process by using a buried layer as an isolation island and placing all voltage-resistant components of the clock circuit in the isolation island.
[0008] In some embodiments, in the charge pump circuit, the output signal CK low of the driving circuit is VIN-x, and the output signal CK high is VIN;
[0009] When the driving signal CK = VIN-x, VX = VIN-Vpn, the voltage difference between the upper and lower plates of the capacitor Cfly is VX-CK = x-Vpn; Vpn is the diode voltage drop;
[0010] When the driving signal CK transitions from low to high to VIN, VX rises by 5V, which is equal to VIN-Vpn+x, and VCP=VIN-2Vpn+x, which means that the output terminal VCP is higher than VIN by (x-2*Vpn).
[0011] In some embodiments, in the clock circuit, when Vn and Vp are both low levels, the trigger is maintained; when Vn is low, Vp is charged to a high level through the second RC charging circuit, the trigger logic flips, outp is high, outn is low, so that Vp is discharged to a low level, and Vn is charged through the first RC charging circuit; when Vn is charged to a high level, the trigger logic flips, outp is low, outn is high, so that Vn is discharged to a low level, and Vp is charged through the second RC charging circuit; this cycle repeats to generate a clock.
[0012] In some embodiments, the output clock frequency of the clock circuit is Fosc=1 / (2*RC).
[0013] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:
[0014] Compared with traditional circuits, the charge pump circuit using a high-voltage domain isolated clock of the present invention has no capacitor voltage resistance limit and has a wider range of applications in VIN high-voltage applications. It also has a greater cost advantage by not requiring special high-voltage capacitors. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 Schematic diagram of the structure of a traditional charge pump circuit.
[0016] Figure 2 Schematic diagram of the structure of a charge pump circuit using a high-voltage domain isolated clock in an embodiment of the present invention.
[0017] Figure 3 Schematic diagram of the structure of the clock circuit in an embodiment of the present invention.
[0018] Figure 4 1 is a signal waveform diagram of the clock circuit in operation according to an embodiment of the present invention.
[0019] Figure 5 Schematic diagram of the isolation method of the clock circuit in an embodiment of the present invention. DETAILED DESCRIPTION
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.
[0022] Example
[0023] In order to solve the problem of small high-voltage capacitor capacitance under CMOS process, such as Figure 2 As shown, this embodiment proposes a charge pump circuit using a high-voltage domain isolated clock, including a clock circuit, a drive circuit, a capacitor Cfly, a diode D1, and a diode D2; the power supply is connected to the input voltage VIN, and the ground is connected to the input voltage VIN-5V, forming a VIN voltage domain; the clock circuit and the drive circuit operate in the VIN voltage domain; the output end of the clock circuit is connected to the electrical connection point between the diode D1 and the diode D2 in sequence through the drive circuit and the capacitor Cfly; the input voltage VIN-5V is connected to the output end VCP in sequence through the positive and negative electrodes of the diode D1 and the positive and negative electrodes of the diode D2; the clock circuit and the drive circuit both use isolated devices. Among them, 5V is only the withstand voltage requirement of the low-voltage capacitor in the CMOS process in this embodiment, and can be set according to actual needs.
[0024] The charge pump circuit operates as follows: the output signal CK of the drive circuit is VIN-5V when it's low, and VIN when it's high. When the drive signal CK = VIN-5V, VX = VIN-Vpn, and the voltage difference between the upper and lower plates of capacitor Cfly is VX-CK = 5-Vpn (less than 5V). When the drive signal CK transitions from low to high, VX rises by 5V, equal to VIN-Vpn+5V, and VCP = VIN-2Vpn+5V. Therefore, even with the use of low-voltage capacitors, the output voltage VCP can still be higher than VIN by (5-2*Vpn).
[0025] In some embodiments, the clock circuit is implemented as a ring oscillator composed of a trigger and an RC charging circuit, such as Figure 3 As shown, the clock circuit includes a rectifier bridge, a trigger, an RC charging circuit and a NOT gate, and the RC charging circuit includes a first RC charging circuit and a second RC charging circuit; the first branch of the rectifier bridge is connected to the first input terminal of the trigger via the first RC charging circuit, and the input signal is recorded as vn; the second branch of the rectifier bridge is connected to the second input terminal of the trigger via the second RC charging circuit, and the input signal is recorded as vp; the output terminal of the trigger is connected to the control terminal of the second branch of the rectifier bridge on the one hand, and the output signal is recorded as outp; on the other hand, it is connected to the control terminal of the first branch of the rectifier bridge via the NOT gate, and the output signal is recorded as outn.
[0026] like Figure 4 As shown, when both Vn and Vp are low (logic 0), the flip-flop remains in the state of hold. When Vn is low (logic 0), Vp is charged to a high level (logic 1) via the second RC charging circuit, causing the flip-flop to flip, with outp at a high level (logic 1) and outn at a low level (logic 0). This causes Vp to discharge to a low level (logic 0), and Vn to charge via the first RC charging circuit. When Vn is charged to a high level (logic 1), the flip-flop flips, with outp at a low level (logic 0) and outn at a high level (logic 1). This causes Vn to discharge to a low level (logic 0), and Vp to charge via the second RC charging circuit. This repetitive cycle generates a clock, with the output clock frequency determined by RC, Fosc = 1 / (2*RC).
[0027] In some embodiments, as Figure 5 As shown, the isolation method of the clock circuit under the CMOS process is to use a buried layer (NBL) as an isolation island, and the voltage-resistant devices in the clock circuit (such as the 5V voltage-resistant NMOS and PMOS of the rectifier bridge) are all made in the isolation island, so as to achieve operation in the high-voltage VIN voltage domain.
[0028] Compared with traditional circuits, the charge pump circuit using the high-voltage domain isolated clock has no capacitor voltage resistance limit and has a wider range of applications in VIN high-voltage applications. It also has a greater cost advantage by not requiring special high-voltage capacitors.
[0029] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.
Claims
1. A charge pump circuit using a high voltage domain isolation type clock, characterized in that: It includes a clock circuit, a drive circuit, a capacitor Cfly, a diode D1 and a diode D2; the power supply is connected to the input voltage VIN, and the ground is connected to the input voltage VIN-x, forming a VIN voltage domain; the clock circuit and the drive circuit work in the VIN voltage domain; the output end of the clock circuit is connected to the electrical connection point between the diode D1 and the diode D2 via the drive circuit and the capacitor Cfly in sequence; the input voltage VIN-x is connected to the output end VCP via the positive and negative electrodes of the diode D1 and the positive and negative electrodes of the diode D2 in sequence; the clock circuit and the drive circuit both use isolated devices.
2. The charge pump circuit using a high voltage domain isolation type clock according to claim 1, characterized in that: The clock circuit is realized by using a ring oscillator composed of a trigger and an RC charging circuit.
3. The charge pump circuit using a high voltage domain isolation type clock according to claim 2, characterized in that: The clock circuit includes a rectifier bridge, a trigger, an RC charging circuit and a NOT gate, and the RC charging circuit includes a first RC charging circuit and a second RC charging circuit; the first branch of the rectifier bridge is connected to the first input terminal of the trigger via the first RC charging circuit, and the input signal is recorded as vn; the second branch of the rectifier bridge is connected to the second input terminal of the trigger via the second RC charging circuit, and the input signal is recorded as vp; the output terminal of the trigger is connected to the control terminal of the second branch of the rectifier bridge on the one hand, and the output signal is recorded as outp, and is connected to the control terminal of the first branch of the rectifier bridge via the NOT gate on the other hand, and the output signal is recorded as outn.
4. The charge pump circuit using a high voltage domain isolation type clock according to claim 1, characterized in that: The isolation method of the clock circuit under the CMOS process is to use a buried layer to make an isolation island, and to place the voltage-resistant components of the clock circuit in the isolation island.
5. The charge pump circuit using a high voltage domain isolation type clock according to claim 1, characterized in that: In the charge pump circuit, the output signal CK of the drive circuit is low, which is VIN-x, and the output signal CK is high, which is VIN; When the driving signal CK=VIN-x, VX=VIN-Vpn, the voltage difference between the upper and lower plates of the capacitor Cfly is VX-CK=x-Vpn; Vpn is the diode voltage drop; When the driving signal CK turns from low to high to VIN, VX rises by 5V, which is equal to VIN-Vpn+x, and VCP=VIN-2Vpn+x, that is, the output terminal VCP is higher than VIN by (x-2*Vpn) voltage.
6. The charge pump circuit using a high voltage domain isolation type clock according to claim 3, characterized in that: In the clock circuit, when Vn and Vp are both low levels, the trigger is maintained; when Vn is low level, Vp is charged to a high level through the second RC charging circuit, the trigger logic flips, outp is high level, outn is low level, so Vp is discharged to a low level, and Vn is charged through the first RC charging circuit; when Vn is charged to a high level, the trigger logic flips, outp is low level, outn is high level, so Vn is discharged to a low level, and Vp is charged through the second RC charging circuit; this reciprocating cycle generates a clock.
7. The charge pump circuit using a high voltage domain isolation type clock according to claim 6, characterized in that: The output clock frequency of the clock circuit is Fosc=1 / (2*RC).