Fast locking frequency hopping frequency source based on phase-locked loop frequency synthesis module and control method

Abstract

The invention discloses a fast-locking frequency hopping frequency source based on a phase-locked loop frequency synthesis module and a control method, which are applied to a communication system, and are characterized in that a loop filter module quickly charges a narrow-band loop filter circuit or a broadband loop filter circuit based on a fast-locking instruction and a first processing voltage value to reach a preset voltage value; based on the quick locking instruction and the analog signal, the narrowband loop filter circuit or the broadband loop filter circuit is controlled to quickly lock the first frequency value to obtain a locking result; and if the locking result is that the locking is successful, switching the narrowband loop filter circuit or the broadband loop filter circuit. By implementing the embodiment of the invention, the narrow-band loop filter circuit or the broadband loop filter circuit is controlled to quickly lock the first frequency value to obtain the locking result in the process of quickly charging the narrow-band loop filter circuit or the broadband loop filter circuit to reach the preset voltage value. Therefore, charging and locking are carried out at the same time, the fast locking time is saved, and the communication efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency sources, and in particular to a fast-lock frequency hopping frequency source based on a phase-locked loop frequency synthesis module and a control method thereof. Background Art

[0002] With the widespread application of modern communication systems, the requirements for the anti-interference ability of communication systems are constantly increasing, and frequency hopping is currently the most effective communication method to resist interference.

[0003] The frequency synthesizer of frequency hopping is the core of frequency hopping radio. High hopping speed, short switching time and precise control are important factors for high-performance communication equipment, which directly affect the performance of communication system. However, fast frequency hopping is mutually restricted by factors such as loop bandwidth, phase noise, spurious and power consumption. Therefore, the existing fast frequency hopping technology has the problem of low communication efficiency. Summary of the invention

[0004] The embodiment of the present invention provides a fast-lock frequency hopping frequency source and a control method based on a phase-locked loop frequency synthesis module, aiming to solve the problem of low communication efficiency of the fast frequency hopping technology in the prior art.

[0005] In order to solve the above problems, in a first aspect, an embodiment of the present invention provides a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module, which is applied to a communication system, and includes a controller module, a digital-to-analog conversion module, an analog-to-digital conversion module and a phase-locked loop frequency synthesis module; the controller module is communicatively connected with the digital-to-analog conversion module, the analog-to-digital conversion module and the phase-locked loop frequency synthesis module; the phase-locked loop frequency synthesis module includes a phase detector module, a loop filter module and a voltage-controlled oscillator; the phase detector module is connected with the controller module, and is also connected with the loop filter module and the voltage-controlled oscillator; the loop filter module is also connected with the voltage-controlled oscillator, the digital-to-analog conversion module and the analog-to-digital conversion module;

[0006] When receiving the quick lock instruction sent by the controller module, the first processing voltage value sent by the digital-to-analog conversion module, and the analog signal and the first frequency value sent by the phase detector module, the loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to reach a preset voltage value based on the received quick lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received quick lock instruction and the analog signal to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched.

[0007] In a second aspect, an embodiment of the present invention further provides a control method for a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module as described in the first aspect, the method comprising:

[0008] When receiving or sending communication data, the controller module configures a frequency table based on the communication data, sends a first frequency value in the frequency table to the phase detector module, sends a calibration instruction and a first voltage value corresponding to the first frequency value in the frequency table to the digital-to-analog converter, and sends a fast lock instruction to the loop filter module;

[0009] The digital-to-analog conversion module converts and amplifies the received first voltage value based on the received calibration instruction to obtain a first processed voltage value, and sends the first processed voltage value to the loop filter module;

[0010] The phase detector module generates an analog signal according to the received first frequency value, and sends the analog signal and the first frequency value to the loop filter module;

[0011] The loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to reach a preset voltage value based on the received fast lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received fast lock instruction and the analog signal to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched, and a control voltage value is output to a voltage-controlled oscillator; and the control voltage value is divided to obtain a divided voltage value;

[0012] The analog-to-digital conversion module collects the divided voltage value, performs conversion processing on it, and obtains a target voltage value of the first frequency value, and sends the target voltage value to the controller module;

[0013] The controller module updates the target voltage value to the voltage corresponding to the first frequency value in the frequency table;

[0014] The voltage-controlled oscillator performs synthesis processing based on the control voltage value to obtain a target frequency sub-value;

[0015] The controller module frequency-hops to a second frequency value in the frequency table based on the communication data until the voltage-controlled oscillator synthesizes each frequency value in the frequency table to obtain the corresponding target frequency sub-value.

[0016] The embodiment of the present invention provides a fast-lock frequency hopping frequency source and control method based on a phase-locked loop frequency synthesis module, which is applied to a communication system and includes a controller module, a digital-to-analog conversion module, an analog-to-digital conversion module and a phase-locked loop frequency synthesis module; the controller module is communicatively connected with the digital-to-analog conversion module, the analog-to-digital conversion module and the phase-locked loop frequency synthesis module; the phase-locked loop frequency synthesis module includes a phase detector module, a loop filter module and a voltage-controlled oscillator; the phase detector module is connected with the controller module and also with the loop filter module; the loop filter module is also connected with the voltage-controlled oscillator, the digital-to-analog conversion module and the analog-to-digital conversion module; when receiving the When the controller module receives the fast lock instruction, the digital-to-analog conversion module receives the first processing voltage value, and the phase detector module receives the analog signal, the loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to reach the preset voltage value based on the received fast lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received fast lock instruction and the analog signal to obtain a locking result; if the locking result is a successful locking, the narrowband loop filter circuit or the broadband loop filter circuit is switched. By implementing the embodiment of the present invention, in the process of quickly charging the narrowband loop filter circuit or the broadband loop filter circuit to reach the preset voltage value, the narrowband loop filter circuit or the broadband loop filter circuit is controlled to quickly lock the first frequency value to obtain a locking result, and when the locking is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched. Therefore, charging and locking are performed simultaneously, saving the time of fast locking, thereby improving communication efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0018] Figure 1 A schematic structural diagram of the framework of a fast-lock frequency hopping frequency source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention;

[0019] Figure 2 A schematic structural diagram of a part of the circuit of a loop filter module in a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention;

[0020] Figure 3A schematic structural diagram of a portion of the circuits of a digital-to-analog conversion module and a loop filter module in a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention;

[0021] Figure 4 A schematic circuit diagram of an analog-to-digital conversion module in a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention;

[0022] Figure 5 The present invention provides a flowchart of a method for controlling a fast-lock frequency hopping frequency source based on a phase-locked loop frequency synthesis module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but are not used to limit the present invention. In addition, in the drawings, structures with similar or identical structures are represented by the same reference numerals.

[0025] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0026] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0027] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0028] See also Figure 1-4 , Figure 1A schematic structural diagram of the framework of a fast-lock frequency hopping frequency source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention; Figure 2 A schematic structural diagram of a part of the circuit of a loop filter module in a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention; Figure 3 A schematic structural diagram of a portion of the circuits of a digital-to-analog conversion module and a loop filter module in a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention; Figure 4 A schematic circuit structure diagram of an analog-to-digital conversion module in a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention.

[0029] like Figure 1-4 As shown, the embodiment of the present invention provides a fast-lock frequency hopping source 1 based on a phase-locked loop frequency synthesis module, which is applied to a communication system and includes a controller module 10, a digital-to-analog conversion module 20, an analog-to-digital conversion module 30 and a phase-locked loop frequency synthesis module; the controller module 10 is communicatively connected with the digital-to-analog conversion module 20, the analog-to-digital conversion module 30 and the phase-locked loop frequency synthesis module; the phase-locked loop frequency synthesis module includes a phase detector module 40, a loop filter module 50 and a voltage-controlled oscillator 60; the phase detector module 40 is connected to the controller module 10, and is also connected to the loop filter module 50 and the voltage-controlled oscillator 60; the loop filter module 50 is also connected to the voltage-controlled oscillator 60, the digital-to-analog conversion module 20 and the analog-to-digital conversion module 30;

[0030] When receiving the quick lock instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal and the first frequency value sent by the phase detector module 40, the loop filter module 50 quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module 50 to reach a preset voltage value based on the received quick lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received quick lock instruction and the analog signal to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched.

[0031] In this embodiment, if Figure 1-4As shown, the communication system refers to a data transmission system with a receiving function or a sending function, which can send and receive the communication data. For example, the communication system can be used in navigation and electronic countermeasure systems, cellular communications, satellite communications, microwave radio, radar systems, measurement and testing, tactical radio and other equipment; the digital-to-analog conversion module 20 is used to perform digital-to-analog conversion and amplification processing on the first voltage value to obtain the first processed voltage value; the phase detector module 40 includes a crystal oscillator, a control frequency register and a phase detector, the control frequency register includes a reference divider and a feedback divider, the crystal oscillator is connected to the reference divider, and the reference divider is connected to the phase detector. The phase detector is connected to the feedback divider and the loop filter module 50 to form a loop; the crystal oscillator is used to provide a reference frequency to the reference divider, for example, the reference frequency can be 19.2MHz; the control frequency register can confirm that the controller module 10 sends the first frequency value or the second frequency value and other frequency values ​​to the reference divider or the feedback divider to control and lock the frequency according to the protocol defined in the specific situation; the phase detector is used to output the analog signal adjusted according to the input first frequency value or the second frequency value, and the analog signal is a pulse signal generated by the error value compared by the phase detector.

[0032] The communication data is provided by the communication system; the frequency table is a corresponding calibrated table configured according to the communication data and initializes the frequency value and the voltage value according to the timetable, corresponding to the corresponding channel, for example, it can correspond to a channel of 100 MHz to 150 MHz or a channel of 150 MHz to 200 MHz; a general frequency hopping frequency table may include 40 to 1024 frequency points, such as a narrowband waveform of an ultra-short wave radio station has a total of 232 frequency points, or a very correct waveform has 1024 points, 256 points or 512 points; the first frequency value refers to the first frequency value in the frequency table, the second frequency value refers to the second frequency value in the frequency table, and so on; the calibration instruction is an instruction generated by the controller module 10 when receiving the communication data to control the digital-to-analog conversion module 20; the first voltage value is The first frequency value is the voltage value corresponding to the storage in the frequency table; the quick lock instruction is an instruction generated by the controller module 10 when receiving the communication data to control the loop filter module 50; the quick lock instruction includes a quick lock enable instruction, a quick lock charging control instruction and a lock instruction, the quick lock enable instruction is used to control the loop filter module 50 to start the quick lock process, the quick lock control instruction is used to control the loop filter module 50 to perform a quick charge process or stop the quick charge process, and the lock instruction is used to control the loop filter module 50 to perform a lock process; the preset voltage value refers to the voltage value determined by the loop filter module 50 after the initialization process, which can be set according to the actual situation, and corresponds to the charging time used by the loop filter module 50 for the quick charging process.

[0033] The fast-lock frequency hopping source 1 based on the phase-locked loop frequency synthesis module also includes a power supply module, which is connected to the controller module 10, the digital-to-analog conversion module 20, the analog-to-digital conversion module 30 and the phase-locked loop frequency synthesis module, and is used to provide working power to the controller module 10, the digital-to-analog conversion module 20, the analog-to-digital conversion module 30 and the phase-locked loop frequency synthesis module.

[0034] The controller module 10 is used to configure a frequency table based on the communication data when receiving or sending communication data, and send a first frequency value in the frequency table to the phase detector module 40, and send a calibration instruction and a first voltage value corresponding to the first frequency value in the frequency table to the digital-to-analog converter 20, and send a fast lock instruction to the loop filter module 50; the digital-to-analog conversion module 20 is used to convert and amplify the received first voltage value based on the received calibration instruction to obtain a first processed voltage value, and send the first processed voltage value to the loop filter module 50; the phase detector module 40 is used to generate an analog signal according to the received first frequency value, and send the analog signal to the loop filter module 50; the loop filter module 50 is used to quickly charge the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module 50 to a preset voltage value based on the received fast lock instruction and the first processed voltage value, and based on the received fast lock instruction and the analog The analog signal controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched and a control voltage value is output to the voltage-controlled oscillator 60; and the control voltage value is divided to obtain a divided voltage value; the analog-to-digital conversion module 30 is used to collect the divided voltage value for conversion to obtain a target voltage value of the first frequency value, and send the target voltage value to the controller module 10; the controller module 10 is also used to update the target voltage value to the voltage corresponding to the first frequency value in the frequency table; the voltage-controlled oscillator 40 is used to perform synthesis processing based on the control voltage value to obtain a target frequency sub-value; the controller module 10 is also used to hop to a second frequency value in the frequency table based on the communication data until the voltage-controlled oscillator 40 synthesizes each frequency value in the frequency table to obtain the corresponding target frequency sub-value.

[0035] Specifically, the fast-lock frequency hopping source 1 based on the phase-locked loop frequency synthesis module includes two working modes, namely, a narrowband frequency hopping mode and a broadband frequency modulation mode, and the narrowband frequency hopping mode and the broadband frequency modulation mode are determined according to the communication data; that is, the controller module 10 selects the narrowband frequency hopping mode or the broadband frequency modulation mode according to the communication data to determine the working mode.

[0036] When in the narrowband frequency hopping mode, that is, receiving the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the high-level lock instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal and the first frequency value sent by the phase detector module 40, the loop filter module 50 starts to select the broadband filter circuit to quickly capture and lock the first frequency value according to the high-level lock instruction and the analog signal to obtain the locking result. At the same time, the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the first processing voltage value are used to select the narrowband loop filter circuit for fast charging. After reaching the preset voltage value, and the locking result is successful locking, the broadband filter circuit is controlled to switch to the narrowband loop filter circuit, thereby realizing the secondary narrowband fast lock of the phase-locked loop frequency synthesis module.

[0037] When in the broadband frequency hopping mode, that is, receiving the low-level fast lock enable instruction, the high-level fast lock charge control instruction and the low-level lock instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal and the first frequency value sent by the phase detector module 40, the loop filter module 50 starts to select the narrowband filter circuit to quickly capture and lock the first frequency value according to the low-level lock instruction and the analog signal to obtain the locking result. At the same time, the low-level fast lock enable instruction, the high-level fast lock charge control instruction and the first processing voltage value are used to select the broadband loop filter circuit for fast charging. After reaching the preset voltage value, and the locking result is successful locking, the narrowband filter circuit is controlled to switch to the broadband loop filter circuit, thereby realizing the secondary broadband fast lock of the phase-locked loop frequency synthesis module.

[0038] By implementing the embodiment of the present invention, in the process of quickly charging the narrowband loop filter circuit or the broadband loop filter circuit to reach the preset voltage value, the narrowband loop filter circuit or the broadband loop filter circuit is used to quickly lock the first frequency value to obtain a locking result. Therefore, charging and locking are performed simultaneously, which reduces phase noise, spurious and power consumption, saves fast locking time, and thus improves communication efficiency.

[0039] In one embodiment, if Figure 1-3As shown, the loop filter module 50 includes a fast lock control circuit, a narrowband loop filter circuit and a broadband loop filter circuit; the fast lock control circuit includes a first fast lock control circuit, a second fast lock control circuit, a third fast lock control circuit and a fourth fast lock control circuit; the first fast lock control circuit is connected to the narrowband loop filter circuit and the broadband loop filter circuit, and is also connected to the phase detector module 40 and the controller module 10; the second fast lock control circuit is connected to the narrowband loop filter circuit and the broadband loop filter circuit, and is also connected to the controller module 10, the voltage controlled oscillator 60 and the analog-to-digital conversion module 30; the third fast lock control circuit is connected to the digital-to-analog conversion module 20, and is also connected to the fourth fast lock control circuit and the controller module 10; the fourth fast lock control circuit is also connected to the second fast lock control circuit, the narrowband loop filter circuit and the broadband loop filter circuit.

[0040] In this embodiment, if Figure 1-3As shown, the third fast lock control circuit is connected to the digital-analog control module to receive the first processing voltage value, and is also connected to the controller module 10 to receive the fast lock enable instruction to start the fast lock process, and is also connected to the power module to receive the working power; the fourth fast lock control circuit is connected to the third fast lock control circuit to receive the enable signal, and is also connected to the controller module 10 to receive the fast lock charging control instruction to determine whether to perform fast charging processing on the narrowband loop filter circuit or the broadband loop filter circuit or stop fast charging processing, and is also connected to the power module to receive the working power; the first fast lock control circuit is connected to the phase detector module 40 to receive the analog signal, and is also connected to the controller module 10 to receive the locking instruction and determine in combination with the second fast lock control circuit that the narrowband loop filter circuit or the broadband loop filter circuit performs fast locking processing on the first frequency value, and is also connected to the power module to receive working power supply; the second fast lock control circuit is connected to the controller module 10 to receive the locking instruction and determine in combination with the first fast lock control circuit whether the narrowband loop filter circuit or the broadband loop filter circuit performs fast locking processing on the first frequency value, and is also connected to the power supply module to receive the working power supply, and is also connected to the voltage-controlled oscillator 60 to output the control voltage value to the voltage-controlled oscillator 60, and is also connected to the analog-to-digital conversion module 30 so that the analog-to-digital conversion module 30 collects the divided voltage value; the narrowband loop filter circuit is connected to the fourth fast lock control circuit for fast charging processing, and is also connected to the first fast lock control circuit and the second fast lock control circuit for fast locking processing on the first frequency value; the broadband loop filter circuit is connected to the fourth fast lock control circuit for fast charging processing, and is also connected to the first fast lock control circuit and the second fast lock control circuit for fast locking processing on the first frequency value.

[0041] The fast-lock frequency hopping source 1 based on the phase-locked loop frequency synthesis module includes two working modes, namely, a narrowband frequency hopping mode and a broadband frequency modulation mode, and the narrowband frequency hopping mode and the broadband frequency modulation mode are determined according to the communication data; that is, the controller module 10 selects the narrowband frequency hopping mode or the broadband frequency modulation mode according to the communication data to determine the working mode.

[0042] When in the narrowband frequency hopping mode, that is, when receiving the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the high-level lock instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal sent by the phase detector module 40, the loop filter module 50 starts to select the broadband filter circuit to quickly capture and lock the first frequency value according to the high-level lock instruction and the analog signal to obtain the locking result. At the same time, the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the first processing voltage value are controlled by the third fast lock control module and the fourth fast lock control module to quickly charge the narrowband loop filter circuit. After reaching the preset voltage value and the locking result is successful locking, the broadband filter circuit is controlled to switch to the narrowband loop filter circuit, thereby realizing the secondary narrowband fast lock of the phase-locked loop frequency synthesis module.

[0043] When in the broadband frequency hopping mode, that is, receiving the low-level fast lock enabling instruction, the high-level fast lock charging control instruction and the low-level locking instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal and the first frequency value sent by the phase detector module 40, the loop filter module 50 starts to select the narrowband filter circuit to quickly capture and lock the first frequency value according to the low-level locking instruction and the analog signal. At the same time, the broadband loop filter circuit is quickly charged by the third fast lock control module and the fourth fast lock control module using the low-level fast lock enabling instruction, the high-level fast lock charging control instruction and the first processing voltage value. After reaching the preset voltage value and the locking result is successful locking, the narrowband filter circuit is controlled to switch to the broadband loop filter circuit, thereby realizing the secondary broadband fast lock of the phase-locked loop frequency synthesis module.

[0044] Through the above embodiments, it can be known that by utilizing the narrowband loop filter circuit and the broadband loop filter circuit in combination with the first fast lock control circuit, the second fast lock control circuit, the third fast lock control circuit and the fourth fast lock control circuit, the controller module performs control locking processing, charging processing and switching processing, thereby saving the entire fast lock time and improving communication efficiency.

[0045] In one embodiment, if Figure 1-2 As shown, the narrowband loop filter circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third resistor R3, a third capacitor C3, a fourth capacitor C4, a fourth resistor R4, a fifth capacitor C5 and a sixth capacitor C6;

[0046] The first end of the first resistor R1 is connected to the first fast lock control circuit, the first end of the first capacitor C1, the first end of the second capacitor C2, and the first end of the third resistor R3; the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first end of the third capacitor C3; the second end of the second capacitor C2 is connected to the second end of the third resistor R3 and the first end of the fourth resistor R4; the second end of the fourth resistor R4 is connected to the first end of the fifth capacitor C5, the first end of the sixth capacitor C6, and the second end of the third capacitor C3; the second end of the second resistor R2 is connected to the first end of the fourth capacitor C4, the fourth fast lock control circuit and the second fast lock control circuit; the second end of the first capacitor C1, the second end of the fourth capacitor C4, the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6 are all grounded.

[0047] In this embodiment, if Figure 1-2 As shown, the specification of the first resistor R1 is 12; the specification of the second resistor R2 is 0; the specification of the first capacitor C1 is 0.1uF; the specification of the second capacitor C2 is 0.027uF; the specification of the third resistor R3 is 33; the specification of the third capacitor C3 is NC; the specification of the fourth capacitor C4 is 0.1uF; the specification of the fourth resistor R4 is 82; the specification of the fifth capacitor C5 is 0.22uF; the specification of the sixth capacitor C6 is 0.47uF. It should be noted that the model, specification and connection relationship of each component in the narrowband loop filter circuit can be designed according to actual conditions.

[0048] When in the narrowband frequency hopping mode, that is, receiving the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the high-level lock instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal and the first frequency value sent by the phase detector module 40, the loop filter module 50 starts to select the broadband filter circuit to quickly capture and lock the first frequency value according to the high-level lock instruction and the analog signal to obtain the locking result. At the same time, the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the first processing voltage value are controlled by the third fast lock control module and the fourth fast lock control module to quickly charge the narrowband loop filter circuit. After reaching the preset voltage value, and the locking result is successful, the broadband filter circuit is controlled to switch to the narrowband loop filter circuit, thereby realizing the secondary narrowband fast lock of the phase-locked loop frequency synthesis module. Among them, the preset voltage value is determined according to the narrowband loop filter circuit, so that the charging time used for the fast charging process is determined.

[0049] Through the above embodiments, it can be known that in the narrowband frequency hopping mode, the controller module sends a low-level fast lock enable instruction, a low-level fast lock charging control instruction and a high-level locking instruction, the digital-to-analog conversion module sends a first processing voltage value and the phase detector module sends an analog signal and a first frequency value, so as to control the loop filter module to select a broadband filter circuit to capture and lock the first frequency value to obtain a locking result. At the same time, the digital-to-analog conversion module is combined with the third fast lock control module and the fourth fast lock control module to quickly charge the narrowband loop filter circuit. After reaching the preset voltage value, and the locking result is a successful locking, the broadband filter circuit is switched to the narrowband loop filter circuit, thereby realizing the secondary narrowband fast lock of the phase-locked loop frequency synthesis module. Therefore, charging and locking are carried out simultaneously, saving the time of fast lock, thereby improving communication efficiency.

[0050] In one embodiment, if Figure 1-2 As shown, the broadband loop filter circuit includes a fifth resistor R5, a sixth resistor R6, a seventh capacitor C7, an eighth capacitor C8, a seventh resistor R7, a ninth capacitor C9, a tenth capacitor C10, an eighth resistor R8, an eleventh capacitor C11 and a twelfth capacitor C12;

[0051] The first end of the fifth resistor R5 is connected to the first fast lock control circuit, the first end of the seventh capacitor C7, the first end of the eighth capacitor C8, and the first end of the seventh resistor R7; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the first end of the tenth capacitor C10; the second end of the eighth capacitor C8 is connected to the second end of the seventh resistor R7 and the first end of the eighth resistor R8; the second end of the eighth resistor R8 is connected to the first end of the eleventh capacitor C11, the first end of the twelfth capacitor C12, and the second end of the tenth capacitor C10; the second end of the sixth resistor R6 is connected to the first end of the ninth capacitor C9, the fourth fast lock control circuit and the second fast lock control circuit; the second end of the seventh capacitor C7, the second end of the ninth capacitor C9, the second end of the eleventh capacitor C11, and the second end of the twelfth capacitor C12 are all grounded.

[0052] In this embodiment, if Figure 1-2As shown, the specification of the fifth resistor R5 can be 1K; the specification of the sixth resistor R6 can be 1K; the specification of the seventh capacitor C7 can be 390nF; the specification of the eighth capacitor C8 can be 270pF; the specification of the seventh resistor R7 can be 700; the specification of the ninth capacitor C9 can be 330pF; the specification of the tenth capacitor C10 can be 470pF; the specification of the eighth resistor R8 can be 120; the specification of the eleventh capacitor C11 can be 3.9nF; the specification of the twelfth capacitor C12 can be 4.7nF. It should be noted that the model, specification and connection relationship of each component in the broadband loop filter circuit can be designed according to actual conditions.

[0053] When in the broadband frequency hopping mode, that is, receiving the low-level fast lock enable instruction, the high-level fast lock charge control instruction and the low-level lock instruction sent by the controller module 10, the first processing voltage value sent by the digital-to-analog conversion module 20, and the analog signal and the first frequency value sent by the phase detector module 40, the loop filter module 50 starts to select the narrowband filter circuit to quickly capture and lock the first frequency value according to the low-level lock instruction and the analog signal to obtain the locking result. At the same time, the broadband loop filter circuit is quickly charged by the third fast lock control module and the fourth fast lock control module using the low-level fast lock enable instruction, the high-level fast lock charge control instruction and the first processing voltage value. After reaching the preset voltage value, and the locking result is successful, the narrowband filter circuit is controlled to switch to the broadband loop filter circuit, thereby realizing the secondary broadband fast lock of the phase-locked loop frequency synthesis module. Among them, the preset voltage value is determined according to the broadband loop filter circuit, so that the charging time used for the fast charging process is determined.

[0054] Through the above embodiments, it can be known that in the broadband frequency hopping mode, the controller module sends a low-level fast lock enable instruction, a high-level fast lock charge control instruction and a low-level lock instruction, the digital-to-analog conversion module sends a first processing voltage value and the phase detector module sends an analog signal and a first frequency value, so as to control the loop filter module to select a narrowband filter circuit to capture and lock the first frequency value to obtain a locking result, and at the same time, the digital-to-analog conversion module is combined with the third fast lock control module and the fourth fast lock control module to quickly charge the broadband loop filter circuit, and after reaching the preset voltage value, if the locking result is successful, the narrowband filter circuit is switched to the broadband loop filter circuit, thereby realizing the secondary broadband fast lock of the phase-locked loop frequency synthesis module. Therefore, charging and locking are carried out simultaneously, saving the time of fast lock, thereby improving communication efficiency.

[0055] In one embodiment, if Figure 1-2As shown, the first fast lock control circuit includes a first control chip U1, a thirteenth capacitor C13, a fourteenth capacitor C14, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a fifteenth capacitor C15;

[0056] The first pin of the first control chip U1 is connected to the first end of the first capacitor C1, the first end of the second capacitor C2, the first end of the third resistor R3 and the first end of the first resistor R1; the third pin of the first control chip U1 is connected to the first end of the seventh capacitor C7, the first end of the eighth capacitor C8, the first end of the seventh resistor R7 and the first end of the fifth resistor R5; the fourth pin of the first control chip U1 is connected to the second end of the eleventh resistor R11 and the first end of the fifteenth capacitor C15, and the first end of the eleventh resistor R11 is connected to the controller module 10; the fifth pin of the first control chip U1 is connected to the second end of the ninth resistor R9, the second end of the thirteenth capacitor C13 and the second end of the fourteenth capacitor C14; the sixth pin of the first control chip U1 is connected to the second end of the tenth resistor R10; the first end of the tenth resistor R10 is connected to the phase detector module 40; the second pin of the first control chip U1, the first end of the thirteenth capacitor C13, the first end of the fourteenth capacitor C14 and the second end of the fifteenth capacitor C15 are all grounded.

[0057] In this embodiment, if Figure 1-2 As shown, the model of the first control chip U1 can be WAS3157D; the specification of the thirteenth capacitor C13 can be 1uF; the specification of the fourteenth capacitor C14 can be 220pF; the specification of the ninth resistor R9 can be 5.6; the specification of the tenth resistor R10 can be 0; the specification of the eleventh resistor R11 can be 33; the specification of the fifteenth capacitor C15 can be 47pF. It should be noted that the model, specification and connection relationship of each component in the first fast lock control circuit can be designed according to actual conditions.

[0058] The first end of the ninth resistor R9 is connected to the power module so that the power module provides a first working power supply, and the corresponding voltage value of the first working power supply is 5V. Figure 2 As shown, the first working power supply is represented by 5VA_FGU_RX in the circuit diagram. The first end of the tenth resistor R10 is connected to the phase detector to receive the analog signal sent by the phase detector. Figure 2 As shown, the analog signal is represented by CPout in the circuit diagram. The first end of the eleventh resistor R11 is connected to the controller module 10 to receive the locking instruction, such as Figure 2As shown, the locking instruction is represented by Loop_Ctrl in the circuit diagram.

[0059] Through the above embodiments, it can be known that the first fast lock control circuit controls the narrowband loop filter circuit or the wideband loop filter circuit to perform targeted processing on the capture and lock of the first frequency value according to the analog signal sent by the phase detector and the lock instruction sent by the controller module, thereby improving data stability and communication efficiency.

[0060] In one embodiment, if Figure 1-2 As shown, the second fast lock control circuit includes a second control chip U2, a sixteenth capacitor C16, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a seventeenth capacitor C17, an eighteenth capacitor C18, a sixteenth resistor R16, a seventeenth resistor R17 and a nineteenth capacitor C19;

[0061] The first pin of the second control chip U2 is connected to the second end of the second resistor R2, the first end of the fourth capacitor C4 and the fourth fast lock control circuit; the third pin of the second control chip U2 is connected to the second end of the sixth resistor R6, the first end of the ninth capacitor C9 and the fourth fast lock control circuit; the fourth pin of the second control chip U2 is connected to the second end of the sixteenth capacitor C16 and the first end of the twelfth resistor R12, and the second end of the twelfth resistor R12 is connected to the controller module 10; the fifth pin of the second control chip U2 is connected to the first end of the fourteenth resistor R14, the first end of the seventeenth capacitor C17 and the first end of the eighteenth capacitor C18; the first control The 6th pin of the control chip U1 is connected to the first end of the thirteenth resistor R13, and the second end of the thirteenth resistor R13 is connected to the voltage-controlled oscillator 60 and the first end of the fifteenth resistor R15; the second end of the fifteenth resistor R15 is connected to the second end of the sixteenth resistor R16 and the first end of the nineteenth capacitor C19, and the first end of the sixteenth resistor R16 is connected to the analog-to-digital conversion module 30 and the first end of the seventeenth resistor R17; the 2nd pin of the second control chip U2, the first end of the sixteenth capacitor C16, the second end of the seventeenth capacitor C17, the second end of the eighteenth capacitor C18, the second end of the seventeenth resistor R17 and the second end of the nineteenth capacitor C19 are all grounded.

[0062] In this embodiment, if Figure 1-2As shown, the model of the second control chip U2 can be WAS3157D; the specification of the sixteenth capacitor C16 can be 47pF; the specification of the twelfth resistor R12 can be 33; the specification of the thirteenth resistor R13 can be 0; the specification of the fourteenth resistor R14 can be 5.6; the specification of the fifteenth resistor R15 can be 0; the specification of the seventeenth capacitor C17 can be 220pF; the specification of the eighteenth capacitor C18 can be 1uF; the specification of the sixteenth resistor R16 can be 200k 0.1%; the specification of the seventeenth resistor R17 can be 200k 0.1%; the specification of the nineteenth capacitor C19 can be NC. It should be noted that the model, specification and connection relationship of each component in the second fast lock control circuit can be designed according to actual conditions.

[0063] The second end of the twelfth resistor R12 is connected to the controller module 10 to receive the locking instruction. The second end of the thirteenth resistor R13 is also connected to the voltage-controlled oscillator 60 to send the control voltage value to the voltage-controlled oscillator 60. Figure 2 As shown, the control voltage value is represented by CV in the circuit diagram. The second end of the fourteenth resistor R14 is connected to the power module so that the power module provides the first working power supply, and the corresponding voltage value of the first working power supply is 5V. The first end of the sixteenth resistor R16 and the first end of the seventeenth resistor are also connected to the analog-to-digital conversion module 30 so that the analog-to-digital conversion module 30 collects the divided voltage value, as shown in FIG. Figure 2 As shown, the divided voltage value is represented by CP_CV in the circuit diagram.

[0064] Through the above embodiments, it can be known that the second fast lock control circuit controls the narrowband loop filter circuit or the wideband loop filter circuit in combination with the first fast lock control circuit according to the lock instruction sent by the controller module to perform targeted processing of capture and lock, thereby improving data stability and communication efficiency.

[0065] In one embodiment, if Figure 1-3 As shown, the third fast lock control circuit includes a third control chip U3, an eighteenth resistor R18, a twentieth capacitor C20, a twenty-first capacitor C21, a nineteenth resistor R19, a twenty-second capacitor C22 and a twentieth resistor R20;

[0066] The first pin of the third control chip U3 is connected to the fourth fast lock control circuit; the third pin of the third control chip U3 is connected to the first end of the twentieth resistor R20; the fourth pin of the third control chip U3 is connected to the second end of the nineteenth resistor R19 and the first end of the twenty-second capacitor C22; the fifth pin of the third control chip U3 is connected to the second end of the eighteenth resistor R18, the first end of the twentieth capacitor C20 and the first end of the twenty-first capacitor C21; the sixth pin of the third control chip U3 is connected to the digital-to-analog conversion module 20; the second pin of the third control chip U3, the second end of the twentieth capacitor C20, the second end of the twenty-first capacitor C21, the second end of the twentieth resistor R20 and the second end of the twenty-second capacitor C22 are all grounded.

[0067] In this embodiment, if Figure 1-3 As shown, the model of the third control chip U3 can be WAS3157D; the specification of the eighteenth resistor R18 can be 5.6; the specification of the twentieth capacitor C20 can be 1uF; the specification of the twenty-first capacitor C21 can be 220pF; the specification of the nineteenth resistor R19 can be 33; the specification of the twenty-second capacitor C22 can be 47pF; the specification of the twentieth resistor R20 can be NC. It should be noted that the model, specification and connection relationship of each component in the third fast lock control circuit can be designed according to actual conditions.

[0068] The first end of the eighteenth resistor R18 is connected to the power module so that the power module provides the first working power, and the corresponding voltage value of the first working power is 5V. The first end of the nineteenth resistor R19 is connected to the controller module 10 to receive the fast lock enable instruction. Figure 3 As shown, the quick lock enabling instruction is represented by Lock_Ctrl in the circuit diagram.

[0069] Through the above embodiments, it can be known that the third fast lock control circuit provides an enable signal to the fourth fast lock control circuit according to the fast lock enable instruction sent by the controller module to start controlling the narrowband loop filter circuit or the broadband loop filter circuit to perform targeted processing on the first frequency value for fast charging, thereby improving data stability and communication efficiency.

[0070] In one embodiment, if Figure 1-3 As shown, the fourth fast lock control circuit includes a fourth control chip U4, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25 and a twenty-fifth capacitor C25;

[0071] The first pin of the fourth control chip U4 is connected to the first end of the twenty-third resistor R23, the second end of the twenty-third resistor R23 is connected to the second end of the second resistor R2, the first end of the fourth capacitor C4 and the first pin of the second control chip U2; the third pin of the fourth control chip U4 is connected to the first end of the twenty-fifth resistor R25, the second end of the twenty-fifth resistor R25 is connected to the second end of the sixth resistor R6, the first end of the ninth capacitor C9 and the third pin of the second control chip U2; the fourth pin of the fourth control chip U4 is connected to the second end of the twenty-fourth resistor R24, the first end of the twenty-fifth capacitor C25 The first end of the twenty-fourth resistor R24 ​​is connected to the controller module 10; the fifth pin of the fourth control chip U4 is connected to the second end of the twenty-first resistor R21, the second end of the twenty-third capacitor C23 and the second end of the twenty-fourth capacitor C24; the sixth pin of the fourth control chip U4 is connected to the second end of the twenty-second resistor R22, and the first end of the twenty-second resistor R22 is connected to the first pin of the third control chip U3; the second pin of the fourth control chip U4, the first end of the twenty-third capacitor C23, the first end of the twenty-fourth capacitor C24 and the second end of the twenty-fifth capacitor C25 are all grounded.

[0072] In this embodiment, if Figure 1-3 As shown, the model of the fourth control chip U4 can be WAS3157D; the specification of the 23rd capacitor C23 can be 1uF; the specification of the 24th capacitor C24 can be 220pF; the specification of the 21st resistor R21 can be 5.6; the specification of the 22nd resistor R22 can be 0; the specification of the 23rd resistor R23 is 0; the specification of the 24th resistor R24 ​​can be 33; the specification of the 25th resistor R25 can be 0; the specification of the 25th capacitor C25 can be 47pF. It should be noted that the model, specification and connection relationship of each component in the fourth fast lock control circuit can be designed according to actual conditions.

[0073] The first end of the 21st resistor R21 is connected to the power module so that the power module provides the first working power, and the corresponding voltage value of the first working power is 5V. The first end of the 24th resistor R24 ​​is connected to the controller module 10 to receive the fast charging instruction. Figure 3 As shown, the fast charging instruction is represented by Fastlock_Ctrl in the circuit diagram.

[0074] Through the above embodiments, it can be known that the fourth fast lock control circuit controls the narrowband loop filter circuit or the broadband loop filter circuit to perform targeted processing of fast charging according to the fast charging instruction sent by the controller module, thereby improving data stability and communication efficiency.

[0075] In one embodiment, if Figure 1-3 As shown, the digital-to-analog conversion module 20 includes a digital-to-analog converter, an amplifier chip U5, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a first inductor L1, a twenty-sixth capacitor C26, a twenty-seventh capacitor C27, a twenty-eighth resistor R28 and a twenty-ninth resistor R29;

[0076] The first and second pins of the amplifier chip U5 are both connected to the second end of the twenty-sixth resistor R26; the third pin of the amplifier chip U5 is connected to the first end of the twenty-ninth resistor R29, and the second end of the twenty-ninth resistor R29 is connected to the digital-to-analog converter and the second end of the twenty-eighth resistor R28; the fifth pin of the amplifier chip U5 is connected to the first end of the twenty-eighth resistor R28; the sixth and seventh pins of the amplifier chip U5 are connected to the second end of the twenty-seventh resistor R27, and the first end of the twenty-seventh resistor R27 is connected to the sixth pin of the third control chip U3 and the first end of the twenty-sixth resistor R26; the eighth pin of the amplifier chip U5 is connected to the first pin of the first inductor L1, the first end of the twenty-sixth capacitor C26 and the first end of the twenty-seventh capacitor C27; the fourth pin of the amplifier chip U5, the second end of the twenty-sixth capacitor C26 and the second end of the twenty-seventh capacitor C27 are all grounded.

[0077] In this embodiment, if Figure 1-3 As shown, the model of the amplifier chip U5 can be AD8566; the specification of the 26th resistor R26 can be 0; the specification of the 27th resistor R27 can be 0; the model of the first inductor L1 can be BLM03AX121SN1D; the specification of the 26th capacitor C26 can be 10uF; the specification of the 27th capacitor C27 can be 470pF; the specification of the 28th resistor R28 can be 0; the specification of the 29th resistor R29 can be 0. It should be noted that the model, specification and connection relationship of each component in the digital-to-analog conversion module 20 can be designed according to actual conditions.

[0078] The first end of the first inductor L1 is connected to the power module, so that the power module provides a second working power supply, and the corresponding voltage value of the second working power supply is 5V. Figure 3As shown, the second working power is represented by 5VA in the circuit diagram. The second end of the 29th resistor R29 and the second end of the 28th resistor are connected to the digital-to-analog converter to receive the first processing voltage value, such as Figure 3 As shown, the first processing voltage value is represented by DAC_CP_CV in the circuit diagram.

[0079] In one embodiment, if Figure 1-4 As shown, the analog-to-digital conversion module 30 includes an analog-to-digital conversion chip U6, a 30th resistor R30, a 28th capacitor C28, a 31st resistor R31, a 32nd resistor R32, a 33rd resistor R33, a 34th resistor R34, a second inductor L2, a third inductor L3, a fourth inductor L4, a 29th capacitor C29, a 30th capacitor C30, a 31st capacitor C31, a 32nd capacitor C32, a 33rd capacitor C33, a 34th capacitor C34, a 35th capacitor C35 and a 36th capacitor C36;

[0080] The first pin of the analog-to-digital conversion chip U6 is connected to the second end of the thirty-first resistor R31 and the first end of the thirty-first capacitor C31; the second pin of the analog-to-digital conversion chip U6 is connected to the second end of the thirty-second resistor R32 and the first end of the thirty-second capacitor C32; the third pin of the analog-to-digital conversion chip U6 is connected to the second end of the thirty-fourth resistor R34 and the first end of the thirty-third capacitor C33; the first end of the thirty-first resistor R31, the first end of the thirty-second resistor R32 and the first end of the thirty-fourth resistor R34 are all connected to the controller module 10; the fourth pin of the analog-to-digital conversion chip U6 is connected to the first pin of the second inductor L2, the second pin of the second inductor L2 is connected to the first pin of the third inductor L3, the first end of the twenty-ninth capacitor C29 and the first end of the thirtieth capacitor C30; the sixth pin of the analog-to-digital conversion chip U6 is connected to the first end of the thirty-fourth capacitor C34, the first end of the thirty-fifth capacitor C35, the first end of the thirty-fifth capacitor C36, the first end of the thirty-fifth capacitor C37, the first end of the thirty-fifth capacitor C38, the first end of the thirty-fifth capacitor C39, the first end of the thirty-fif ...9, the first end of the thirty-fifth capacitor C39, the first end of the thirty-fifth capacitor C39, the The first end of the thirty-sixth capacitor C36, the second pin of the fourth inductor L4 and the second pin of the fifth inductor L5 are connected; the seventh pin of the analog-to-digital conversion chip U6 is connected to the second end of the twenty-eighth capacitor C28 and the first end of the thirty-third resistor R33, and the second end of the thirty-third resistor R33 is connected to the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17; the eighth pin of the analog-to-digital conversion chip U6 is connected to the second end of the thirtieth resistor R30; the fifth pin of the analog-to-digital conversion chip U6, the first end of the thirtieth resistor R30, the first end of the twenty-eighth capacitor C28, the second end of the twenty-ninth capacitor C29, the second end of the thirtieth capacitor C30, the second end of the thirty-first capacitor C31, the second end of the thirty-second capacitor C32, the second end of the thirty-third capacitor C33, the second end of the thirty-fourth capacitor C34, the second end of the thirty-fifth capacitor C35 and the second end of the thirty-sixth capacitor C36 are all grounded.

[0081] In this embodiment, if Figure 1-4As shown, the model of the analog-to-digital conversion chip U6 may be ADS7042IRUGR; the specification of the 30th resistor R30 may be 33 1%; the specification of the 28th capacitor C28 may be 1500pF; the specification of the 31st resistor R31 may be 33; the specification of the 32nd resistor R32 may be 33; the specification of the 33rd resistor R33 may be 20 1%; the specification of the thirty-fourth resistor R34 can be 33; the model of the second inductor L2 can be BLM03AX121SN1D; the model of the third inductor L3 can be BLM03AX121SN1D; the specification of the fourth inductor L4 can be NC; the specification of the twenty-ninth capacitor C29 can be 1uF; the specification of the thirtieth capacitor C30 can be 47pF; the specification of the thirty-first capacitor C31 can be 47pF; the specification of the thirty-second capacitor C32 can be 47pF; the specification of the thirty-third capacitor C33 can be 47pF; the specification of the thirty-fourth capacitor C34 can be 470pF; the specification of the thirty-fifth capacitor C35 can be 1uF; the specification of the thirty-sixth capacitor C36 can be 10uF. It should be noted that the model, specification and connection relationship of each component in the analog-to-digital conversion module 30 can be designed according to actual conditions.

[0082] The second pin of the third inductor L3 is connected to the power module so that the power module provides a third working power supply. The corresponding voltage value of the third working power supply is 3.3V. Figure 4 As shown, the first processing voltage value is represented by 3V3D in the circuit diagram. The first pin of the fourth inductor L4 is connected to the power module, so that the power module provides a fourth working power supply, and the corresponding voltage value of the fourth working power supply is 3.3V. Figure 4 As shown, the fourth working power supply is represented by 3V3A_TX_FGU in the circuit diagram. The first pin of the fifth inductor L5 is connected to the power module so that the first working power supply is provided by the power module, and the corresponding voltage value of the first working power supply is 5V. The second end of the thirty-third resistor R33 is connected to the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17 to collect the divided voltage value. The first end of the thirty-first resistor R31 and the first end of the thirty-fourth resistor R34 are both connected to the controller module 10, and are used to receive the enable instruction and pointer instruction sent by the controller module 10 to start the acquisition process, such as Figure 4As shown, the enable instruction and the pointer instruction are represented by FGPA>ADC_SPI1_CE and FGPA>ADC_SPI1_CLK in the circuit diagram respectively. The first end of the thirty-second resistor R32 is connected to the controller module 10 to send the divided voltage value to the controller module 10 through the SPI bus, such as Figure 4 As shown, the SPI bus is represented by FGPA>ADC_SPI1_CI in the circuit diagram.

[0083] like Figure 5 As shown, the embodiment of the present invention provides a control method for a fast-lock frequency hopping frequency source based on a phase-locked loop frequency synthesis module as described in the above embodiment; please refer to Figure 5 , Figure 5 A flow chart of a method for controlling a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module provided in an embodiment of the present invention, wherein the method for controlling a fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module comprises:

[0084] S110, when receiving or sending communication data, the controller module configures a frequency table based on the communication data, sends a first frequency value in the frequency table to the phase detector module, sends a calibration instruction and a first voltage value corresponding to the first frequency value in the frequency table to the digital-to-analog converter, and sends a fast lock instruction to the loop filter module;

[0085] S120, the digital-to-analog conversion module converts and amplifies the received first voltage value based on the received calibration instruction to obtain a first processed voltage value, and sends the first processed voltage value to the loop filter module;

[0086] S130, the phase detector module generates an analog signal according to the received first frequency value, and sends the analog signal and the first frequency value to the loop filter module;

[0087] S140, the loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to reach a preset voltage value based on the received fast lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received fast lock instruction and the analog signal to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched, and a control voltage value is output to a voltage-controlled oscillator; and the control voltage value is divided to obtain a divided voltage value;

[0088] S150, the analog-to-digital conversion module collects the divided voltage value, performs conversion processing on it, obtains a target voltage value of the first frequency value, and sends the target voltage value to the controller module;

[0089] S160, the controller module updates the target voltage value to the voltage corresponding to the first frequency value in the frequency table;

[0090] S170, the voltage-controlled oscillator performs synthesis processing based on the control voltage value to obtain a target frequency sub-value;

[0091] S180: The controller module frequency-hops to a second frequency value in the frequency table based on the communication data until the voltage-controlled oscillator synthesizes each frequency value in the frequency table to obtain the corresponding target frequency sub-value.

[0092] In this embodiment, if Figure 1-5 As shown, the fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module is applied to a communication system, and the fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module includes a controller module, a digital-to-analog conversion module, an analog-to-digital conversion module and a phase-locked loop frequency synthesis module; the controller module is communicatively connected with the digital-to-analog conversion module, the analog-to-digital conversion module and the phase-locked loop frequency synthesis module; the phase-locked loop frequency synthesis module includes a phase detector module, a loop filter module and a voltage-controlled oscillator; the phase detector module is connected with the controller module, and is also connected with the loop filter module and the voltage-controlled oscillator; the loop filter module is also connected with the voltage-controlled oscillator, the digital-to-analog conversion module and the analog-to-digital conversion module.

[0093] The communication system refers to a data transmission system with a receiving function or a sending function, which can send and receive the communication data. For example, the communication system can be used in navigation and electronic countermeasure systems, cellular communications, satellite communications, microwave radio, radar systems, measurement and testing, tactical radio stations and other equipment; the digital-to-analog conversion module is used to perform digital-to-analog conversion and amplification processing on the first voltage value to obtain the first processed voltage value; the phase detector module includes a crystal oscillator, a control frequency register and a phase detector, the control frequency register includes a reference divider and a feedback divider, the crystal oscillator is connected to the reference divider, and the reference divider is connected to the phase detector. The phase detector is also connected to the feedback divider and the loop filter module to form a loop; the crystal oscillator is used to provide a reference frequency to the reference divider, for example, the reference frequency can be 19.2MHz; the control frequency register can confirm that the controller module sends the first frequency value or the second frequency value and other frequency values ​​to the reference divider or the feedback divider to control and lock the frequency according to the protocol defined in the specific situation; the phase detector is used to output the analog signal adjusted according to the input first frequency value or the second frequency value, etc., and the analog signal is a pulse signal generated by the error value compared by the phase detector.

[0094] The communication data is provided by the communication system; the frequency table is a corresponding calibrated table configured according to the communication data and initializes the frequency value and the voltage value according to the timetable, corresponding to the corresponding channel, for example, it can correspond to a channel of 100 MHz to 150 MHz or a channel of 150 MHz to 200 MHz; a general frequency hopping frequency table may include 40 to 1024 frequency points, such as a narrowband waveform of an ultra-short wave radio station has a total of 232 frequency points, or a very correct waveform has 1024 points, 256 points or 512 points; the first frequency value refers to the first frequency value in the frequency table, the second frequency value refers to the second frequency value in the frequency table, and so on; the calibration instruction is an instruction generated by the controller module when receiving the communication data to control the digital-to-analog conversion module; the first A voltage value is a voltage value corresponding to the first frequency value stored in the frequency table; the fast lock instruction is an instruction generated by the controller module when receiving the communication data to control the loop filter module; the fast lock instruction includes a fast lock enable instruction, a fast lock charging control instruction and a lock instruction, the fast lock enable instruction is used to control the loop filter module to start fast lock processing, the fast lock control instruction is used to control the loop filter module to perform fast charging processing or stop fast charging processing, and the lock instruction is used to control the loop filter module to perform locking processing; the preset voltage value refers to the voltage value determined by the loop filter module after the initialization processing, which can be set according to the actual situation, and corresponds to the charging time used by the loop filter module for fast charging processing.

[0095] The fast-lock frequency hopping source based on the phase-locked loop frequency synthesis module also includes a power supply module, which is connected to the controller module, the digital-to-analog conversion module, the analog-to-digital conversion module and the phase-locked loop frequency synthesis module, and is used to provide working power to the controller module, the digital-to-analog conversion module, the analog-to-digital conversion module and the phase-locked loop frequency synthesis module.

[0096] When receiving or sending communication data, the controller module configures a frequency table based on the communication data, and sends a first frequency value in the frequency table to the phase detector module, and sends a calibration instruction and a first voltage value corresponding to the first frequency value in the frequency table to the digital-to-analog converter, and sends a fast lock instruction to the loop filter module; the digital-to-analog conversion module converts and amplifies the received first voltage value based on the received calibration instruction to obtain a first processed voltage value, and sends the first processed voltage value to the loop filter module; the phase detector module generates an analog signal according to the received first frequency value, and sends the analog signal and the first frequency value to the loop filter module; the loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to a preset voltage value based on the received fast lock instruction and the first processed voltage value, and based on the received fast lock instruction and The analog signal controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched and a control voltage value is output to the voltage-controlled oscillator; and the control voltage value is divided to obtain a divided voltage value; the analog-to-digital conversion module collects the divided voltage value and converts it to obtain a target voltage value of the first frequency value, and sends the target voltage value to the controller module; the controller module updates the target voltage value to the voltage corresponding to the first frequency value in the frequency table; the voltage-controlled oscillator performs synthesis processing based on the control voltage value to obtain a target frequency sub-value; the controller module hops to a second frequency value in the frequency table based on the communication data until the voltage-controlled oscillator synthesizes each frequency value in the frequency table to obtain the corresponding target frequency sub-value.

[0097] Specifically, the fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module includes two working modes, namely, a narrowband frequency hopping mode and a broadband frequency modulation mode, and the narrowband frequency hopping mode and the broadband frequency modulation mode are determined according to the communication data; that is, the controller module selects the narrowband frequency hopping mode or the broadband frequency modulation mode according to the communication data to determine the working mode.

[0098] When in the narrowband frequency hopping mode, that is, receiving the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the high-level lock instruction sent by the controller module, the first processing voltage value sent by the digital-to-analog conversion module, and the analog signal and the first frequency value sent by the phase detector module, the loop filter module starts to select the broadband filter circuit to quickly capture and lock the first frequency value according to the high-level lock instruction and the analog signal to obtain the locking result. At the same time, the low-level fast lock enable instruction, the low-level fast lock charge control instruction and the first processing voltage value are used to select the narrowband loop filter circuit for fast charging. After reaching the preset voltage value, and the locking result is successful locking, the broadband filter circuit is controlled to switch to the narrowband loop filter circuit, thereby realizing the secondary narrowband fast lock of the phase-locked loop frequency synthesis module.

[0099] When in the broadband frequency hopping mode, that is, receiving the low-level fast lock enable instruction, the high-level fast lock charge control instruction and the low-level lock instruction sent by the controller module, the first processing voltage value sent by the digital-to-analog conversion module, and the analog signal and the first frequency value sent by the phase detector module, the loop filter module starts to select the narrowband filter circuit to quickly capture and lock the first frequency value according to the low-level lock instruction and the analog signal to obtain the locking result. At the same time, the low-level fast lock enable instruction, the high-level fast lock charge control instruction and the first processing voltage value are used to select the broadband loop filter circuit for fast charging. After reaching the preset voltage value, if the locking result is successful locking, the narrowband filter circuit is controlled to switch to the broadband loop filter circuit, thereby realizing the secondary broadband fast lock of the phase-locked loop frequency synthesis module.

[0100] By implementing the embodiment of the present invention, in the process of quickly charging the narrowband loop filter circuit or the broadband loop filter circuit to reach the preset voltage value, the narrowband loop filter circuit or the broadband loop filter circuit is used to quickly lock the first frequency value to obtain a locking result. Therefore, charging and locking are performed simultaneously, which reduces phase noise, spurious and power consumption, saves fast locking time, and thus improves communication efficiency.

[0101] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above method and each module can refer to the corresponding description in the aforementioned fast-lock frequency hopping frequency source embodiment based on the phase-locked loop frequency synthesis module. For the convenience and conciseness of the description, it will not be repeated here.

[0102] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A fast-lock frequency hopping source based on a phase-locked loop frequency synthesis module, applied to a communication system, characterized in that: The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module includes a controller module, a digital-to-analog conversion module, an analog-to-digital conversion module and a phase-locked loop frequency synthesis module; the controller module is communicatively connected with the digital-to-analog conversion module, the analog-to-digital conversion module and the phase-locked loop frequency synthesis module; the phase-locked loop frequency synthesis module includes a phase detector module, a loop filter module and a voltage-controlled oscillator; the phase detector module is connected with the controller module, and is also connected with the loop filter module and the voltage-controlled oscillator; the loop filter module is also connected with the voltage-controlled oscillator, the digital-to-analog conversion module and the analog-to-digital conversion module; When receiving the quick lock instruction sent by the controller module, the first processing voltage value sent by the digital-to-analog conversion module, and the analog signal and the first frequency value sent by the phase detector module, the loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to reach a preset voltage value based on the received quick lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received quick lock instruction and the analog signal to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched.

2. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 1, characterized in that: The loop filter module includes a quick lock control circuit, a narrowband loop filter circuit and a broadband loop filter circuit; the quick lock control circuit includes a first quick lock control circuit, a second quick lock control circuit, a third quick lock control circuit and a fourth quick lock control circuit; the first quick lock control circuit is connected to the narrowband loop filter circuit and the broadband loop filter circuit, and is also connected to the phase detector module and the controller module; the second quick lock control circuit is connected to the narrowband loop filter circuit and the broadband loop filter circuit, and is also connected to the controller module, the voltage-controlled oscillator and the analog-to-digital conversion module; the third quick lock control circuit is connected to the digital-to-analog conversion module, and is also connected to the fourth quick lock control circuit and the controller module; the fourth quick lock control circuit is also connected to the second quick lock control circuit, the narrowband loop filter circuit and the broadband loop filter circuit.

3. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 2, characterized in that: The narrowband loop filter circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor, a third resistor, a third capacitor, a fourth capacitor, a fourth resistor, a fifth capacitor and a sixth capacitor; The first end of the first resistor is connected to the first fast lock control circuit, the first end of the first capacitor, the first end of the second capacitor, and the first end of the third resistor; the second end of the first resistor is connected to the first end of the second resistor and the first end of the third capacitor; the second end of the second capacitor is connected to the second end of the third resistor and the first end of the fourth resistor; the second end of the fourth resistor is connected to the first end of the fifth capacitor, the first end of the sixth capacitor, and the second end of the third capacitor; the second end of the second resistor is connected to the first end of the fourth capacitor, the fourth fast lock control circuit, and the second fast lock control circuit; the second end of the first capacitor, the second end of the fourth capacitor, the second end of the fifth capacitor, and the second end of the sixth capacitor are all grounded.

4. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 3, characterized in that: The broadband loop filter circuit includes a fifth resistor, a sixth resistor, a seventh capacitor, an eighth capacitor, a seventh resistor, a ninth capacitor, a tenth capacitor, an eighth resistor, an eleventh capacitor and a twelfth capacitor; The first end of the fifth resistor is connected to the first fast lock control circuit, the first end of the seventh capacitor, the first end of the eighth capacitor, and the first end of the seventh resistor; the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the tenth capacitor; the second end of the eighth capacitor is connected to the second end of the seventh resistor and the first end of the eighth resistor; the second end of the eighth resistor is connected to the first end of the eleventh capacitor, the first end of the twelfth capacitor, and the second end of the tenth capacitor; the second end of the sixth resistor is connected to the first end of the ninth capacitor, the fourth fast lock control circuit, and the second fast lock control circuit; the second end of the seventh capacitor, the second end of the ninth capacitor, the second end of the eleventh capacitor, and the second end of the twelfth capacitor are all grounded.

5. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 4, characterized in that: The first fast lock control circuit includes a first control chip, a thirteenth capacitor, a fourteenth capacitor, a ninth resistor, a tenth resistor, an eleventh resistor and a fifteenth capacitor; The first pin of the first control chip is connected to the first end of the first capacitor, the first end of the second capacitor, the first end of the third resistor and the first end of the first resistor; the third pin of the first control chip is connected to the first end of the seventh capacitor, the first end of the eighth capacitor, the first end of the seventh resistor and the first end of the fifth resistor; the fourth pin of the first control chip is connected to the second end of the eleventh resistor and the first end of the fifteenth capacitor, and the first end of the eleventh resistor is connected to the controller module; the fifth pin of the first control chip is connected to the second end of the ninth resistor, the second end of the thirteenth capacitor and the second end of the fourteenth capacitor; the sixth pin of the first control chip is connected to the second end of the tenth resistor; the first end of the tenth resistor is connected to the phase detector module; the second pin of the first control chip, the first end of the thirteenth capacitor, the first end of the fourteenth capacitor and the second end of the fifteenth capacitor are all grounded.

6. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 5, characterized in that: The second fast lock control circuit includes a second control chip, a sixteenth capacitor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a seventeenth capacitor, an eighteenth capacitor, a sixteenth resistor, a seventeenth resistor and a nineteenth capacitor; The first pin of the second control chip is connected to the second end of the second resistor, the first end of the fourth capacitor and the fourth fast lock control circuit; the third pin of the second control chip is connected to the second end of the sixth resistor, the first end of the ninth capacitor and the fourth fast lock control circuit; the fourth pin of the second control chip is connected to the second end of the sixteenth capacitor and the first end of the twelfth resistor, and the second end of the twelfth resistor is connected to the controller module; the fifth pin of the second control chip is connected to the first end of the fourteenth resistor, the first end of the seventeenth capacitor and the first end of the eighteenth capacitor; the sixth pin of the first control chip is connected to the first end of the thirteenth resistor, and the second end of the thirteenth resistor is connected to the voltage-controlled oscillator and the first end of the fifteenth resistor; the second end of the fifteenth resistor is connected to the second end of the sixteenth resistor and the first end of the nineteenth capacitor, and the first end of the sixteenth resistor is connected to the analog-to-digital conversion module and the first end of the seventeenth resistor; the second pin of the second control chip, the first end of the sixteenth capacitor, the second end of the seventeenth capacitor, the second end of the eighteenth capacitor, the second end of the seventeenth resistor and the second end of the nineteenth capacitor are all grounded.

7. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 6, characterized in that: The third fast lock control circuit includes a third control chip, an eighteenth resistor, a twentieth capacitor, a twenty-first capacitor, a nineteenth resistor, a twenty-second capacitor and a twentieth resistor; The first pin of the third control chip is connected to the fourth fast lock control circuit; the third pin of the third control chip is connected to the first end of the twentieth resistor; the fourth pin of the third control chip is connected to the second end of the nineteenth resistor and the first end of the twenty-second capacitor; the fifth pin of the third control chip is connected to the second end of the eighteenth resistor, the first end of the twentieth capacitor and the first end of the twenty-first capacitor; the sixth pin of the third control chip is connected to the digital-to-analog conversion module; the second pin of the third control chip, the second end of the twentieth capacitor, the second end of the twenty-first capacitor, the second end of the twentieth resistor and the second end of the twenty-second capacitor are all grounded.

8. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 7, characterized in that: The fourth fast lock control circuit includes a fourth control chip, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor and a twenty-fifth capacitor; The first pin of the fourth control chip is connected to the first end of the twenty-third resistor, the second end of the second resistor of the twenty-third resistor is connected to the second end, the first end of the fourth capacitor and the first pin of the second control chip; the third pin of the fourth control chip is connected to the first end of the twenty-fifth resistor, the second end of the twenty-fifth resistor is connected to the second end of the sixth resistor, the first end of the ninth capacitor and the third pin of the second control chip; the fourth pin of the fourth control chip is connected to the second end of the twenty-fourth resistor, the first end of the twenty-fifth capacitor, and the first end of the twenty-fourth resistor is connected to the controller module; the fifth pin of the fourth control chip is connected to the second end of the twenty-first resistor, the second end of the twenty-third capacitor and the second end of the twenty-fourth capacitor; the sixth pin of the fourth control chip is connected to the second end of the twenty-second resistor, the first end of the twenty-second resistor is connected to the first pin of the third control chip; the second pin of the fourth control chip, the first end of the twenty-third capacitor, the first end of the twenty-fourth capacitor and the second end of the twenty-fifth capacitor are all grounded.

9. The fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module according to claim 7, characterized in that: The digital-to-analog conversion module includes a digital-to-analog converter, an amplifier chip, a twenty-sixth resistor, a twenty-seventh resistor, a first inductor, a twenty-sixth capacitor, a twenty-seventh capacitor, a twenty-eighth resistor and a twenty-ninth resistor; The first pin and the second pin of the amplifier chip are both connected to the second end of the twenty-sixth resistor; the third pin of the amplifier chip is connected to the first end of the twenty-ninth resistor, and the second end of the twenty-ninth resistor is connected to the digital-to-analog converter and the second end of the twenty-eighth resistor; the fifth pin of the amplifier chip is connected to the first end of the twenty-eighth resistor; the sixth pin and the seventh pin of the amplifier chip are connected to the second end of the twenty-seventh resistor, and the first end of the twenty-seventh resistor is connected to the sixth pin of the third control chip and the first end of the twenty-sixth resistor; the eighth pin of the amplifier chip is connected to the first pin of the first inductor, the first end of the twenty-sixth capacitor and the first end of the twenty-seventh capacitor; the fourth pin of the amplifier chip, the second end of the twenty-sixth capacitor and the second end of the twenty-seventh capacitor are all grounded.

10. The fast-lock frequency hopping source based on the phase-locked loop frequency synthesis module according to claim 6, characterized in that: The analog-to-digital conversion module includes an analog-to-digital conversion chip, a 30th resistor, a 28th capacitor, a 31st resistor, a 32nd resistor, a 33rd resistor, a 34th resistor, a second inductor, a third inductor, a fourth inductor, a 29th capacitor, a 30th capacitor, a 31st capacitor, a 32nd capacitor, a 33rd capacitor, a 34th capacitor, a 35th capacitor and a 36th capacitor; The first pin of the analog-to-digital conversion chip is connected to the second end of the thirty-first resistor and the first end of the thirty-first capacitor; the second pin of the analog-to-digital conversion chip is connected to the second end of the thirty-second resistor and the first end of the thirty-second capacitor; the third pin of the analog-to-digital conversion chip is connected to the second end of the thirty-fourth resistor and the first end of the thirty-third capacitor; the first end of the thirty-first resistor, the first end of the thirty-second resistor and the first end of the thirty-fourth resistor are all connected to the controller module; the fourth pin of the analog-to-digital conversion chip is connected to the first pin of the second inductor, the second pin of the second inductor is connected to the first pin of the third inductor, the first end of the twenty-ninth capacitor and the first end of the thirtieth capacitor; the sixth pin of the analog-to-digital conversion chip is connected to the first end of the thirty-fourth capacitor, the first end of the thirty-fifth capacitor , the first end of the thirty-sixth capacitor, the second pin of the fourth inductor and the second pin of the fifth inductor are connected; the seventh pin of the analog-to-digital conversion chip is connected to the second end of the twenty-eighth capacitor and the first end of the thirty-third resistor, and the second end of the thirty-third resistor is connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor; the eighth pin of the analog-to-digital conversion chip is connected to the second end of the thirtieth resistor; the fifth pin of the analog-to-digital conversion chip, the first end of the thirtieth resistor, the first end of the twenty-eighth capacitor, the second end of the twenty-ninth capacitor, the second end of the thirtieth capacitor, the second end of the thirty-first capacitor, the second end of the thirty-second capacitor, the second end of the thirty-third capacitor, the second end of the thirty-fourth capacitor, the second end of the thirty-fifth capacitor and the second end of the thirty-sixth capacitor are all grounded.

11. A method for controlling a fast-lock frequency hopping frequency source based on a phase-locked loop frequency synthesis module as claimed in any one of claims 1 to 10, characterized in that: The control method of the fast-lock frequency hopping frequency source based on the phase-locked loop frequency synthesis module includes: When receiving or sending communication data, the controller module configures a frequency table based on the communication data, sends a first frequency value in the frequency table to the phase detector module, sends a calibration instruction and a first voltage value corresponding to the first frequency value in the frequency table to the digital-to-analog converter, and sends a fast lock instruction to the loop filter module; The digital-to-analog conversion module converts and amplifies the received first voltage value based on the received calibration instruction to obtain a first processed voltage value, and sends the first processed voltage value to the loop filter module; The phase detector module generates an analog signal according to the received first frequency value, and sends the analog signal and the first frequency value to the loop filter module; The loop filter module quickly charges the narrowband loop filter circuit or the broadband loop filter circuit in the loop filter module to reach a preset voltage value based on the received fast lock instruction and the first processing voltage value, and controls the narrowband loop filter circuit or the broadband loop filter circuit to quickly lock the first frequency value based on the received fast lock instruction and the analog signal to obtain a locking result; if the locking result is successful, the narrowband loop filter circuit or the broadband loop filter circuit is switched, and a control voltage value is output to a voltage-controlled oscillator; and the control voltage value is divided to obtain a divided voltage value; The analog-to-digital conversion module collects the divided voltage value, performs conversion processing on it, and obtains a target voltage value of the first frequency value, and sends the target voltage value to the controller module; The controller module updates the target voltage value to the voltage corresponding to the first frequency value in the frequency table; The voltage-controlled oscillator performs synthesis processing based on the control voltage value to obtain a target frequency sub-value; The controller module frequency-hops to a second frequency value in the frequency table based on the communication data until the voltage-controlled oscillator synthesizes each frequency value in the frequency table to obtain the corresponding target frequency sub-value.

Images