Wiring method and device for chip layout, equipment and storage medium

Abstract

The invention discloses a wiring method and device for a chip layout, equipment and a storage medium, and particularly relates to the technical field of quantum. The method comprises the steps that wiring from a first wiring port to a second wiring port on a chip layout is determined, the wiring comprises tangent segments and arcs which are alternately connected, the straight line where the tangent segments are located is tangent to the circle where the arcs connected with the tangent segments are located, each arc takes a vertex on the chip layout as the circle center and bypasses a component corresponding to the vertex, and the tangent segments are arranged on the first wiring port and the second wiring port; the vertex is a point corresponding to a component passed between the first wiring port and the second wiring port; arcs included in the wiring are identified, a target arc is determined, the target arc refers to an arc with a rotation phenomenon, and the rotation phenomenon refers to that the central angle corresponding to the arc is larger than a threshold value; and removing the target arc, and adjusting the wiring to obtain the adjusted wiring. According to the method, the wiring accuracy is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of quantum technology, and in particular to a wiring method, device, equipment and storage medium for a chip layout. Background Art

[0002] In the field of quantum technology, it is generally necessary to prepare the corresponding quantum chip by designing the chip layout. In the chip layout, the layout of components, the connection method of components, etc. can be designed.

[0003] In the related art, when routing components that should be connected in a chip layout, the components that need to be bypassed are usually determined based on the source port and the destination port, and the components are bypassed by laying arc lines at the components that need to be bypassed.

[0004] In the above-mentioned related technologies, the layout of the arc line may go around in circles, that is, the central angle of the arc line laid out around the components that need to be bypassed is too large, causing the arc line to overlap with other lines, thereby making the determined wiring relatively unreasonable. Summary of the invention

[0005] The embodiment of the present application provides a chip layout wiring method, device, equipment and storage medium, which can improve the accuracy of wiring. The technical solution is as follows:

[0006] According to one aspect of an embodiment of the present application, a wiring method for a chip layout is provided, the method comprising:

[0007] Obtaining a wiring from a first wiring port to a second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, each circular arc has a vertex on the chip layout as a center and bypasses a component corresponding to the vertex, and the vertex is a point corresponding to a component passing between the first wiring port and the second wiring port;

[0008] Identify the arc included in the wiring to determine a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold;

[0009] The target arc is eliminated, and the wiring is adjusted to obtain an adjusted wiring.

[0010] According to one aspect of an embodiment of the present application, a chip is provided. The chip is processed based on a chip layout, and the wiring of the chip layout is obtained using the wiring method of the above-mentioned chip layout.

[0011] According to one aspect of an embodiment of the present application, a wiring device for a chip layout is provided, the device comprising:

[0012] a wiring determination module, used to determine the wiring from the first wiring port to the second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, each circular arc takes a vertex on the chip layout as the center and bypasses the component corresponding to the vertex, and the vertex is a point corresponding to the component passing between the first wiring port and the second wiring port;

[0013] An arc determination module, used for identifying the arc included in the wiring, and determining a target arc, wherein the target arc refers to an arc with a spinning phenomenon, wherein the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold value;

[0014] The wiring adjustment module is used to remove the target arc and adjust the wiring to obtain the adjusted wiring.

[0015] According to one aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein a computer program is stored in the memory, and the processor is used to execute the computer program to implement the wiring method of the above-mentioned chip layout.

[0016] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the wiring method of the above-mentioned chip layout.

[0017] According to one aspect of an embodiment of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being loaded and executed by a processor to implement the above-mentioned chip layout wiring method.

[0018] The technical solution provided in the embodiments of the present application can bring the following beneficial effects:

[0019] By identifying arcs in the wiring, arcs with central angles greater than a threshold are identified and deleted, so that the adjusted wiring does not include arcs with central angles greater than the threshold, that is, all arcs with circling phenomena are deleted, and arcs without circling phenomena are retained, thereby avoiding the phenomenon of overlapping of lines determined by the wiring due to circling, making the wiring on the chip layout more reasonable and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a topological wiring provided by the related technology;

[0021] Figure 2 It is a wiring schematic diagram provided by the related art;

[0022] Figure 3 It is a schematic diagram of a spinning phenomenon provided by the related art;

[0023] Figure 4 It is a schematic diagram from topological wiring to wiring provided by related technology;

[0024] Figure 5 It is a schematic diagram of another circling phenomenon provided by the related art;

[0025] Figure 6 This is a schematic diagram of avoiding the phenomenon of spinning in circles provided by an embodiment of the present application;

[0026] Figure 7 It is a flow chart of a wiring method of a chip layout provided by an embodiment of the present application;

[0027] Figure 8 is a schematic diagram of a target arc provided by an embodiment of the present application;

[0028] Fig. 9 is a flow chart of a chip layout wiring method provided by another embodiment of the present application;

[0029] Fig.10 is a schematic diagram of a target arc provided by another embodiment of the present application;

[0030] Fig.11 is a flow chart of a chip layout wiring method provided by another embodiment of the present application;

[0031] Fig.12 is a flow chart of a chip layout wiring method provided by another embodiment of the present application;

[0032] Fig.13 is a flow chart of a chip layout wiring method provided by another embodiment of the present application;

[0033] Fig.14 It is a block diagram of a wiring method of a chip layout provided by an embodiment of the present application;

[0034] Fig.15 is a schematic diagram of avoiding the phenomenon of spinning in circles provided by another embodiment of the present application;

[0035] Fig.16 is a block diagram of a wiring device for a chip layout provided by an embodiment of the present application;

[0036] Fig.17is a block diagram of a wiring device for a chip layout provided by another embodiment of the present application;

[0037] Fig.18 It is a structural block diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] Before introducing the embodiments of the present application, some terms involved in the present application are first explained.

[0040] 1. Superconducting quantum chip: The central processing unit of a superconducting quantum computer. A quantum computer is a machine that uses the principles of quantum mechanics to perform calculations. Based on the superposition principle and quantum entanglement of quantum mechanics, quantum computers have strong parallel processing capabilities and can solve some problems that are difficult for classical computers to calculate. The zero resistance characteristics of superconducting quantum bits and the manufacturing process that is close to that of integrated circuits make the quantum computing system built using superconducting quantum bits one of the most promising systems for realizing practical quantum computing.

[0041] 2. Electronic Design Automation (EDA): It is a design method in the electronic field, which refers to the use of computer software (design-aided software) to complete design work in the electronic field and realize design automation. It includes, for example, the functional design, functional verification, layout and routing of integrated circuit chips. The software tools used in this category are collectively referred to as EDA tools.

[0042] 3. Automatic routing: Use software to automatically complete the layout of circuits and chip designs, and connect components according to rules and requirements. It is mostly used in large-scale and ultra-large-scale integrated circuit design. It is one of the links and is usually performed after the layout is completed.

[0043] 4. Layout: Also known as circuit layout, it is a design drawing that describes how the components in the circuit are laid out, placed, and connected. It is a planar geometric shape description of the actual physical situation of the circuit. The design of the layout must comply with constraints such as manufacturing process, timing, area, power consumption, etc. The layout design file contains the shape, area, and position information of each hardware unit on the chip.

[0044] 5. Component: A general term for elements and devices, which are electronic components and elements in the circuit, such as resistors, capacitors, inductors, etc.

[0045] 6. Co-Planar Waveguide (CPW): It is a microwave planar transmission line with superior performance and convenient processing, used to transmit microwave signals. A large number of co-planar waveguide technologies are used in superconducting quantum chips.

[0046] 7. Radius of curvature: The radius of curvature is the reciprocal of the curvature and is represented by R. For a curve, the radius of curvature is equal to the radius of the arc closest to the curve at that point.

[0047] 8. Microwave: refers to electromagnetic waves with wavelengths between infrared and radio waves, and frequencies between 300MHz and 300GHz, which are higher than radio frequencies and are also called ultra-high frequency electromagnetic waves. Microwaves are used in radar, wireless networks, and sensors. In superconducting quantum, microwaves in the resonant cavity can carry and store quantum states, thereby using them for quantum information processing.

[0048] 9. Phase: It is a measurement that describes the change in signal waveform, and its unit is angle (deg) or radian (rad).

[0049] 10. Topology: Topology is a discipline that studies topological space. It is developed from geometry and set theory. It mainly studies the properties of geometric figures or spaces that remain unchanged after continuous changes in shape. It studies concepts such as space, dimension, and transformation. Topology only considers the positional relationship between objects rather than the shape and size. Topological wiring is a wiring method based on topological structure and topological network.

[0050] 11. Resonance: The full name is simple harmonic vibration, also known as resonance in physics. In electronics, when the input impedance and output impedance of the circuit are almost 0 and the transfer function is close to 1, the impedance or admittance of the circuit elements cancel each other out, and the circuit will oscillate at a specific frequency (resonance frequency), causing the circuit to generate a higher current and voltage than the input. This phenomenon is called electrical resonance or circuit resonance. In quantum mechanics, the resonance of particles is similar to the situation in classical physics.

[0051] In the related art, the topological routing algorithm is another type of routing algorithm different from the grid routing algorithm. The topological routing process can be roughly divided into the following stages: 1) Perform mincut (minimum cut algorithm) on the circuit layout that has been placed (components are placed) to decompose it into independent chip layouts; 2) Perform multi-layer planning on a single chip, and decompose it into independent circuits on each layer by introducing cross-layer auxiliary devices such as through holes. Generally speaking, the positions of components are fixed, and the positions of components on different layers will not intersect; 3) Triangulate the devices of each layer of the circuit, and introduce a topological algorithm to realize the topological direction between multiple pairs of routing ports. The topological direction is a pair of lines that connect the source port and the destination port and bypass the existing devices. The routing port includes the source port and the destination port, where the source port is the pin (the control / read pin of the bit), and the destination port is the pad (the pad around the chip). The routing process is to find a suitable line to connect the pin and the pad. The routing port is also a type of device on the chip layout, which is equivalent to two special devices. It is necessary to determine the pins and pads first, and then the routing process is to find the lines connecting the pins and pads, and not intersecting with other devices and the route is as short as possible. That is, first merge the polygons abstracted from the devices of different layers into the same layer (different devices generally do not intersect), and then triangulate all polygons (Delaunay Triangulation, DT for short). After triangulation, you will get the lines between the points of the polygons corresponding to many components; 4) Generate the corresponding final routing for each set of topological routing. One requirement of routing is to bypass these components, so starting from the upper end point of the polygon and taking a certain distance along the lines of these triangulations, you can determine the path required for routing. In some embodiments, triangulation is implemented by a constrained triangulation (Constrained Delaunay Triangulation, CDT for short) algorithm based on the DT algorithm, that is, adding some restrictive edges on the basis of DT. The purpose of the DT algorithm is to divide the plane point set into triangles, and the circumscribed circle of each triangle cannot contain the fixed points of other triangles.

[0052] In the above-mentioned related technologies, when converting from topological routing to routing, due to some algorithmic blind spots, the converted routing may have a circuitous phenomenon. Figure 1 As shown in FIG. 1 , it is the algorithm output of the topological routing, wherein a plurality of initial signal lines 110 formed by initial path points pass through the triangulated mesh 100 formed by components. Figure 2As shown, it is a normal wiring, and there is no cross-over or overlap among the normally laid multiple lines 210. In some embodiments, according to the components and wiring ports in the chip layout, the triangulation line and the square obstacle to be bypassed (the component to be bypassed) are determined, and then the appropriate distance is selected according to the spacing along the triangulation line from the fixed point of the obstacle. The spacing here is the shortest spacing between different lines and the shortest spacing between devices that are specified in advance. Figure 2 What is shown in the figure is that when multiple lines take different distances to bypass the same obstacle, multiple topological paths are finally realized. The intersection of the triangulation line and the initial signal line is the topological path point of the different lines (multiple lines need to be laid at the same time) found in this step. Figure 3 As shown, it is an abnormal wiring, in which the laid line 310 is circled at 300, resulting in the laid line 310 and the laid line 320 crossing at 300.

[0053] Specifically, in the routing algorithm of the related art, the path points around each signal line that needs to be routed are first determined, and then these path points are traversed to find the appropriate path points, and based on the specific circumstances of the triangulation endpoints near the path points (the triangulation endpoints are the vertices of a series of line segments after the multiple polygons abstracted from all (devices) on the input chip layout and triangulated), it is determined which triangulation endpoints need to be bypassed, that is, the center, radius, starting point and ending point of a series of arcs on the final routing path are determined, and finally these arcs are connected by tangents to form the final signal line. Among them, the triangulation endpoints here are also the vertices in the embodiments of the present application, and the two represent the same meaning, and are both used to represent the vertices of the polygons corresponding to the components. Such as Figure 4 As shown, the topology routing 400 includes multiple path points obtained according to the topology algorithm. Optionally, the routing 410 is determined according to the topology routing 400. In some embodiments, the routing may go around in circles. Figure 5 As shown in FIG. 5 , one of the two CPW lines arranged is spun around and crosses with the other CPW line at 510 . Figure 3 ,still Figure 5 The consequences of circling are obvious. Not only is the CPW signal interrupted due to the wrong wiring, but the adjacent wiring is also interrupted due to the wiring circling. Therefore, it is necessary to solve this defect from topology routing algorithm to routing.

[0054] The technical solution provided by the present application proposes a general supplementary algorithm to solve such spinning problems by deeply analyzing the topology routing to routing rendering algorithm. Figure 6As shown, sub-figure (a) shows the phenomenon of line crossing caused by circling, and sub-figure (b) shows the line normally laid out to avoid circling. The present application realizes the transition from sub-figure (a) to sub-figure (b). Based on topological wiring, the present application has developed an algorithm that can automatically identify the phenomenon of signal lines circling during wiring and reasonably avoid it, so that the automatically laid signal lines will not intersect or be too close due to the above reasons, thus meeting the automatic wiring requirements of superconducting quantum chips. Therefore, the present application has the following innovations: EDA automatic wiring for superconducting quantum chips, automatic identification of signal line circling, and selection of only appropriate wiring paths according to different circling situations.

[0055] Please refer to Figure 7 , which shows a flow chart of a wiring method for a chip layout provided by an embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC (Personal Computer), a tablet computer, a server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided by the present embodiment is implemented by the computer program. Figure 7 As shown, the method may include at least one of the following steps 710 to 730.

[0056] Step 710, obtaining a wiring from a first wiring port to a second wiring port on a chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, wherein the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, and each circular arc takes a vertex on the chip layout as the center and bypasses the component corresponding to the vertex, and the vertex is the point corresponding to the component passing between the first wiring port and the second wiring port.

[0057] The chip layout is a design drawing that describes how the components in the circuit are laid out, placed, and connected. It is a planar geometric shape description of the physical situation of the real circuit. The chip layout can be the chip layout of a quantum chip, such as the chip layout of a superconducting quantum chip. Superconducting quantum chips use a large number of coplanar waveguide technologies to transmit microwave signals. The layout design file of the chip layout contains information such as the shape, area, and position of each hardware unit on the chip. After automatic wiring, wiring information connecting each point can be added to the layout design file, and finally a layout design file with wiring information is generated. The above wiring information can include the location information of each component, and can also include the location information of how the components are connected.

[0058] In some embodiments, the first wiring port and the second wiring port are considered to be a pair of wiring ports. Among them, the first wiring port can be considered as the starting position of wiring, and the second wiring port can be considered as the ending position of wiring. Generally speaking, in a chip layout containing multiple components, multiple pairs of wiring ports should be included. The embodiment of the present application does not limit the number of wiring ports, nor does it limit the number of wiring ports that need to be wired. In the embodiment of the present application, only one pair of wiring ports is used for wiring as an example, and the wiring of other pairs of wiring ports refers to the embodiment of the present application. When the wiring between all pairs of wiring ports in the chip layout is determined to be completed, the chip layout is considered to be wired. Of course, which specific ports should be connected is set in advance by the developer or determined in advance according to the algorithm. The embodiment of the present application performs subsequent wiring work only on the premise that which wiring ports are determined to be connected.

[0059] The first wiring port: is a component or a part of the component. In some embodiments, the first wiring port is a special component where the wiring starts. In other embodiments, the first wiring port is a pin of the component. Exemplarily, the first wiring port is a pin (bit control / read pin). In some embodiments, different components in the chip layout and different pins in the components have different characteristics. Assuming that component a and component b need to be connected, first find component a, then find a pin that meets the pin characteristics from the various pins of component a, and use the pin as the first wiring port.

[0060] The second wiring port: is a component or a part of the component. In some embodiments, the second wiring port is a special component, which is where the wiring ends. In other embodiments, the second wiring port is a pad of the component. Exemplarily, the second wiring port is a pad (pads around the chip). Optionally, the wiring process is to find a suitable line to connect the pin and the pad. Assuming that component a and component b need to be connected, after finding a pin that meets the pin characteristics from each pin of component a as the first wiring port, find the pad of component b and use the pad as the second wiring port.

[0061] In some embodiments, there may be many components between the first wiring port and the second wiring port, so it is necessary to bypass the components in the middle. Figure 2 As shown, rectangle 200 represents a component on the chip layout. Generally speaking, when designing a chip layout, the components are graphically represented, that is, the components are mapped to various graphics in the chip layout, such as Figure 2The rectangle 200 shown is the result of a component being graphed. Different components may correspond to different graphics, and the number of vertices of different graphics may be different. When routing, it is necessary to consider which vertices of the rectangle 200 are bypassed. In some embodiments, when routing, the component is bypassed by laying out arc lines at the vertices that need to be bypassed. Therefore, when passing through multiple components, there are multiple vertices that need to be bypassed, that is, there are multiple arcs. In some embodiments, the vertex is the endpoint of the triangulation line obtained after the constrained triangulation algorithm is performed on the components on the chip layout, that is, the triangulation endpoint. Exemplarily, the point corresponding to the component, that is, the triangulation endpoint, refers to the vertex of the polygon corresponding to the component. The polygon corresponding to the component here refers to the representation of the real component with a polygon at the algorithm level. The polygon represents the size and shape of the component, and the real component and the polygon on the chip layout are one-to-one corresponding.

[0062] In some embodiments, the wiring in step 710 may be the initial wiring or the wiring in the adjustment process, and the present application does not limit this. Among them, the initial wiring refers to the wiring that has not been adjusted for the first time determined according to the first wiring port and the second wiring port. In some embodiments, the initial wiring includes at least one arc with the vertex as the center and at least two tangent segments connecting the arcs. For example, when there is only one component that needs to be bypassed, the arc corresponding to the vertex of the component is determined, the starting position of the arc and the line connecting the first wiring port are tangent to the arc, and the ending position of the arc and the line connecting the second wiring port are tangent to the arc. Of course, the embodiment of the present application does not limit the number of components that need to be bypassed. The number of components that need to be bypassed is positively correlated with the number of arcs in the wiring. When the number of components that need to be bypassed increases, the number of arcs in the wiring also increases accordingly.

[0063] In addition, the alternating connection in the embodiments of the present application means that the arcs and tangent segments are connected at intervals, that is, one arc is connected to the front and rear two tangent segments, and one tangent segment is connected to at least one arc. When the tangent segment is a tangent segment passing through the first wiring port, the tangent segment is only connected to one arc, and when the tangent segment is a tangent segment passing through the second wiring port, the tangent segment is only connected to one arc. Except for the two tangent segments connected to the first wiring port or the second wiring port, all other tangent segments are connected to the front and rear two arcs.

[0064] In some embodiments, the size of the center angle of each arc and the length of each tangent segment are not limited, and the arc is tangent to the two tangent segments before and after it. That is, the arc and the tangent segments are connected alternately one by one in the wiring. In some embodiments. The tangent segments and the arc are connected alternately in the wiring. In some embodiments, the beginning of the wiring is the tangent segment connected to the first wiring port, and the end of the wiring is the tangent segment connected to the second wiring port. In some embodiments, Fig.10 As shown in 1020, line segment d3t3, arc t3 counterclockwise to f3, line segment f3t4, arc t4 counterclockwise to f4, and line segment f4d4 are connected to each other to obtain wiring from the first wiring port d3 to the second wiring port d4, and line segment d3t3, line segment f3t4, and line segment f4d4 are all tangent segments, that is, the tangent segments and arcs are connected alternately. Among them, line segment d3t3 is tangent to the circle with c3 as the center from arc t3 counterclockwise to f3, line segment f3t4 is tangent to the circle with c3 as the center from arc t3 counterclockwise to f3 and the circle with c4 as the center from arc t4 counterclockwise to f4, and line segment f4d4 is tangent to the circle with c4 as the center from arc t4 counterclockwise to f4. The beginning of the wiring is the tangent segment d3t3 connected to the first wiring port d3, and the end of the wiring is the tangent segment f4d4 connected to the second wiring port d4.

[0065] Step 720, identifying arcs included in the wiring, and determining a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to an arc with a center angle corresponding to the arc being greater than a threshold.

[0066] In some embodiments, at least one arc included in the wiring is identified for spinning, and a target arc is determined. In the embodiment of the present application, an arc with spinning phenomenon is considered to be an arc with a center angle greater than a threshold. Since each arc corresponds to two front and rear tangent segments when the embodiment of the present application is wiring, when the center angle corresponding to the arc is too large, the front and rear tangent segments intersect, resulting in the occurrence of circling phenomenon. In some embodiments, the threshold is equal to 180 degrees. When the center angle corresponding to the arc is greater than 180 degrees, the arc is considered to have spinning. Of course, the embodiment of the present application does not limit the specific value of the threshold.

[0067] In some embodiments, Figure 8 As shown, 810 shows that there is a target arc. If the arc from point a1 to point b1 counterclockwise has a center angle less than a threshold, then the arc from a1 to b1 does not belong to the target arc. If the arc from point a2 to point b2 counterclockwise has a center angle greater than a threshold, then the arc from a2 to b2 belongs to the target arc. In some embodiments, Figure 8As shown, 820 shows that there is no target arc. If the arc from point a3 to point b3 is counterclockwise and the center angle is less than the threshold, then the arc from a3 to b3 does not belong to the target arc. If the arc from point a4 to point b4 is counterclockwise and the center angle is less than the threshold, then the arc from a4 to b4 belongs to the target arc. That is, Figure 8 The target arc determined according to step 720 is only the arc from a2 counterclockwise to b2.

[0068] In some embodiments, the recognition in step 720 may also be referred to as spinning recognition, circling recognition, or circling recognition.

[0069] Step 730, remove the target arc, adjust the wiring, and obtain the adjusted wiring.

[0070] In some embodiments, after determining the target arc, the target arc is removed and the routing is re-determined. For example, the target arc and the front and rear tangent segments corresponding to the target arc are removed at the same time. The remaining lines are reconnected and meet the above routing requirements to obtain an adjusted routing.

[0071] The technical solution provided by the embodiment of the present application identifies arcs in the wiring, identifies arcs with central angles greater than a threshold, and deletes the arcs, so that the adjusted wiring does not include arcs with central angles greater than the threshold, that is, all arcs with circling phenomena are deleted, while arcs without circling phenomena are retained, and the tangent segments connected to the retained arcs are re-determined to obtain updated arcs, and the updated arcs are continuously determined to determine whether there is a circling phenomenon, until all arcs in the wiring do not have a circling phenomenon, and the final wiring is obtained. Therefore, the phenomenon of overlapping of the lines determined according to the wiring due to circling is avoided, making the wiring on the chip layout more reasonable and accurate.

[0072] Please refer to Fig. 9 , which shows a flow chart of a wiring method for a chip layout provided by another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, a tablet computer, a server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided by the present embodiment is implemented by the computer program. Fig. 9 As shown, the method may include at least one of the following steps 910 to 940.

[0073] Step 910, obtaining a wiring from a first wiring port to a second wiring port on a chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, wherein the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, and each circular arc takes a vertex on the chip layout as the center and bypasses the component corresponding to the vertex, and the vertex is the point corresponding to the component passing between the first wiring port and the second wiring port.

[0074] Step 920, for each arc, obtain the starting point of the arc connected to the first tangent segment, the vertex corresponding to the arc, and the end point of the arc connected to the second tangent segment; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc, and the second tangent segment in sequence.

[0075] In some embodiments, the front and rear tangent segments of the arc are considered to include a front tangent segment (first tangent segment) and a rear tangent segment (second tangent segment). The tangent point between the first tangent segment and the arc is considered to be the starting tangent point of the arc, and the tangent point between the second tangent segment and the arc is considered to be the final tangent point of the arc. According to the wiring direction from the first wiring port to the second wiring port, the starting tangent point is first passed, then the arc is passed, and finally the final tangent point is passed.

[0076] In some embodiments, Fig.10 As shown in 1010, according to the wiring direction from the first wiring port to the second wiring port, first pass through the starting point t1 of the first arc with c1 as the center, then pass through arc t1 counterclockwise to f1, f1 is the final tangent point of the arc. After passing the first arc, pass through line segment f1 to t2, t2 is considered to be the starting point of the second arc with c2 as the center, pass through arc t2 counterclockwise to f2, and finally continue to route backward along the tangent direction of the final tangent point f2. Among them, line segment d1 to t1 is the first tangent segment of the arc with c1 as the center, and line segment f1 to t2 is the second tangent segment of the arc with c1 as the center. At the same time, line segment f1 to t2 is the first tangent segment of the arc with c2 as the center, and line segment f2 to d2 is the second tangent segment of the arc with c2 as the center.

[0077] Step 930, determining whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the final point of tangency.

[0078] In some embodiments, when the wiring direction on the arc is counterclockwise, when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is counterclockwise, the arc is determined to be the target arc. In some embodiments, when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is clockwise, the arc is determined not to be the target arc. Conversely, when the wiring direction on the arc is clockwise, when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is clockwise, the arc is determined to be the target arc. In some embodiments, when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is counterclockwise, the arc is determined not to be the target arc.

[0079] Fig.10 The routing direction of the arc in is counterclockwise. In some embodiments, Fig.10 As shown in 1010, based on the positional relationship between the starting point of contact t1, the vertex c1 corresponding to the arc, and the final point of contact f1, it is determined whether the arc with c1 as the center is the target arc. Since the direction formed by the starting point of contact t1, the vertex c1 corresponding to the arc to the final point of contact f1 is clockwise, the arc is not the target arc. In some embodiments, based on the positional relationship between the starting point of contact t2, the vertex c2 corresponding to the arc, and the final point of contact f2, it is determined whether the arc with c2 as the center is the target arc. Since the direction formed by the starting point of contact t2, the vertex c2 corresponding to the arc to the final point of contact f2 is counterclockwise, the arc is the target arc.

[0080] In some embodiments, Fig.10 As shown in 1020, according to the positional relationship between the starting point of contact t3, the vertex c3 corresponding to the arc, and the final point of contact f3, it is determined whether the arc with c3 as the center is the target arc. Since the direction formed by the starting point of contact t3, the vertex c3 corresponding to the arc to the final point of contact f3 is clockwise, the arc is not the target arc. In some embodiments, according to the positional relationship between the starting point of contact t4, the vertex c4 corresponding to the arc, and the final point of contact f4, it is determined whether the arc with c4 as the center is the target arc. Since the direction formed by the starting point of contact t4, the vertex c4 corresponding to the arc to the final point of contact f4 is clockwise, the arc is not the target arc.

[0081] In some embodiments, step 930 includes at least one of steps 931 to 933 (not shown in the figure).

[0082] Step 931, determine the first direction and the second direction; wherein the first direction refers to the rotation direction from the starting point of tangency to the final point of tangency and then to the vertex corresponding to the arc, and the second direction refers to the rotation direction from the starting point of tangency along the arc to the final point of tangency, and the rotation direction is clockwise or counterclockwise.

[0083] The first direction shown in step 931 refers to the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc. Of course, the first direction can not only be the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc, but also the rotation direction from the final point to the vertex corresponding to the arc and then to the starting point, or from the vertex corresponding to the arc to the starting point and then to the final point. The specific form of the first direction is not limited in this application. Of course, in addition to the first direction, other directions can also be used to determine whether it is the target arc. For example, in the above embodiment, Fig.10 In the description, the direction of judgment is the rotation direction from the starting point of tangency to the vertex corresponding to the arc and then to the final point of tangency.

[0084] The second direction shown in step 931 may be considered as the routing direction of the arc.

[0085] Step 932: If the first direction and the second direction are different, determine that the arc is a target arc.

[0086] Step 933: If the first direction and the second direction are the same, it is determined that the arc is not the target arc.

[0087] When the first direction shown in step 931 refers to the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc, if the first direction and the second direction are different, it is determined that the arc is the target arc. If the first direction and the second direction are the same, it is determined that the arc is not the target arc.

[0088] The following is the method of steps 931 to 933. Fig.10 The arc in the image is identified. Fig.10 As shown in FIG. 1 , the second direction, i.e., the wiring direction of the arc, is counterclockwise. Fig.10 As shown in 1010, for an arc with c1 as the center, the first direction, i.e., the rotation direction from the starting point t1 to the final point f1 and then to the vertex c1 corresponding to the arc, is counterclockwise, and the first direction and the second direction are the same, then it is determined that the arc is not the target arc. For an arc with c2 as the center, the first direction, i.e., the rotation direction from the starting point t2 to the final point f2 and then to the vertex c2 corresponding to the arc, is clockwise, and the first direction and the second direction are different, then it is determined that the arc is the target arc. In some embodiments, as Fig.10 As shown in 1020, for the arc with c3 as the center, the first direction, that is, the rotation direction from the starting point t3 to the final point f3 and then to the vertex c3 corresponding to the arc, is counterclockwise, and the first direction and the second direction are the same, then it is determined that the arc is not the target arc. For the arc with c4 as the center, the first direction, that is, the rotation direction from the starting point t4 to the final point f4 and then to the vertex c4 corresponding to the arc, is counterclockwise, and the first direction and the second direction are the same, then it is determined that the arc is not the target arc.

[0089] In some embodiments, step 930 also includes at least one of steps 934 to 936 (not shown in the figure).

[0090] Step 934, determine the center angle of the arc; wherein the center angle has the vertex corresponding to the arc as the vertex, one side of the center angle passes through the starting tangent point, and the other side of the center angle passes through the ending tangent point.

[0091] This application does not limit the specific method of determining the central angle of a circle. When the center position, the starting point of tangency, and the final point of tangency are known, the degree of the central angle of a circle can be calculated according to the arc length formula l=πrα / 180, where l is the arc length, r is the radius of the arc, and α is the number of segments of the central angle of a circle.

[0092] Step 935: If the center angle is greater than the threshold, it is determined that the arc is a target arc.

[0093] Step 936: If the center angle is less than or equal to the threshold, it is determined that the arc is not the target arc.

[0094] In some embodiments, if the center angle is greater than a threshold, the arc is determined to be a target arc, and if the center angle is less than or equal to the threshold, the arc is determined not to be a target arc. Optionally, the threshold is 180 degrees.

[0095] Step 940, remove the target arc, adjust the wiring, and obtain the adjusted wiring.

[0096] In the technical solution provided in the embodiment of the present application, whether the arc is the target arc is determined based on the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the final point of tangency, so that the accuracy of the determined target arc is high. In addition, two methods are specifically shown, one is to determine whether it is the target arc based on whether the first direction and the second direction are consistent, and the other is to determine whether it is the target arc based on the degree of the center angle. Therefore, the diversity of the methods for determining the target arc is improved.

[0097] Please refer to Fig.11 , which shows a flow chart of a wiring method for a chip layout provided by another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, a tablet computer, a server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided by the present embodiment is implemented by the computer program. Fig.11 As shown, the method may include at least one of the following steps 1110 to 1140.

[0098] Step 1110, obtaining a wiring from a first wiring port to a second wiring port on a chip layout, wherein the wiring includes alternatingly connected tangent segments and circular arcs, wherein the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, and each circular arc takes a vertex on the chip layout as the center and bypasses the component corresponding to the vertex, and the vertex is the point corresponding to the component passing between the first wiring port and the second wiring port.

[0099] Step 1120, for each arc, obtain a first tangent segment and a second tangent segment connected by the arc; wherein, according to the routing direction from the first routing port to the second routing port, the routing sequentially passes through the first tangent segment, the arc, and the second tangent segment.

[0100] In some embodiments, Fig.10 As shown, the line segment d1 to t1 is the first tangent segment of the arc with c1 as the center, and the line segment f1 to t2 is the second tangent segment of the arc with c1 as the center. At the same time, the line segment f1 to t2 is the first tangent segment of the arc with c2 as the center, and the line segment f2 to d2 is the second tangent segment of the arc with c2 as the center.

[0101] Step 1130: Determine whether the arc is a target arc based on the positional relationship between the first tangent segment and the second tangent segment.

[0102] In some embodiments, if the first tangent segment and the second tangent segment intersect, it is determined that the arc is the target arc. If the first tangent segment and the second tangent segment do not intersect, it is determined that the arc is not the target arc.

[0103] In some embodiments, Fig.10 As shown in 1010, if the first tangent segment and the second tangent segment of the arc with c1 as the center do not intersect, it is determined that the arc is not the target arc. If the first tangent segment and the second tangent segment of the arc with c2 as the center intersect, it is determined that the arc is the target arc.

[0104] In some embodiments, Fig.10 As shown in 1020, if the first tangent segment and the second tangent segment of the arc with c3 as the center do not intersect, it is determined that the arc is not the target arc. If the first tangent segment and the second tangent segment of the arc with c4 as the center do not intersect, it is determined that the arc is not the target arc.

[0105] Step 1140, remove the target arc, adjust the wiring, and obtain the adjusted wiring.

[0106] For other steps in the embodiments of the present application, please refer to the explanations of the above embodiments and will not be described in detail.

[0107] The technical solution provided in the embodiment of the present application determines whether the arc is a spinning arc and needs to be eliminated by judging whether the front and rear tangent segments of the arc intersect. If the two tangent segments intersect, the arc is considered to be spinning and needs to be eliminated. If the two tangent segments do not intersect, the arc is considered to be non-spinning and does not need to be eliminated. Therefore, the present application improves the efficiency of identifying arcs by judging whether they intersect, and further improves the speed of wiring.

[0108] Please refer to Fig.12 , which shows a flow chart of a wiring method for a chip layout provided by another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, a tablet computer, a server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided by the present embodiment is implemented by the computer program. Fig.12 As shown, the method may include at least one of the following steps 1210 to 1250.

[0109] Step 1210, obtaining a wiring from a first wiring port to a second wiring port on a chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, wherein the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, and each circular arc takes a vertex on the chip layout as the center and bypasses the component corresponding to the vertex, and the vertex is the point corresponding to the component passing between the first wiring port and the second wiring port.

[0110] Step 1220, identifying arcs included in the wiring, and determining a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to an arc with a center angle corresponding to the arc being greater than a threshold.

[0111] Step 1230, remove the target arc, generate a tangent segment connecting the previous connection object and the next connection object of the target arc, and obtain an adjusted wiring; wherein the previous connection object is the previous arc or the first wiring port, and the next connection object is the next arc or the second wiring port.

[0112] In some embodiments, after the target arc is removed, rewiring is required. That is, it is necessary to generate a tangent segment connecting the previous connection object and the next connection object of the target arc to obtain the adjusted wiring. In some embodiments, the previous connection object of the target arc is the first wiring port, and the next connection object is the next arc, then it is necessary to generate a tangent segment connecting the first wiring port and the next arc, and when the connection method changes, the size of the center angle corresponding to the next arc also changes. In some embodiments, the previous connection object of the target arc is the previous arc, and the next connection object is the next arc, then it is necessary to generate a common tangent connecting the previous arc and the next arc, and when the connection method changes, the size of the center angle corresponding to the previous arc and the next arc also changes. In some embodiments, the previous connection object of the target arc is the previous arc, and the next connection object is the second wiring port, then it is necessary to generate a tangent segment connecting the previous arc and the second wiring port, and when the connection method changes, the size of the center angle corresponding to the previous arc also changes.

[0113] Step 1240, determine whether there is a target arc in the wiring.

[0114] In some embodiments, all arcs in the adjusted wiring continue to be judged one by one whether there is a target arc. In other embodiments, it is not necessary to identify all arcs, but only the arcs before and after the arc deleted in the last adjustment are re-identified. This is because the tangent points corresponding to the front and rear arcs are changed in the adjusted wiring, which may cause the rotation of the front and rear arcs to change, but it does not affect other arcs except the front and rear arcs of the target arc. Therefore, only the front and rear arcs after rewiring need to be identified, without identifying all arcs, thereby improving the recognition efficiency.

[0115] If it exists, execute step 1220. If it does not exist, execute step 1250.

[0116] Step 1250, end the process and obtain the adjusted chip layout.

[0117] In some embodiments, after removing the arcs, when the adjusted wiring is traversed and no arcs that need to be removed are found, it is considered that there is no spinning phenomenon in the wiring, and the wiring is considered to be the final planned wiring. That is, when the wiring of the physical device is performed according to the wiring in the chip layout, the line in the physical device does not spin. It should be understood that the wiring in the embodiments of the present application refers to the chip layout level, not the actual layout of the signal line, but reflects the actual device connection in electronic form.

[0118] In some embodiments, all arcs are traversed only once, and when it is determined that an arc is not the target arc, the next arc is identified. When an arc is determined to be the target arc, the arc is removed, and the front and rear connected objects are reconnected to determine whether the reconnected front and rear connected objects are not objects that need to be removed. If neither of them needs to be removed, the next arc is identified.

[0119] Please refer to Fig.13 , which shows a flow chart of a wiring method for a chip layout provided by another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, a tablet computer, a server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided by the present embodiment is implemented by the computer program. Fig.13 As shown, the method may include at least one of the following steps 1310 to 1350.

[0120] Step 1310, determining at least one vertex from the points corresponding to each component on the chip layout.

[0121] In some embodiments, the vertex corresponding to the initial line segment is determined according to the distances from the vertices corresponding to each component to the initial line segment, and the initial line segment is a line segment formed by the line connecting the first wiring port and the second wiring port; taking the vertex as the midpoint, the first line segment is determined according to the line connecting the midpoint and the starting point of the initial line segment, and the second line segment is determined according to the line connecting the midpoint and the ending point of the initial line segment; taking the first line segment and the second line segment as the initial line segment respectively, the step of determining the vertex corresponding to the initial line segment is performed until there is no corresponding vertex for the line segment formed by any two adjacent points, and the process is terminated, and any adjacent points include at least one of the following: the first wiring port, at least one determined vertex, and the second wiring port.

[0122] In some embodiments, the positions of various components in the chip layout are fixed, that is, the positions of the points corresponding to various components are fixed. For the line from the first wiring port to the second wiring port, determine the vertex with the shortest distance from the line as the vertex that needs to be bypassed based on the line segment. According to the vertex, divide the line from the first wiring port to the second wiring port into two line segments, and determine again whether there are vertices that need to be bypassed for each of the two line segments, until there are no vertices that need to be bypassed in the line segment after the two divisions, and stop looking for vertices that need to be bypassed. In some embodiments, the determined distance from the vertex to the line segment needs to meet at least the distance condition in addition to meeting the minimum value. For example, the distance from the vertex to the line segment needs to be less than the first value. When the distance from the vertex to the line segment is the minimum value and less than the first value, it is determined that the vertex is the vertex that needs to be bypassed corresponding to the line segment.

[0123] Step 1320: For the k-th vertex among the at least one vertex, determine a circle with the k-th vertex as the center, where k is a positive integer.

[0124] In some embodiments, when determining the routing, it is also necessary to draw a circle for each vertex. The radius of the circle corresponding to each vertex is not limited in this application and can be preset in advance or generated according to an algorithm.

[0125] In some embodiments, the radius of the circle corresponding to the kth vertex is determined based on the number of wires laid at the kth vertex; wherein, when the number of laid wires is 0, the radius of the circle corresponding to the kth vertex is equal to the shortest safety distance; when the number of laid wires is s, the radius of the circle corresponding to the kth vertex is equal to the product of s and the wiring interval and the shortest safety distance, s is a positive integer, and the shortest safety distance and the wiring interval are constants; based on the radius of the circle corresponding to the kth vertex, a circle with the kth vertex as the center is determined.

[0126] In some embodiments, the route laid out at the kth vertex here can be considered as a geometric route that needs to be laid out bypassing the kth vertex. It should be understood that for a certain point a, all geometric routes that need to be laid out bypassing point a need to bypass point a. As the number of planned routes increases, the radius of the arc that bypasses point a should also be larger during routing.

[0127] In some embodiments, when the number of laid lines is 0, the radius r of the circle corresponding to the kth vertex = the shortest safety distance; when the number of laid lines is s, the radius r of the circle corresponding to the kth vertex when the s+1th line is laid = s*wiring interval + shortest safety distance. This application does not limit the specific values ​​of the shortest safety distance and the wiring interval.

[0128] Step 1330 , determining an initial wiring according to the first wiring port, the second wiring port, and the circles corresponding to each vertex.

[0129] In the embodiments of the present application, there is no limitation on how to determine the initial wiring according to the first wiring port, the second wiring port, and the circles corresponding to each vertex, as long as the determined wiring satisfies the constraint conditions. Optionally, the constraint condition for the wiring is that the wiring includes at least two tangent segments and at least one arc, wherein the arc is tangent to its front and rear tangent segments respectively. In some embodiments, the wiring only includes tangent segments and arcs.

[0130] In some embodiments, the tangent to the circle corresponding to the first vertex is determined through the first routing port, and the tangent point is determined as the starting tangent point corresponding to the first vertex; a common tangent is drawn between the circle corresponding to the kth vertex and the circle corresponding to the k+1th vertex, and the intersection point of the common tangent and the circle corresponding to the kth vertex is determined as the final tangent point corresponding to the kth vertex, and the intersection point of the common tangent and the circle corresponding to the k+1th vertex is determined as the starting tangent point corresponding to the k+1th vertex; the tangent to the circle corresponding to the last vertex is determined through the second routing port, and the tangent point is determined as the final tangent point corresponding to the last vertex; the arc formed by the starting tangent point and the final tangent point corresponding to the kth vertex is determined as the arc corresponding to the kth vertex; starting from the first routing port, each tangent segment and the arc corresponding to each vertex are alternately connected in sequence until the second routing port is connected to obtain the initial routing.

[0131] In some embodiments, when a common tangent is drawn between the circle corresponding to the kth vertex and the circle corresponding to the k+1th vertex, the tangent segment formed by the two tangent points does not intersect the line segment connecting the kth vertex and the k+1th vertex.

[0132] Step 1340, identifying each arc included in the wiring, and determining a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to an arc with a central angle greater than a threshold;

[0133] Step 1350, remove the target arc, adjust the wiring, and obtain the adjusted wiring.

[0134] The technical solution provided in the embodiment of the present application selects suitable vertices from the vertices of components as vertices in a distance-first manner when determining the wiring, and determines suitable vertices multiple times through binary search. The binary search method for determining vertices can effectively improve the accuracy of the determined vertices and can also greatly improve the efficiency of vertex determination.

[0135] On the other hand, the wiring determined by sequentially connecting arcs and tangent segments requires the shortest signal line, which is beneficial to saving wiring costs. On the other hand, determining the arc radius based on the number of laid lines is beneficial to avoiding line crossing, thereby improving the accuracy of wiring.

[0136] Please refer to Fig.14 , which shows a block diagram of a wiring method for a chip layout provided by an embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, a tablet computer, a server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided by the present embodiment is implemented by the computer program.

[0137] like Fig.14 As shown in 1400, the present application designs an algorithm for automatically identifying signal lines that go around in circles and reasonably avoiding them, which successfully solves the problem of signal lines going around in circles during the layout process, making the layout of signal lines more reasonable and efficient. First, the initial path points are laid out, and the routingedge endpoints are traversed to determine the arcs. Wherein routingedge is the triangulated line where the initial path point is located, and the routingedge endpoint is the triangulation endpoint. Optionally, the triangulation endpoint is the vertex of the component. There will be multiple path points in a round of traversal, and there will be multiple endpoints of the triangulation line. It is necessary to select the point that needs to be bypassed from these endpoints by sorting as the center of the circle and determine the radius. The traversal process refers to the above embodiment, which is mainly through recursive traversal. At the beginning, as long as there are two points and a line at the starting point and the end point, each subsequent round is divided into two, and the most suitable point for the current round is selected, until the recursion stops after a suitable point is found. After all the endpoints that need to be bypassed are determined, all arcs and radii are determined according to the radius of the circle corresponding to each endpoint. Then traverse all arcs and perform rotation identification. Determine whether the first direction and the second direction are the same. If they are the same, the arc is considered not to be the target arc. If they are different, the arc is considered to be the target arc and the target arc is removed. Determine whether the traversal is completed. When all arcs are traversed, the routing is completed. That is, the main implementation method is to traverse each arc on the path line and detect whether it is spinning in a circle. If spinning occurs, the arc is deleted, and the tangent point position of the arc before and after the deleted arc is recalculated to connect. Specifically, Fig.15 For example, in Fig.15 In the wiring 1510, assuming that the wiring direction is from the first wiring port h1 to the second wiring port h8, the wiring includes tangent segment h1h2, arc h2 counterclockwise to h3, tangent segment h3 to h4, arc h4 counterclockwise to h5, tangent segment h5 to h6, arc h6 counterclockwise to h7, and tangent segment h7h8. According to the technical solution provided by the above embodiment, it is not difficult to find that there is a circle reversal phenomenon when the arc h4 counterclockwise to h5, then based on the technical solution provided by the embodiment of the present application, the arc h4 counterclockwise to h5 is identified as the target arc, that is, the arc that needs to be deleted. After deleting the arc, the tangent segment h4h4 and tangent segment h5h6 connected to the arc are also deleted accordingly, such as Fig.15As shown in 1520, the common tangent between the arc h2 counterclockwise to the circle where h3 is located and the arc h6 counterclockwise to the circle where h7 is located, that is, the tangent segment g3g4, is re-determined. According to the tangent segment h3h4, the updated arc h2 counterclockwise to g3 and the updated arc g4 counterclockwise to h7 connected to the tangent segment can be obtained. This process can be classified as the operation of deleting a node in a single linked list and connecting its previous and subsequent nodes. The wiring determined based on the technical solution provided in the embodiment of the present application completely solves the problem of signal lines spinning in circles in the previous wiring, and will not be too close to adjacent signal lines or even overlap.

[0138] The core link of the improved algorithm proposed in this application is the automatic identification and avoidance of signal line circles. When performing corresponding analysis and identification on the arc, if arcwind and fcwind are different, where arcwind is the direction of the arc route, that is, the second direction, and tfcwind is the direction from the starting point of the arc to the final point of the arc and then to the center of the arc, that is, the first direction, then the arc has circled and subsequent avoidance is required. If arcwind and tfcwind are the same, no circle has occurred. By deleting the rotating arc and connecting the arcs before and after it by recalculating the tangent point, reasonable avoidance of the signal line spinning problem is achieved. In some embodiments, since the position of the arc tangent point changes dynamically, the following two situations are likely to occur during the layout process: 1. A certain arc is normal at the beginning, and there is no phenomenon of circling, but later due to the change of the tangent point position, the arc circling phenomenon occurs; 2. A certain arc is circling at the beginning, but due to the change of the adjacent arc, the tangent point position changes accordingly, so the arc returns to normal. Based on the above analysis, we put the recognition and judgment logic of the arc circling phenomenon in the algorithm until all the arc tangent point positions are completely determined (by recursively traversing the initial path points, constantly finding the most suitable triangulation point as the middle point for binary recursion, and determining all the centers and radii that need to be bypassed, the corresponding tangent points are also determined) and then make corresponding judgments and avoidances. And after deleting the arc that is circling, it is necessary to recalculate the tangent point positions of the arcs before and after the deleted arc (if any), so that the transition of the signal line between arcs is more natural and reasonable.

[0139] In an exemplary embodiment, a chip is also provided, which is obtained based on a chip layout, and the wiring of the chip layout is obtained using the wiring method of the chip layout mentioned in the above embodiment. In some embodiments, the chip is a quantum chip.

[0140] The following are device embodiments of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0141] Please refer to Fig.16 , which shows a block diagram of a wiring device for a chip layout provided by an embodiment of the present application. The device has the function of implementing the above method example, and the function can be implemented by hardware or by hardware executing corresponding software. The device can be the computer device described above, or it can be set in a computer device. Fig.16 As shown, the device 1600 includes: a wiring determination module 1610 , an arc determination module 1620 and a wiring adjustment module 1630 .

[0142] The wiring determination module 1610 is used to determine the wiring from the first wiring port to the second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and arcs, each arc having a vertex on the chip layout as the center and bypassing the component corresponding to the vertex, and the vertex is the point corresponding to the component passing between the first wiring port and the second wiring port.

[0143] The arc determination module 1620 is used to identify each of the arcs included in the wiring and determine a target arc, where the target arc refers to an arc with a spinning phenomenon, and the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold.

[0144] The wiring adjustment module 1630 is used to remove the target arc and adjust the wiring to obtain an adjusted wiring.

[0145] In some embodiments, Fig.17 As shown, the arc determination module 1620 includes a point acquisition unit 1621 and an arc determination unit 1622 .

[0146] The point acquisition unit 1621 is used to acquire, for each of the arcs, a starting point of tangency between the arc and the first tangent segment, a vertex corresponding to the arc, and an end point of tangency between the arc and the second tangent segment. According to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc, and the second tangent segment in sequence.

[0147] The arc determination unit 1622 is used to determine whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the end point of tangency.

[0148] In some embodiments, the arc determination unit 1622 is used to determine a first direction and a second direction; wherein the first direction refers to the rotation direction from the starting point to the end point and then to the vertex corresponding to the arc, and the second direction refers to the rotation direction from the starting point along the arc to the end point, and the rotation direction is clockwise or counterclockwise; if the first direction and the second direction are different, it is determined that the arc is the target arc; if the first direction and the second direction are the same, it is determined that the arc is not the target arc.

[0149] In some embodiments, the arc determination unit 1622 is also used to determine the center angle corresponding to the arc; wherein the center angle has the vertex corresponding to the arc as the vertex, one side of the center angle passes through the starting tangent point, and the other side of the center angle passes through the end tangent point; if the center angle is greater than the threshold, it is determined that the arc is the target arc; if the center angle is less than or equal to the threshold, it is determined that the arc is not the target arc.

[0150] In some embodiments, Fig.17 As shown, the arc determination module 1620 also includes a line segment acquisition unit 1623 .

[0151] The line segment acquisition unit 1623 is used to acquire, for each of the arcs, a first tangent segment and a second tangent segment connected by the arc; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc and the second tangent segment in sequence.

[0152] The arc determining unit 1622 is further configured to determine whether the arc is the target arc according to the positional relationship between the first tangent segment and the second tangent segment.

[0153] In some embodiments, the arc determination unit 1622 is further used to determine that the arc is the target arc if the first tangent segment and the second tangent segment intersect; if the first tangent segment and the second tangent segment do not intersect, determine that the arc is not the target arc.

[0154] In some embodiments, the wiring adjustment module 1630 is used to remove the target arc, generate a tangent segment connecting the previous connection object and the next connection object of the target arc, and obtain an adjusted wiring; wherein the previous connection object is the previous arc or the first wiring port, and the next connection object is the next arc or the second wiring port.

[0155] In some embodiments, the arc determination module 1620 is further used to start from the step of identifying each of the arcs included in the wiring and determining the target arc; if the target arc does not exist in the wiring, the process is terminated to obtain the adjusted chip layout.

[0156] In some embodiments, Fig.17 As shown, the wiring determination module 1610 includes a vertex determination unit 1611 , a circle determination unit 1612 , and a wiring determination unit 1613 .

[0157] The vertex determination unit 1611 is used to determine at least one vertex from the points corresponding to each of the components on the chip layout.

[0158] The circle determination unit 1612 is used to determine, for at least one of the vertices, a circle with the k-th vertex as the center, where k is a positive integer.

[0159] The wiring determination unit 1613 is used to determine the initial wiring according to the first wiring port, the second wiring port and the circles corresponding to the vertices.

[0160] In some embodiments, the wiring determination unit 1613 is used to determine the tangent of the circle corresponding to the first vertex through the first wiring port, and determine the tangent point as the starting tangent point corresponding to the first vertex; draw a common tangent between the circle corresponding to the kth vertex and the circle corresponding to the k+1th vertex, determine the intersection of the common tangent and the circle corresponding to the kth vertex as the final tangent point corresponding to the kth vertex, and determine the intersection of the common tangent and the circle corresponding to the k+1th vertex as the starting tangent point corresponding to the k+1th vertex; determine the tangent of the circle corresponding to the last vertex through the second wiring port, and determine the tangent point as the final tangent point corresponding to the last vertex; determine the arc formed by the starting tangent point and the final tangent point corresponding to the kth vertex as the arc corresponding to the kth vertex; starting from the first wiring port, alternately connect each tangent segment and each arc corresponding to the vertex in sequence until the second wiring port is connected to obtain the initial wiring.

[0161] In some embodiments, the circle determination unit 1612 is used to determine the radius of the circle corresponding to the kth vertex according to the number of lines laid at the kth vertex; wherein, when the number of laid lines is 0, the radius of the circle corresponding to the kth vertex is equal to the shortest safety distance; when the number of laid lines is s, the radius of the circle corresponding to the kth vertex is equal to the product of s and the wiring interval and the shortest safety distance, s is a positive integer, and the shortest safety distance and the wiring interval are constants; according to the radius of the circle corresponding to the kth vertex, a circle with the kth vertex as the center is determined.

[0162] In some embodiments, the vertex determination unit 1611 is used to determine the vertex corresponding to the initial line segment according to the distances from the points corresponding to each of the components to the initial line segment, where the initial line segment is a line segment formed by the line connecting the first wiring port and the second wiring port; taking the vertex as the midpoint, determining the first line segment according to the line connecting the midpoint and the starting point of the initial line segment, and determining the second line segment according to the line connecting the midpoint and the ending point of the initial line segment; taking the first line segment and the second line segment as the initial line segments respectively, executing the step of determining the vertex corresponding to the initial line segment, until there is no corresponding vertex in the line segment formed by any two adjacent points, then terminating the process, where the any adjacent points include at least one of the following: the first wiring port, at least one of the determined vertices, and the second wiring port.

[0163] It should be noted that the device provided in the above embodiment, when implementing its functions, is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0164] Please refer to Fig.18 , which shows a block diagram of a computer device 1800 provided in one embodiment of the present application. The computer device 1800 may be any electronic device with data calculation, processing and storage capabilities. The computer device 1800 may be used to implement the wiring method of the chip layout provided in the above embodiment.

[0165] Typically, the computer device 1800 includes a processor 1801 and a memory 1802 .

[0166] The processor 1801 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1801 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1801 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1801 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1801 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0167] The memory 1802 may include one or more computer-readable storage media, which may be non-transitory. The memory 1802 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1802 is used to store a computer program, which is configured to be executed by one or more processors to implement the wiring method of the above-mentioned chip layout.

[0168] Those skilled in the art will understand that Fig.18 The structure shown in the figure does not constitute a limitation on the computer device 1800, and the computer device 1800 may include more or less components than shown in the figure, or combine some components, or adopt a different arrangement of components.

[0169] In an exemplary embodiment, a computer-readable storage medium is also provided, in which a computer program is stored, and when the computer program is executed by a processor, the wiring method of the above-mentioned chip layout is implemented. Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives) or optical disks, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0170] In an exemplary embodiment, a computer program product is also provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the wiring method of the chip layout.

[0171] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0172] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip layout wiring method, characterized in that: The method comprises: Obtaining a wiring from a first wiring port to a second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, each circular arc has a vertex on the chip layout as a center and bypasses a component corresponding to the vertex, and the vertex is a point corresponding to a component passing between the first wiring port and the second wiring port; Identify the arc included in the wiring to determine a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold; The target arc is eliminated, and the wiring is adjusted to obtain an adjusted wiring.

2. The method according to claim 1, characterized in that The step of identifying the arc included in the wiring and determining the target arc includes: For each of the arcs, a starting point of tangency between the arc and the first tangent segment, a vertex corresponding to the arc, and an end point of tangency between the arc and the second tangent segment are obtained; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc, and the second tangent segment in sequence; Whether the arc is the target arc is determined according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the final point of tangency.

3. The method according to claim 2, characterized in that The determining whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the terminal point of tangency includes: Determine a first direction and a second direction; wherein the first direction refers to the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc, and the second direction refers to the rotation direction from the starting point along the arc to the final point, and the rotation direction is clockwise or counterclockwise; If the first direction and the second direction are different, determining that the arc is the target arc; If the first direction and the second direction are the same, it is determined that the arc is not the target arc.

4. The method according to claim 2, characterized in that: The determining whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the terminal point of tangency includes: Determine the central angle corresponding to the arc; wherein the central angle has a vertex corresponding to the arc as a vertex, one side of the central angle passes through the starting tangent point, and the other side of the central angle passes through the final tangent point; If the central angle is greater than the threshold, determining that the arc is the target arc; If the central angle is less than or equal to the threshold, it is determined that the arc is not the target arc.

5. The method according to claim 1, characterized in that The step of respectively identifying each of the arcs included in the wiring and determining a target arc includes: For each of the circular arcs, a first tangent segment and a second tangent segment connected by the circular arc are obtained; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the circular arc and the second tangent segment in sequence; Whether the arc is the target arc is determined according to the positional relationship between the first tangent segment and the second tangent segment.

6. The method according to claim 5, characterized in that The determining, based on the positional relationship between the first tangent segment and the second tangent segment, whether the arc is the target arc includes: If the first tangent segment and the second tangent segment intersect, determining that the arc is the target arc; If the first tangent segment and the second tangent segment do not intersect, it is determined that the arc is not the target arc.

7. The method according to claim 1, characterized in that The step of removing the target arc and adjusting the wiring to obtain the adjusted wiring includes: Eliminate the target arc, generate a tangent segment connecting the previous connection object and the next connection object of the target arc, and obtain an adjusted wiring; wherein the previous connection object is the previous arc or the first wiring port, and the next connection object is the next arc or the second wiring port.

8. The method according to claim 1, characterized in that The target arc is removed, the wiring is adjusted, and the adjusted wiring further includes: Again, the step of identifying each of the arcs included in the wiring and determining a target arc is started; If the target arc does not exist in the wiring, the process ends and an adjusted chip layout is obtained.

9. The method according to claim 1, characterized in that: The obtaining of the wiring from the first wiring port to the second wiring port on the chip layout includes: Determine at least one vertex from points corresponding to each of the components on the chip layout; For a k-th vertex among at least one of the vertices, determine a circle with the k-th vertex as the center, where k is a positive integer; The initial wiring is determined according to the first wiring port, the second wiring port, and the circles corresponding to the vertices.

10. The method according to claim 9, characterized in that The determining the initial wiring according to the first wiring port, the second wiring port, and the circles corresponding to the vertices respectively includes: Determine a tangent line to a circle corresponding to a first vertex through the first wiring port, and determine a tangent point as a starting tangent point corresponding to the first vertex; Draw a common tangent line between the circle corresponding to the k-th vertex and the circle corresponding to the k+1-th vertex, determine the intersection point of the common tangent line with the circle corresponding to the k-th vertex as the final tangent point corresponding to the k-th vertex, and determine the intersection point of the common tangent line with the circle corresponding to the k+1-th vertex as the starting tangent point corresponding to the k+1-th vertex; Determine a tangent line to the circle corresponding to the last vertex through the second wiring port, and determine the tangent point as the final tangent point corresponding to the last vertex; Determine the arc formed by the starting point and the ending point of tangency corresponding to the k-th vertex as the arc corresponding to the k-th vertex; Starting from the first wiring port, each tangent segment and the arc corresponding to each vertex are alternately connected in sequence until the second wiring port is connected to obtain the initial wiring.

11. The method according to claim 9, characterized in that The step of determining a circle with the k-th vertex as the center includes: Determine the radius of the circle corresponding to the kth vertex according to the number of wires laid at the kth vertex; wherein, when the number of laid wires is 0, the radius of the circle corresponding to the kth vertex is equal to the shortest safety distance; when the number of laid wires is s, the radius of the circle corresponding to the kth vertex is equal to the sum of the product of s and the wiring interval and the shortest safety distance, s is a positive integer, and the shortest safety distance and the wiring interval are constants; According to the radius of the circle corresponding to the k-th vertex, a circle with the k-th vertex as the center is determined.

12. The method according to claim 9, characterized in that Determining at least one vertex from points corresponding to each of the components on the chip layout includes: Determine, according to the distances from the points corresponding to the components to the initial line segment, the vertex corresponding to the initial line segment, wherein the initial line segment is a line segment formed by the line connecting the first wiring port and the second wiring port; Taking the vertex as the middle point, determining the first line segment according to the line connecting the middle point and the starting point of the initial line segment, and determining the second line segment according to the line connecting the middle point and the ending point of the initial line segment; The first line segment and the second line segment are respectively used as the initial line segments, and the step of determining the vertices corresponding to the initial line segments is performed until there are no corresponding vertices for the line segments formed by any two adjacent points, and the process is terminated, wherein the any adjacent points include at least one of the following: the first wiring port, at least one of the determined vertices, and the second wiring port.

13. A chip, characterized in that: The chip is obtained based on chip layout processing, and the wiring of the chip layout is obtained by using the method according to any one of claims 1 to 12.

14. The chip according to claim 13, characterized in that: The chip is a quantum chip.

15. A wiring device for a chip layout, characterized in that: The device comprises: a wiring determination module, configured to obtain a wiring from a first wiring port to a second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, wherein the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, and each circular arc has a vertex on the chip layout as a center and bypasses a component corresponding to the vertex, and the vertex is a point corresponding to a component passing between the first wiring port and the second wiring port; An arc determination module, used for identifying the arc included in the wiring, and determining a target arc, wherein the target arc refers to an arc with a spinning phenomenon, wherein the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold value; The wiring adjustment module is used to remove the target arc and adjust the wiring to obtain the adjusted wiring.

16. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein a computer program is stored in the memory, and the processor is configured to execute the computer program to implement the method according to any one of claims 1 to 12.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method according to any one of claims 1 to 12.

18. A computer program product, characterized in that The computer program product comprises a computer program, which is loaded and executed by a processor to implement the method according to any one of claims 1 to 12.

Images