Back power supply chip packaging structure and preparation method thereof

Abstract

According to the back power supply chip packaging structure and the preparation method thereof provided by the invention, the back power supply logic chip is formed by the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power supply wiring layer, and the storage chip is stacked by using the back power supply logic chip, so that the packaging thickness is effectively reduced, and the size of the packaging structure is reduced; the back power supply logic chip and the metal columns penetrating through the interior of the first transistor layer can effectively shorten the transmission distance and reduce power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to a back-side power supply chip packaging structure and a preparation method thereof. Background Art

[0002] In traditional 2.5D or 3D advanced packaging, wiring is mostly done on the front side of the wafer, and signal lines and power lines are stacked and connected vertically to form two or more layers of semiconductor devices with active electronic components of the integrated circuit. Power lines are used to supply power to the chip to form a power supply network. However, there is also a signal network formed by signal lines in the front area of ​​the chip, that is, the signal network layer and the power supply network layer are both located on the same side of the chip. Making the power supply network on the front side of the chip means that the power supply network and the signal network in the chip must share space, and the volume of the entire packaging structure is difficult to further reduce, making the miniaturization and high-density integration of semiconductor packaging structures more and more challenging. Therefore, the industry began to explore the transfer of the power supply network to the back side, making backside power supply (Backside PDN) a hot technical issue.

[0003] Therefore, it is necessary to provide a back-side power supply chip packaging structure and a preparation method thereof. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a back-side power supply chip packaging structure and a preparation method thereof, so as to solve the problem that the semiconductor packaging structure in the prior art is difficult to achieve miniaturization and high-density integration.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a back-side power supply chip packaging structure, comprising the following steps:

[0006] providing a first semiconductor substrate;

[0007] forming a first transistor layer on the front surface of the first semiconductor substrate;

[0008] forming a first signal wiring layer on the first transistor layer, wherein the first signal wiring layer is electrically connected to the first transistor layer;

[0009] forming a first rewiring layer on the first signal wiring layer, wherein the first rewiring layer is electrically connected to the first signal wiring layer;

[0010] Providing a chip, the chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer;

[0011] forming a second rewiring layer on the composite wiring layer, wherein the second rewiring layer is electrically connected to the second signal wiring layer and the second power wiring layer;

[0012] Bonding the first rewiring layer to the second rewiring layer, and electrically connecting the first rewiring layer to the second rewiring layer;

[0013] thinning the first semiconductor substrate from the back side of the first semiconductor substrate;

[0014] forming a passivation layer on the back side of the first semiconductor substrate;

[0015] forming a metal column penetrating the passivation layer, the first semiconductor substrate and the first transistor layer, wherein a first end of the metal column is electrically connected to both the first signal wiring layer and the first transistor layer;

[0016] forming a first power wiring layer on the surface of the passivation layer, wherein the first power wiring layer is electrically connected to the second end of the metal column;

[0017] A metal bump is formed on the surface of the first power wiring layer, and the metal bump is electrically connected to the first power wiring layer.

[0018] Optionally, the method for thinning the first semiconductor substrate includes one or a combination of a mechanical grinding method and a CMP method; the thickness of the first semiconductor substrate after thinning is 1 to 10 μm.

[0019] Optionally, the first semiconductor substrate includes a silicon substrate; and the second semiconductor substrate includes a silicon substrate.

[0020] Optionally, the passivation layer includes an epoxy resin layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

[0021] Optionally, the first signal wiring layer, the first power wiring layer, the second signal wiring layer, the second power wiring layer, the first rewiring layer and the second rewiring layer are all prepared by a Damascene process.

[0022] Optionally, a cutting process step is also included, wherein the cutting method includes one or a combination of mechanical cutting and laser cutting.

[0023] The present invention also provides a back-side power supply chip packaging structure, the back-side power supply chip packaging structure comprising:

[0024] a first semiconductor substrate;

[0025] A first transistor layer, wherein the first transistor layer is located on a front surface of the first semiconductor substrate;

[0026] A passivation layer, the passivation layer is located on the back side of the first semiconductor substrate;

[0027] a first signal wiring layer, wherein the first signal wiring layer is located on the first transistor layer, and the first signal wiring layer and the first transistor layer are electrically connected;

[0028] a first rewiring layer, the first rewiring layer being located on the first signal wiring layer and the first rewiring layer being electrically connected to the first signal wiring layer;

[0029] Providing a chip, the chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer;

[0030] a second rewiring layer, the second rewiring layer being located on the composite wiring layer, the second rewiring layer being electrically connected to the second signal wiring layer and the second power wiring layer, wherein the first rewiring layer is bonded to the second rewiring layer, and the first rewiring layer is electrically connected to the second rewiring layer;

[0031] a metal column, wherein the metal column penetrates the passivation layer, the first semiconductor substrate, and the first transistor layer, and a first end of the metal column is electrically connected to both the first signal wiring layer and the first transistor layer;

[0032] a first power wiring layer, the first power wiring layer being located on a surface of the passivation layer and being electrically connected to the second end of the metal column;

[0033] A metal bump is located on a surface of the first power wiring layer and is electrically connected to the first power wiring layer.

[0034] Optionally, the thickness of the first semiconductor substrate is 1-10 μm; the first semiconductor substrate includes a silicon substrate; and the second semiconductor substrate includes a silicon substrate.

[0035] Optionally, the passivation layer includes an epoxy resin layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

[0036] Optionally, the chip is a memory chip; the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power wiring layer constitute a back-side power supply logic chip.

[0037] As described above, the back-side power supply chip packaging structure and the preparation method thereof of the present invention form a back-side power supply logic chip through a first semiconductor substrate, a first transistor layer, a passivation layer, a first signal wiring layer and a first power wiring layer, and utilize the back-side power supply logic chip to stack the storage chip, thereby effectively reducing the packaging thickness and the size of the packaging structure; the back-side power supply logic chip and the metal pillars running through the first transistor layer can effectively shorten the transmission distance and reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the process flow of preparing a back-side power supply chip packaging structure in an embodiment of the present invention.

[0039] Figure 2 It is a schematic diagram of the structure after the first transistor layer is formed in an embodiment of the present invention.

[0040] Figure 3 It is a schematic diagram of the structure after the first rewiring layer is formed in an embodiment of the present invention.

[0041] Figure 4 It is a schematic diagram of the structure after bonding the first redistribution layer and the second redistribution layer in an embodiment of the present invention.

[0042] Figure 5 It is a schematic diagram of the structure after the first semiconductor substrate is thinned in an embodiment of the present invention.

[0043] Figure 6 It is a schematic diagram of the structure after the metal pillars are formed in an embodiment of the present invention.

[0044] Figure 7 It is a schematic diagram of the structure after the metal bump is formed in the embodiment of the present invention.

[0045] Description of Reference Numerals

[0046] 100 Backside powered logic chip

[0047] 101 first semiconductor substrate

[0048] 102 First transistor layer

[0049] 103 First signal wiring layer

[0050] 104 Passivation layer

[0051] 105 First power wiring layer

[0052] 200 Memory Chip

[0053] 201 second semiconductor substrate

[0054] 202 Second transistor layer

[0055] 203 Composite wiring layer

[0056] 301 First rewiring layer

[0057] 302 Second rewiring layer

[0058] 400 Metal Column

[0059] 500 metal bumps DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0062] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0063] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0064] The present embodiment provides a method for preparing a back-side power supply chip packaging structure, wherein the back-side power supply chip takes a back-side power supply logic chip as an example, and the chip combined with the back-side power supply logic chip is integrated and packaged using a storage chip with a single-sided stacked signal / power wiring layer. The types of the back-side power supply chip and the chip combined with the back-side power supply chip are not limited to this.

[0065] In this embodiment, the memory chip is stacked by using the back-side power supply logic chip, which can effectively reduce the package thickness, reduce the size of the package structure, and effectively shorten the transmission distance and reduce power consumption.

[0066] The following instructions Figure 1 to Figure 7 , the back side power supply chip packaging structure and the preparation method thereof in this embodiment are further introduced.

[0067] First, see Figure 1 and Figure 2 , execute step S1 to provide a first semiconductor substrate 101.

[0068] Specifically, the first semiconductor substrate 101 may include, for example, a silicon substrate, a germanium substrate, etc. In this embodiment, the first semiconductor substrate 101 is a silicon substrate, but is not limited thereto.

[0069] The size of the first semiconductor substrate 101 is preferably at the wafer level, so as to improve production efficiency through subsequent processes such as cutting, but the size of the first semiconductor substrate 101 is not limited thereto.

[0070] Next, see Figure 1 and Figure 2 , execute step S2 to form a first transistor layer 102 on the front side of the first semiconductor substrate 101.

[0071] Specifically, a plurality of transistors (not shown) may be provided in the first transistor layer 102, that is, the first transistor layer 102 may have a plurality of source regions, drain regions, and gate regions, and adjacent transistors may be isolated by, for example, an isolation structure (not shown). The specific type, preparation, structure, and distribution of the transistors are not limited herein.

[0072] Next, see Figure 1 and Figure 3 , executing step S3, forming a first signal wiring layer 103 on the first transistor layer 102, and the first signal wiring layer 103 is electrically connected to the first transistor layer 102.

[0073] Specifically, the first signal wiring layer 103 includes a dielectric layer and metal wiring, and the material of the dielectric layer may include a polymer such as polybenzoxazole and polyimide, or may be formed of an inorganic dielectric material such as silicon nitride and silicon oxide, which is not limited here. The material of the metal wiring may include aluminum, copper, tungsten, etc., or alloys thereof, which is not limited here.

[0074] The specific structure, material and preparation method of the first signal wiring layer 103 are not limited here, and reference may be made to the prior art. For example, the first signal wiring layer 103 may be formed by a combination of photolithography, etching, electroplating or deposition.

[0075] The metal wiring in the first signal wiring layer 103 includes metal signal wiring for transmitting signals to the back-side power supply logic chip and metal power wiring for transmitting power to the memory chip 200 .

[0076] Next, see Figure 1 and Figure 3 , executing step S4, forming a first rewiring layer 301 on the first signal wiring layer 103, and the first rewiring layer 301 is electrically connected to the first signal wiring layer 103.

[0077] Specifically, the first rewiring layer 301 may include a dielectric layer and metal wiring. The material of the dielectric layer may include polymers such as polybenzoxazole and polyimide, or may be formed of inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited here. The material of the metal wiring may include aluminum, copper, tungsten, etc. or their alloys, which are not limited here. The specific structure, material and preparation method of the first rewiring layer 301 are not limited here, and can refer to the existing technology. For example, it can be formed by a combination of processes such as photolithography, etching, electroplating or deposition.

[0078] Next, see Figure 1 and Figure 4 , execute step S5 to provide a chip, wherein the chip includes a stacked second semiconductor substrate 201, a second transistor layer 202 and a composite wiring layer 203, wherein the composite wiring layer 203 includes a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer 202.

[0079] Specifically, the second semiconductor substrate 201 may include, for example, a silicon substrate, a germanium substrate, etc. In this embodiment, the second semiconductor substrate 201 is a silicon substrate, but is not limited thereto. The size of the second semiconductor substrate 201 is preferably wafer-level, so as to improve production efficiency through subsequent processes such as cutting, but the size of the second semiconductor substrate 201 is not limited thereto.

[0080] The second transistor layer 202 may be provided with a plurality of transistors (not shown), that is, it may have a plurality of source regions, drain regions, and gate regions, and adjacent transistors may be isolated by an isolation structure (not shown). The specific type, preparation, structure, and distribution of the transistors are not limited here.

[0081] Among them, the composite wiring layer 203 is located on the same side of the second transistor layer 202, including a second signal wiring layer for transmitting signals to the memory chip and a second power wiring layer for transmitting power to the memory chip, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer 202.

[0082] Among them, the composite wiring layer 203 includes a dielectric layer and a metal wiring. The material of the dielectric layer may include polymers such as polybenzoxazole and polyimide, or may be formed by inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited here; the material of the metal wiring may include aluminum, copper, tungsten, etc. or their alloys, which are not limited here.

[0083] The specific structure, material and preparation method of the composite wiring layer 203 are not limited here, and reference may be made to the prior art. For example, the composite wiring layer 203 may be formed by a combination of photolithography, etching, electroplating or deposition.

[0084] Next, see Figure 1 and Figure 4 , executing step S6, forming a second rewiring layer 302 on the composite wiring layer 203, and the second rewiring layer 302 is electrically connected to the second signal wiring layer and the second power wiring layer.

[0085] Specifically, the second rewiring layer 302 may include a dielectric layer and metal wiring. The material of the dielectric layer may include polymers such as polybenzoxazole and polyimide, or may be formed of inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited here; the material of the metal wiring may include aluminum, copper, tungsten, etc. or their alloys, which are not limited here. The specific structure, material and preparation method of the second rewiring layer 302 are not limited here, and can refer to the existing technology. For example, it can be formed by a combination of photolithography, etching, electroplating or deposition.

[0086] Next, see Figure 1 and Figure 4 , executing step S7, bonding the first re-distribution layer 301 and the second re-distribution layer 302, and the first re-distribution layer 301 and the second re-distribution layer 302 are electrically connected.

[0087] Specifically, the bonding method between the first rewiring layer 301 and the second rewiring layer 302 is preferably a hybrid bonding process to achieve high-density, high-performance interconnection between the first rewiring layer 301 and the second rewiring layer 302, but the bonding method between the first rewiring layer 301 and the second rewiring layer 302 is not limited to this.

[0088] Among them, through the bonding of the first rewiring layer 301 and the second rewiring layer 302, a transition path for signal and power transmission between the storage chip and the back power supply logic chip can be formed, thereby realizing power supply and signal transmission of the back power supply logic chip.

[0089] Next, see Figure 1 and Figure 5 , execute step S8 to thin the first semiconductor substrate 101 from the back side of the first semiconductor substrate 101.

[0090] As an example, a method for thinning the first semiconductor substrate 101 may include a mechanical grinding method, a CMP method, or a combination thereof.

[0091] Specifically, in this embodiment, the first semiconductor substrate 101 is firstly rough-ground by mechanical grinding to perform the thinning process as quickly as possible and improve efficiency, and then fine-ground by CMP to improve the flatness of the ground surface. However, the thinning method of the first semiconductor substrate 101 is not limited to this.

[0092] By thinning the first semiconductor substrate 101, the thickness of the packaging structure can be effectively reduced. In the vertical direction, due to the thinning of the first semiconductor substrate 101, the transmission path of power and signals can be effectively shortened, the transmission efficiency can be improved, and the power consumption can be reduced.

[0093] As an example, the thickness of the first semiconductor substrate 101 after thinning may be 1-10 μm.

[0094] Specifically, the thickness of the first semiconductor substrate 101 after thinning is preferably 1μm, 2μm, 3μm, 5μm, 8μm, 10μm, etc. The first semiconductor substrate 101 reserved after thinning can protect the first transistor layer 102 to avoid damaging the first transistor layer 102. Regarding the specific thickness of the reserved first semiconductor substrate 101, the present embodiment is preferably 1 to 3μm to shorten the transmission path of power supply and signals as much as possible and reduce the package size.

[0095] Next, see Figure 1 and Figure 6, perform step S9 to form a passivation layer 104 on the back side of the first semiconductor substrate 101.

[0096] Specifically, since the insulation property of the material of the first semiconductor substrate 101 is relatively low and since the thickness of the first semiconductor substrate 101 is relatively thin, after the passivation layer 104 is formed on the back side of the first semiconductor substrate 101, the passivation layer 104 can prevent metal materials from diffusing into the first transistor layer 102 in subsequent processes, such as causing short circuits when the metal pillars 400 are subsequently prepared.

[0097] As an example, the passivation layer 104 may include an epoxy resin layer, a polyamide layer, a silicon nitride layer, or a silicon oxide layer. The material, thickness, and preparation method of the passivation layer 104 are not excessively limited herein.

[0098] Next, see Figure 1 and Figure 6 , execute step S10 to form a metal column 400 that penetrates the passivation layer 104 , the first semiconductor substrate 101 and the first transistor layer 102 , and the first end of the metal column 400 is electrically connected to the first signal wiring layer 103 and the first transistor layer 102 .

[0099] Specifically, since the metal pillar 400 is electrically connected to the first transistor layer 102, power can be provided to the transistor layer in the first transistor layer 102 through the metal pillar 400, and since the metal pillar 400 includes the metal pillar 400 electrically connected to the first signal wiring layer 103, power can be provided to the metal power wiring in the first signal wiring layer 103 through the metal pillar 400, so as to transmit power to the memory chip 200.

[0100] The preparation method of the metal pillar 400 may be a nano-through silicon via (n-TSV) prepared by electroplating, but is not limited thereto. The method of preparing the metal pillar 400 and the distribution of the metal pillar 400 are not limited herein.

[0101] Next, see Figure 1 and Figure 7 , executing step S11 , forming a first power wiring layer 105 on the surface of the passivation layer 104 , and the first power wiring layer 105 is electrically connected to the second end of the metal pillar 400 .

[0102] Specifically, the first power wiring layer 105 may include a dielectric layer and a metal wiring. The material of the dielectric layer may include polymers such as polybenzoxazole and polyimide, or may be formed by inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited here; the material of the metal wiring may include aluminum, copper, tungsten, etc. or their alloys, which are not limited here.

[0103] The specific structure, material and preparation method of the first power wiring layer 105 are not limited here, and reference may be made to the prior art. For example, the first power wiring layer 105 may be formed by a combination of photolithography, etching, electroplating or deposition.

[0104] The metal wiring in the first power wiring layer 105 includes a metal wiring for supplying power to the first transistor layer 102 and a metal wiring for supplying power to the metal power wiring.

[0105] Next, see Figure 1 and Figure 7 , executing step S12 , forming a metal bump 500 on the surface of the first power wiring layer 105 , and the metal bump 500 is electrically connected to the first power wiring layer 105 .

[0106] Specifically, the metal bump 500 may include, for example, a solder ball bump, a C4 metal bump, etc. The specific type and material of the metal bump 500 are not overly limited herein.

[0107] As an example, the first signal wiring layer 103, the first power wiring layer 105, the second signal wiring layer, the second power wiring layer, the first rewiring layer 301 and the second rewiring layer 302 can all be prepared using the Damascus process to improve production efficiency, enhance product performance, and extend the service life of the packaging structure.

[0108] Furthermore, when the first semiconductor substrate 101 is a wafer-level or substrate-level substrate, after forming the metal bumps 500, a cutting process step may be included to divide the overall large-size packaging structure into multiple independent packaging monomer structures to improve process efficiency.

[0109] The cutting method may include one or a combination of mechanical cutting and laser cutting, and the specific cutting method may be selected according to needs.

[0110] See also Figure 2 to Figure 7 This embodiment also provides a back side power supply chip packaging structure, and the back side power supply chip packaging structure can be prepared by using the above-mentioned preparation method of the back side power supply chip packaging structure, such as Figure 2 to Figure 7, but not limited to this, this embodiment directly adopts the above-mentioned preparation process to prepare the back power supply chip packaging structure, so the preparation, material and specific structure of the back power supply chip packaging structure can refer to the above-mentioned method.

[0111] Specifically, the back side power supply chip packaging structure includes:

[0112] A first semiconductor substrate 101;

[0113] A first transistor layer 102, wherein the first transistor layer 102 is located on the front side of the first semiconductor substrate 101;

[0114] A passivation layer 104, wherein the passivation layer 104 is located on the back side of the first semiconductor substrate 101;

[0115] a first signal wiring layer 103, wherein the first signal wiring layer 103 is located on the first transistor layer 102, and the first signal wiring layer 103 is electrically connected to the first transistor layer 102;

[0116] A first rewiring layer 301, wherein the first rewiring layer 301 is located on the first signal wiring layer 103, and the first rewiring layer 301 and the first signal wiring layer 103 are both electrically connected;

[0117] Providing a chip, the chip comprising a stacked second semiconductor substrate 201, a second transistor layer 202 and a composite wiring layer 203, the composite wiring layer 203 comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer 202;

[0118] A second rewiring layer 302, the second rewiring layer 302 is located on the composite wiring layer 203, the second rewiring layer 302 is electrically connected to the second signal wiring layer and the second power wiring layer, wherein the first rewiring layer 301 is bonded to the second rewiring layer 302, and the first rewiring layer 301 is electrically connected to the second rewiring layer 302;

[0119] a metal pillar 400 , wherein the metal pillar 400 penetrates the passivation layer 104 , the first semiconductor substrate 101 , and the first transistor layer 102 , and a first end of the metal pillar 400 is electrically connected to both the first signal wiring layer 103 and the first transistor layer 102 ;

[0120] A first power wiring layer 105 , wherein the first power wiring layer 105 is located on a surface of the passivation layer 104 , and the first power wiring layer 105 is electrically connected to a second end of the metal pillar 400 ;

[0121] The metal bump 500 is located on the surface of the first power wiring layer 105 , and the metal bump 500 is electrically connected to the first power wiring layer 105 .

[0122] As an example, the thickness of the first semiconductor substrate 101 is 1-10 μm; the first semiconductor substrate 101 includes a silicon substrate; and the second semiconductor substrate 201 includes a silicon substrate.

[0123] As an example, the passivation layer 104 includes an epoxy resin layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

[0124] As an example, the chip is a memory chip 200 ; the first semiconductor substrate 101 , the first transistor layer 102 , the passivation layer 104 , the first signal wiring layer 103 and the first power wiring layer 105 constitute a back-side power supply logic chip 100 .

[0125] To summarize, the back-side power supply chip packaging structure and the preparation method thereof of the present invention form a back-side power supply logic chip through a first semiconductor substrate, a first transistor layer, a passivation layer, a first signal wiring layer and a first power wiring layer, and utilizes the back-side power supply logic chip to stack the storage chip, thereby effectively reducing the package thickness and the size of the package structure; the back-side power supply logic chip and the metal pillars running through the first transistor layer can effectively shorten the transmission distance and reduce power consumption.

[0126] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a back-side power supply chip packaging structure, characterized in that: The following steps are involved: providing a first semiconductor substrate; forming a first transistor layer on the front surface of the first semiconductor substrate; forming a first signal wiring layer on the first transistor layer, wherein the first signal wiring layer is electrically connected to the first transistor layer; forming a first rewiring layer on the first signal wiring layer, wherein the first rewiring layer is electrically connected to the first signal wiring layer; Providing a chip, the chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer; forming a second rewiring layer on the composite wiring layer, wherein the second rewiring layer is electrically connected to the second signal wiring layer and the second power wiring layer; Bonding the first rewiring layer to the second rewiring layer, and electrically connecting the first rewiring layer to the second rewiring layer; thinning the first semiconductor substrate from the back side of the first semiconductor substrate; forming a passivation layer on the back side of the first semiconductor substrate; forming a metal column penetrating the passivation layer, the first semiconductor substrate and the first transistor layer, wherein a first end of the metal column is electrically connected to both the first signal wiring layer and the first transistor layer; forming a first power wiring layer on the surface of the passivation layer, wherein the first power wiring layer is electrically connected to the second end of the metal column; A metal bump is formed on the surface of the first power wiring layer, and the metal bump is electrically connected to the first power wiring layer.

2. The method for preparing the back side power supply chip packaging structure according to claim 1, characterized in that: The method for thinning the first semiconductor substrate includes one or a combination of a mechanical grinding method and a CMP method; the thickness of the first semiconductor substrate after thinning is 1 to 10 μm.

3. The method for preparing the back side power supply chip packaging structure according to claim 1, characterized in that: The first semiconductor substrate includes a silicon substrate; the second semiconductor substrate includes a silicon substrate.

4. The method for preparing the back side power supply chip packaging structure according to claim 1, characterized in that: The passivation layer includes an epoxy resin layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

5. The method for preparing the back side power supply chip packaging structure according to claim 1, characterized in that: The first signal wiring layer, the first power wiring layer, the second signal wiring layer, the second power wiring layer, the first rewiring layer and the second rewiring layer are all prepared by using a Damascene process.

6. The method for preparing the back side power supply chip packaging structure according to claim 1, characterized in that: The method also includes a cutting process step, wherein the cutting method includes one or a combination of mechanical cutting and laser cutting.

7. A back-side power supply chip packaging structure, characterized in that: The back side power supply chip packaging structure comprises: a first semiconductor substrate; A first transistor layer, wherein the first transistor layer is located on a front surface of the first semiconductor substrate; A passivation layer, the passivation layer is located on the back side of the first semiconductor substrate; a first signal wiring layer, wherein the first signal wiring layer is located on the first transistor layer, and the first signal wiring layer and the first transistor layer are electrically connected; a first rewiring layer, the first rewiring layer being located on the first signal wiring layer and the first rewiring layer being electrically connected to the first signal wiring layer; Providing a chip, the chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer; a second rewiring layer, the second rewiring layer being located on the composite wiring layer, the second rewiring layer being electrically connected to the second signal wiring layer and the second power wiring layer, wherein the first rewiring layer is bonded to the second rewiring layer, and the first rewiring layer is electrically connected to the second rewiring layer; a metal column, wherein the metal column penetrates the passivation layer, the first semiconductor substrate, and the first transistor layer, and a first end of the metal column is electrically connected to both the first signal wiring layer and the first transistor layer; a first power wiring layer, the first power wiring layer being located on a surface of the passivation layer and being electrically connected to the second end of the metal column; A metal bump is located on a surface of the first power wiring layer and is electrically connected to the first power wiring layer.

8. The back side power supply chip packaging structure according to claim 7, characterized in that: The thickness of the first semiconductor substrate is 1-10 μm; the first semiconductor substrate includes a silicon substrate; and the second semiconductor substrate includes a silicon substrate.

9. The back side power supply chip packaging structure according to claim 7, characterized in that: The passivation layer includes an epoxy resin layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

10. The back side power supply chip packaging structure according to claim 7, characterized in that: The chip is a memory chip; the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power wiring layer constitute a back-side power supply logic chip.

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