Three-dimensional packaging structure and preparation method

Abstract

The invention provides a three-dimensional packaging structure which is characterized in that the packaging structure comprises a plurality of single-layer chips which are vertically stacked and interconnected with one another; the plastic packaging material is used for carrying out coating and plastic packaging on the plurality of single-layer chips; the underfill material is filled in a connection gap between the adjacent chip layers; the single-layer chip comprises a plurality of TSV interconnection structures which comprise TSV silicon through holes and copper columns; the main chip comprises an I / O surface and a back surface opposite to the I / O surface; and a plastic packaging layer, wherein the main chip and the TSV interconnection structure are coated with the plastic packaging layer. The invention further provides a three-dimensional structure packaging method, compared with a traditional WB packaging mode, a substrate is omitted, and the packaging thickness is reduced; through the TSV silicon bridge, vertical stacking between the chips is realized. Through the RDL, I / O re-surface distribution is realized, the interconnection density is greatly improved, the interconnection distance is shortened, and the performance is better.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuit packaging, and in particular to a three-dimensional packaging structure and a preparation method thereof. Background Art

[0002] With the development of IC manufacturing technology, the further the manufacturing process node develops, the more its R&D and production costs will increase by dozens or even hundreds of times. Due to the existence of the substrate and the limitation of wire bonding density, the package size cannot be further reduced, and it is difficult to further improve the performance.

[0003] Traditional 3D packaging is often achieved by wire stacking technology. Through-silicon via (TSV) technology can achieve vertical interconnection between chips. By drilling holes in silicon to interconnect chips, wire bonding is not required, which effectively shortens the length of interconnection, reduces signal transmission delay and loss, improves signal transmission speed and bandwidth, reduces power consumption and packaging volume, and achieves multifunctional, high-performance, high-reliability, lighter, thinner, and smaller chip system-level packaging. Summary of the invention

[0004] Therefore, the present invention proposes a three-dimensional packaging structure and a preparation method. Compared with the traditional WB packaging form, the substrate is eliminated and the packaging thickness is reduced; the vertical stacking of chips is achieved through the TSV silicon bridge; the I / O redistribution is achieved through RDL, the interconnection density is greatly improved, the interconnection distance is shortened, and the performance is better.

[0005] In order to solve the above problems, the present invention provides a three-dimensional packaging structure, characterized in that the packaging structure comprises:

[0006] A plurality of single-layer chips, wherein the plurality of single-layer chips are vertically stacked and interconnected with each other;

[0007] A plastic encapsulation material, wherein the plastic encapsulation material is used to encapsulate the plurality of single-layer chips;

[0008] An underfill material is filled in the connection gap between adjacent chip layers;

[0009] The single-layer chip comprises:

[0010] Multiple TSV interconnect structures, including TSV through silicon vias and copper pillars;

[0011] A main chip, including an I / O surface and a back surface opposite to the I / O surface;

[0012] A plastic encapsulation layer, wherein the plastic encapsulation layer covers the main chip and the TSV interconnection structure.

[0013] In one embodiment of the present invention, the TSV interconnect structure includes one or more TSV through silicon vias, the front side of the TSV interconnect structure has one or more copper pillars, the one or more TSV through silicon vias penetrate the front and back sides of the interconnect structure and are connected to the one or more copper pillars on the front side.

[0014] In another embodiment of the present invention, the copper column is exposed from the second surface of the plastic packaging layer.

[0015] In another embodiment of the present invention, it further includes a first redistribution layer and a second redistribution layer;

[0016] The copper column is exposed from the second surface of the plastic encapsulation layer, and the first redistribution layer is formed on the second surface of the plastic encapsulation layer;

[0017] The first surface of the plastic encapsulation layer is opposite to the second surface, the first surface of the plastic encapsulation layer, the I / O surface of the main chip and the back surface of the TSV interconnection structure are in a plane, and the second redistribution layer is arranged on the plane.

[0018] In another embodiment of the present invention, a first surface of the first redistribution layer is electrically connected to the copper pillar, and a pad is provided on a second surface of the first redistribution layer.

[0019] In another embodiment of the present invention, the first surface of the second redistribution layer is electrically connected to the I / O structure of the main chip and the back TSV exposure structure of the TSV interconnection structure, and the second surface of the second redistribution layer has bumps.

[0020] In another embodiment of the present invention, the bumps on the second surface of the second redistribution layer of the single chip layer are electrically connected to the pads on the first redistribution layer of the adjacent chip layer;

[0021] The pads on the first surface of the first redistribution layer of the single-layer chip layer are electrically connected to the bumps on the second redistribution layer of the adjacent chip layer.

[0022] The present invention also provides a three-dimensional packaging structure packaging method, characterized in that it includes the following steps:

[0023] Step 1, fixing the TSV interconnection structure and the main chip on the first carrier through a temporary bonding layer;

[0024] Step 2, plastic sealing and thinning;

[0025] Step 3, fixing the plastic encapsulation layer on the second carrier through a temporary bonding layer, removing the first carrier, and manufacturing a first multiple wiring layer and welding bumps on the I / O surface of the main chip and the back side of the TSV interconnection structure;

[0026] Step 4, bonding the first multi-wiring layer and the side where the solder bumps are located to a third carrier through a temporary bonding layer, and removing the second carrier;

[0027] Step 5, thinning the plastic packaging layer to expose the copper pillars of the TSV interconnection structure;

[0028] Step 6, manufacturing a second multiple wiring layer on the copper pillar surface of the TSV interconnect structure to obtain a first wafer;

[0029] Step 7, repeating steps 1-6 to obtain a second wafer, debonding and dicing the second wafer to obtain a plurality of single-layer chips;

[0030] Step 8, stacking the obtained single-layer chip and the first wafer in multiple layers;

[0031] Step 9, repeating step 8 until a multi-chip vertical interconnect packaging structure with a desired number of layers is obtained;

[0032] Step 10, performing bottom filling and plastic sealing on the stacked first wafer;

[0033] Step 11, debonding and cutting the first wafer after plastic packaging.

[0034] In one embodiment of the present invention, the TSV interconnection structure includes one or more TSV through silicon vias, the front side of the TSV interconnection structure has one or more copper pillars, the one or more TSV through silicon vias penetrate the front and back sides of the interconnection structure and are connected to the one or more copper pillars on the front side.

[0035] In another embodiment of the present invention, the temporary bonding layer is debonded by heating, mechanical, chemical, laser or freezing.

[0036] Compared with the traditional WB packaging form, the present invention has the following beneficial effects:

[0037] By eliminating the substrate, the package thickness is reduced, further reducing the package size.

[0038] Through the TSV silicon bridge, vertical stacking between chips is achieved without the need for wire bonding, which effectively shortens the interconnection length, reduces signal transmission delay and loss, improves signal transmission speed and bandwidth, and reduces power consumption and packaging volume.

[0039] RDL realizes the redistribution of I / O, greatly improves the interconnection density, shortens the interconnection distance and improves the performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of a three-dimensional packaging structure in one embodiment of the present invention is shown;

[0041] Figure 2 A schematic diagram of a single-layer chip structure in one embodiment of the present invention is shown;

[0042] Figure 3 A schematic diagram showing a TSV interconnect structure in one embodiment of the present invention is shown; and

[0043] FIG. 4A to FIG. 4J A schematic diagram of a process of a three-dimensional packaging structure in an embodiment of the present invention is shown. Specific embodiments

[0044] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that

[0045] It is recognized that the embodiments may be implemented without one or more of the specific details or with other alternative and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details.

[0046] Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0047] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0048] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as expressing or implying relative importance. In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily refer to the same embodiment.

[0049] Figure 1 A cross-sectional schematic diagram of a three-dimensional packaging structure in an embodiment of the present invention is shown.

[0050] like Figure 1 As shown, the packaging structure is a multi-layer chip vertical interconnect packaging structure, in which the structural schematic diagram of a single-layer chip is as shown in Figure 2As shown, it includes: a main chip 1, a TSV interconnection structure 2, and a plastic packaging layer 3.

[0051] In an embodiment of the present invention, the main chip 1 includes an I / O surface and a back surface opposite to the I / O surface. A single-layer chip includes a main chip 1 and multiple TSV interconnect structures 2. The main chip 1 and the multiple TSV interconnect structures 2 are arranged in the same single chip layer. By stacking multiple single-layer chips, a three-dimensional packaging structure of a multi-layer chip vertical interconnect packaging is formed. Figure 3 FIG. 4 is a schematic diagram showing a structure of a TSV interconnection structure in an embodiment of the present invention.

[0052] As shown in the figure, the interconnect structure 2 contains one or more through silicon vias TSV, the front side of the interconnect structure 2 has one or more copper pillars 201, and the back side is exposed by TSV. The height of the copper pillar 201 is in the range of 20 to 60 microns. For example, the height of the copper pillar 201 can be about 30 microns, 35 microns, 40 microns, 45 microns or 50 microns. One or more through silicon vias TSV run through the front and back sides of the interconnect structure 2 and are connected to one or more copper pillars 201 on the front side.

[0053] return Figure 2 The plastic encapsulation layer 3 covers the main chip 1 and the TSV interconnection structure 2. The first surface of the plastic encapsulation layer 3, the I / O surface of the main chip 1 and the back surface of the TSV interconnection structure 2 are in a plane, and the second redistribution layer 102 is arranged on the plane. The first surface of the second redistribution layer 102 is electrically connected with the I / O structure of the main chip 1 and the TSV exposed structure on the back surface of the TSV interconnection structure 2, and the second surface of the second redistribution layer 102 has a pad and a bump 103.

[0054] The second surface of the plastic encapsulation layer 3 is opposite to the first surface. The copper pillar 201 is exposed from the second surface of the plastic encapsulation layer 3. The first redistribution layer 101 is formed on the second surface of the plastic encapsulation layer 3. The first surface of the first redistribution layer 101 is electrically connected to the copper pillar 201, and a pad is provided on the second surface of the first redistribution layer 101.

[0055] The first redistribution layer 101 and the second redistribution layer 102 are structures composed of a metal layer and an insulating dielectric layer. The metal layer is used to form an electrical connection, and the insulating dielectric layer is used to isolate the conductive metal layer. In one embodiment of the present invention, the insulating dielectric layer and the metal wiring layer can be prepared by physical vapor deposition (PVD) and etching processes. Alternatively, the redistribution layer RDL wiring can be completed by photolithography, electroplating and etching processes.

[0056] return Figure 1, stacking multiple chip layers in sequence, can obtain a three-dimensional packaging structure of multi-layer chip vertical interconnection packaging. Specifically, the bumps on the second surface of the second redistribution layer of the second chip layer 120 are electrically connected to the pads on the first redistribution layer of the first chip layer 110; the bumps on the second surface of the second redistribution layer of the third chip layer 130 are electrically connected to the pads on the first redistribution layer of the second chip layer 120; the bumps on the second surface of the second redistribution layer of the fourth chip layer 140 are electrically connected to the pads on the first redistribution layer of the third chip layer 130; and so on. The connection gaps between adjacent chip layers are filled with an underfill insulating medium 150. The underfill insulating medium 150 can disperse the stress on the chip surface and thus improve the reliability of the entire product. The bumps on the second surface of the second redistribution layer of the first chip layer 110 are used for external bumps. The plastic encapsulation material 160 covers the first to fourth chip layers.

[0057] In the above embodiment of the present invention, after the plastic encapsulation layer 3 plastic encapsulates a single chip, the metal pillar 201 of the TSV interconnection structure 2 is exposed for connection with the pad of another single chip. Through the TSV silicon bridge, vertical stacking between chips is achieved, and wire bonding is not required, which effectively shortens the interconnection length, reduces signal transmission delay and loss, improves signal transmission speed and bandwidth, and reduces power consumption and packaging volume. The copper pillar 201 of the TSV interconnection structure 2 is welded to the pad of other single chips to achieve electrical connection between multiple chips.

[0058] FIG. 4A to FIG. 4J A cross-sectional schematic diagram is shown of a process of manufacturing a three-dimensional packaging structure in an embodiment of the present invention.

[0059] As shown in the figure, the present invention provides a three-dimensional packaging structure packaging method, which has the following steps:

[0060] Step 1, such as Figure 4A As shown, the TSV interconnect structure 2 and the main chip 1 (I / O side facing downward) are placed on a glass carrier 401 coated with a temporary bonding layer, and used as a functional chip assembled by a single chip. The temporary bonding thin layer is a thermoplastic or thermosetting organic material, or an inorganic material containing components such as Cu, Ni, Cr, Co, etc. The temporary bonding layer can be removed by heating, mechanical, chemical, laser, freezing, etc.

[0061] Step 2, such as Figure 4B As shown, the chip is plastic-sealed to form a plastic-sealing layer 3, and then thinned.

[0062] Step three, such as Figure 4C As shown, the packaged chip is inverted and bonded on another carrier 402, the previous glass carrier 401 is removed, and the first redistribution layer and bumps are manufactured on the main chip surface.

[0063] Step 4: Figure 4D As shown, as in the previous step, the packaged chip is inverted and bonded on another carrier 403, and the temporary carrier 402 is removed.

[0064] Step 5: Figure 4E As shown, the plastic encapsulation layer 3 is thinned to expose the copper pillars of the TSV interconnection structure.

[0065] Step 6: Figure 4F As shown, a second redistribution layer is fabricated on the copper pillar surface of the TSV interconnect structure 2 to obtain a first wafer.

[0066] Step 7: Repeat steps 1 to 6 to obtain a second wafer, debond and cut it to obtain multiple discrete chip layers, such as Figure 4G .

[0067] Step 8: Figure 4H As shown, the C2W method is used to bond the multiple chip layers obtained in step seven to the wafer 1 in a multi-layer stacking manner until the expected number of stacks is obtained.

[0068] Step nine, such as Fig. 4I As shown, the stacked wafers are bottom-filled and plastic-sealed.

[0069] Step 10: Figure 4J As shown, the plastic-sealed wafer is debonded and cut to obtain the three-dimensional packaging structure.

[0070] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A three-dimensional packaging structure, characterized in that: The packaging structure comprises: A plurality of single-layer chips, wherein the plurality of single-layer chips are vertically stacked and interconnected with each other; A plastic encapsulation material, wherein the plastic encapsulation material is used to encapsulate the plurality of single-layer chips; An underfill material is filled in the connection gap between adjacent chip layers; The single-layer chip comprises: Multiple TSV interconnect structures, including TSV through silicon vias and copper pillars; A main chip, including an I / O surface and a back surface opposite to the I / O surface; A plastic encapsulation layer, wherein the plastic encapsulation layer covers the main chip and the TSV interconnection structure.

2. The three-dimensional packaging structure according to claim 1, characterized in that: The TSV interconnect structure includes one or more TSV through silicon vias, the front side of the TSV interconnect structure has one or more copper pillars, the one or more TSV through silicon vias penetrate the front side and back side of the interconnect structure and are connected to the one or more copper pillars on the front side.

3. The three-dimensional packaging structure according to claim 2, characterized in that: The copper column is exposed from the second surface of the plastic packaging layer.

4. The three-dimensional packaging structure according to claim 2, characterized in that: Also includes a first redistribution layer and a second redistribution layer; The copper column is exposed from the second surface of the plastic encapsulation layer, and the first redistribution layer is formed on the second surface of the plastic encapsulation layer; The first surface of the plastic encapsulation layer is opposite to the second surface, the first surface of the plastic encapsulation layer, the I / O surface of the main chip and the back surface of the TSV interconnection structure are in a plane, and the second redistribution layer is arranged on the plane.

5. The three-dimensional packaging structure according to claim 4, characterized in that: The first surface of the first redistribution layer is electrically connected to the copper pillar, and a pad is provided on the second surface of the first redistribution layer.

6. The three-dimensional packaging structure according to claim 4, characterized in that: The first surface of the second redistribution layer is electrically connected to the I / O structure of the main chip and the back TSV exposure structure of the TSV interconnection structure, and the second surface of the second redistribution layer has bumps.

7. The three-dimensional packaging structure according to claim 6, characterized in that: The bumps on the second surface of the second redistribution layer of the single-layer chip layer are electrically connected to the pads on the first redistribution layer of the adjacent chip layer; The pads on the first surface of the first redistribution layer of the single-layer chip layer are electrically connected to the bumps on the second redistribution layer of the adjacent chip layer.

8. A packaging method for a three-dimensional packaging structure, characterized in that: The steps include: Step 1, fixing the TSV interconnection structure and the main chip on the first carrier through a temporary bonding layer; Step 2, plastic sealing and thinning; Step 3, fixing the plastic encapsulation layer on the second carrier through a temporary bonding layer, removing the first carrier, and manufacturing a first multiple wiring layer and welding bumps on the I / O surface of the main chip and the back side of the TSV interconnection structure; Step 4, bonding the first multi-wiring layer and the side where the solder bumps are located to a third carrier through a temporary bonding layer, and removing the second carrier; Step 5, thinning the plastic packaging layer to expose the copper pillars of the TSV interconnection structure; Step 6, manufacturing a second multiple wiring layer on the copper pillar surface of the TSV interconnect structure to obtain a first wafer; Step 7, repeating steps 1-6 to obtain a second wafer, debonding and dicing the second wafer to obtain a plurality of single-layer chips; Step 8, stacking the obtained single-layer chip and the first wafer in multiple layers; Step 9, repeating step 8 until a multi-chip vertical interconnect packaging structure with a desired number of layers is obtained; Step 10, performing bottom filling and plastic sealing on the stacked first wafer; Step 11, debonding and cutting the first wafer after plastic packaging.

9. The packaging method of the three-dimensional packaging structure according to claim 8, characterized in that: The TSV interconnect structure includes one or more TSV through silicon vias, the front side of the TSV interconnect structure has one or more copper pillars, the one or more TSV through silicon vias penetrate the front side and back side of the interconnect structure and are connected to the one or more copper pillars on the front side.

10. The packaging method of the three-dimensional packaging structure according to claim 8, characterized in that: The temporary bond layer is debonded by heat, mechanical, chemical, laser or freezing.

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