Method for forming double-shallow-trench isolation structure with different depths and semiconductor device

Abstract

The invention provides a forming method of a double-shallow-trench isolation structure with different depths and a semiconductor device, and the method comprises the steps: S1, providing a substrate which comprises a first region and a second region; s2, sequentially forming a first dielectric layer, a first hard mask layer and a second hard mask layer on the substrate, wherein the first hard mask layer and the second hard mask layer are made of different materials; s3, forming a first initial opening in the second hard mask layer of the first region, performing etching by taking the second hard mask layer as a mask, and stopping forming a first opening on the surface of the first dielectric layer; s4, forming a second initial opening in the second hard mask layer of the second region, etching by taking the second hard mask layer as a mask, and stopping on the surface of the substrate to form a second opening; s5, removing the second hard mask layer; and S6, etching the first opening and the second opening at the same time by taking the first hard mask layer as a mask, forming a first shallow trench below the first opening, and forming a second shallow trench below the second opening. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a double shallow trench isolation structure with different depths and a semiconductor device. Background Art

[0002] In the field of semiconductor manufacturing, efficient isolation technology is indispensable for achieving independent operation of each component of an integrated circuit. Shallow trench isolation (STI) structure plays a core role in this process, especially in different manufacturing processes. In order to achieve an STI structure with a specific depth requirement, the traditional process method usually involves two photolithography and two etching steps. Specifically, the first trench and the second trench are first etched to the same depth, and then the first trench is covered with a photoresist, and the second trench is further etched to reach the specified depth. In this process, the silicon nitride around the second trench is consumed as an etching mask, while the silicon nitride around the first trench is retained due to the protection of the photoresist, thereby forming a height difference of the silicon nitride. This height difference may cause uneven load in the subsequent chemical mechanical polishing process, and then produce nitride residues after removing the silicon nitride, and cause the problem of inconsistent silicon oxide height between the first region and the second region, which ultimately affects the yield of the semiconductor device. Summary of the invention

[0003] In order to solve all or part of the problems of the above-mentioned prior art, the present invention provides a method for forming a double shallow trench isolation structure and a semiconductor device with different depths, wherein the depth difference between the first shallow trench and the second shallow trench is directly determined by the thickness of the first dielectric layer, thereby achieving precise control of the trench depth.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A method for forming a dual shallow trench isolation structure with different depths comprises the following steps:

[0006] S1. Providing a substrate, wherein the substrate comprises two different processing regions: a first region and a second region;

[0007] S2. forming a first dielectric layer, a first hard mask layer of different materials, and a second hard mask layer in sequence on the substrate;

[0008] S3. forming a first initial opening on the second hard mask layer in the first region, performing etching using the second hard mask layer as a mask, and stopping the etching at the surface of the first dielectric layer to form a first opening;

[0009] S4. forming a second initial opening on the second hard mask layer in the second region, performing etching using the second hard mask layer as a mask, and stopping the etching on the surface of the substrate to form a second opening;

[0010] S5. removing the second hard mask layer;

[0011] S6. Using the first hard mask layer as a mask, simultaneously etching the areas below the first opening and the second opening to form a first shallow trench below the first opening and a second shallow trench below the second opening.

[0012] The depth of the first shallow groove of the present invention is designed to be less than the depth of the second shallow groove. In step S6, the second shallow groove is etched to a preset depth by a precise etching process to determine its final depth. The depth difference between the first shallow groove and the second shallow groove is determined by the thickness of the first dielectric layer. This design makes the two grooves different in depth to meet different circuit performance requirements.

[0013] The depth of the first shallow trench is less than that of the second shallow trench. The depth of the second shallow trench is determined by etching to a preset depth in step S6. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

[0014] Step S3 further comprises the following steps:

[0015] S3.1 forming a first patterned photoresist layer on a surface of the second hard mask layer;

[0016] S3.2 using the first patterned photoresist layer as a mask, etching through the second hard mask layer in the first region, stopping at the surface of the first hard mask layer, to form the first initial opening;

[0017] S3.3 removing the first patterned photoresist layer.

[0018] Step S3 further comprises the following steps:

[0019] S3.1 forming a dielectric anti-reflective layer and a first patterned photoresist layer in sequence on a surface of the second hard mask layer;

[0020] S3.2 using the first patterned photoresist layer as a mask, etching through the dielectric anti-reflective layer and the second hard mask layer in the first region, stopping at the surface of the first hard mask layer, to form the first initial opening;

[0021] S3.3 removing the first patterned photoresist layer and the dielectric anti-reflective layer.

[0022] 5. The forming method according to claim 1, characterized in that step S4 further comprises the following steps:

[0023] S4.1 forming a second patterned photoresist layer in the first opening and on the second hard mask layer;

[0024] S4.2 using the second patterned photoresist layer as a mask, etching through the second hard mask layer in the second region, stopping at the surface of the first hard mask layer, to form the second initial opening;

[0025] S4.3 retain the second patterned photoresist layer, and use the second patterned photoresist layer and the second hard mask layer as masks to etch the second initial opening, and stop etching at the surface of the substrate to form the second opening.

[0026] The substrate is silicon, the first dielectric layer is silicon dioxide, the first hard mask layer is silicon nitride, and the second hard mask layer is amorphous carbon.

[0027] The thickness of the first hard mask layer is 40 angstroms to 400 angstroms, and the thickness of the second hard mask layer is 200 angstroms to 1500 angstroms.

[0028] The present invention also provides a method for forming a dual shallow trench isolation structure with different depths, comprising the following steps:

[0029] S1. Providing a substrate, wherein the substrate comprises two different processing regions: a first region and a second region;

[0030] S2. forming a first dielectric layer, a first hard mask layer of different materials, and a second hard mask layer in sequence on the substrate;

[0031] S3. forming a first initial opening on the second hard mask layer in the first region, stopping at the surface of the first hard mask layer;

[0032] S4. forming a second initial opening on the second hard mask layer in the second region, performing etching using the second hard mask layer as a mask, and stopping the etching on the surface of the substrate to form a second opening;

[0033] S6. Using the second hard mask layer as a mask, the areas below the first initial opening and the second opening are etched simultaneously to form a first shallow groove below the first initial opening and a second shallow groove below the second opening; the depth of the second shallow groove is determined by etching to a preset depth, and the depth difference between the first shallow groove and the second shallow groove is determined by the thickness of the first hard mask layer and the first dielectric layer.

[0034] After forming the first shallow trench and the second shallow trench, the method further comprises the following steps:

[0035] S7. forming a second dielectric layer inside the first shallow trench and the second shallow trench and above the first hard mask layer;

[0036] S8. performing a chemical mechanical polishing process to remove the second dielectric layer above the first hard mask layer to expose the surface of the first hard mask layer;

[0037] S9. Remove the first hard mask layer to form shallow trench isolation structures of two depths.

[0038] The present invention also provides a method for forming a semiconductor device, which adopts the above-mentioned method for forming a dual shallow trench isolation structure with different depths to form two shallow trench isolation structures with different depths. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 Flow chart of a method for forming a dual shallow trench isolation structure in an embodiment of the present invention.

[0041] Figure 2 It is a schematic structural diagram of forming a first patterned photoresist layer in an embodiment of the present invention.

[0042] Figure 3 It is a schematic diagram of the structure of forming a first initial opening in an embodiment of the present invention.

[0043] Figure 4 FIG. 4 is a schematic diagram of a structure for forming a first opening in an embodiment of the present invention.

[0044] Figure 5 It is a schematic diagram of the structure of forming a second patterned photoresist layer in an embodiment of the present invention.

[0045] Figure 6 A schematic diagram of a structure for forming a second initial opening in an embodiment of the present invention

[0046] Figure 7 FIG. 4 is a schematic diagram of a structure for forming a second opening in an embodiment of the present invention.

[0047] Figure 8 A schematic diagram of the structure of removing the second patterned photoresist layer and the second hard mask layer in an embodiment of the present invention;

[0048] Fig. 9A schematic diagram of a structure for forming a first shallow trench and a second shallow trench in an embodiment of the present invention;

[0049] Fig.10 is a schematic structural diagram of forming a second dielectric layer in an embodiment of the present invention;

[0050] Fig.11 It is a structural schematic diagram of removing the second dielectric layer on the first hard mask layer in an embodiment of the present invention;

[0051] Fig.12 It is a schematic structural diagram of forming a dual shallow trench isolation structure of different depths in an embodiment of the present invention.

[0052] Figure numerals: 1-first region; 101-first initial opening; 102-first opening; 103-first shallow trench; 2-second region; 201-second initial opening; 202-first opening; 203-second shallow trench; 3-first dielectric layer; 4-first hard mask layer; 5-second hard mask layer; 6-first patterned photoresist layer; 7-second patterned photoresist layer; 8-second dielectric layer; 9-first shallow trench isolation structure; 10-second shallow trench isolation structure. DETAILED DESCRIPTION

[0053] The technical solutions in the specific embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] Example 1

[0055] In the embodiment of the present invention, in combination with reference Figure 1-Figure 12 As shown, a method for forming a dual shallow trench isolation structure with different depths is provided, comprising the following steps:

[0056] S1. Provide a substrate, the substrate comprising two different processing regions: a first region 1 and a second region 2;

[0057] S2. Forming a first dielectric layer 3, a first hard mask layer 4 of different materials, and a second hard mask layer 5 in sequence on the substrate;

[0058] S3. forming a first initial opening 101 on the second hard mask layer 5 in the first region 1, performing etching using the second hard mask layer 5 as a mask, and stopping the etching on the surface of the first dielectric layer 3 to form a first opening 102;

[0059] S4. A second initial opening 201 is formed on the second hard mask layer 5 in the second region 2, and etching is performed using the second hard mask layer 5 as a mask, and the etching stops at the substrate surface to form a second opening 202;

[0060] S5. removing the second hard mask layer 5;

[0061] S6 . Using the first hard mask layer 4 as a mask, the regions below the first opening 102 and the second opening 202 are etched simultaneously to form a first shallow trench 103 below the first opening 102 and a second shallow trench 203 below the second opening 202 .

[0062] The depth of the first shallow groove 103 is designed to be less than the depth of the second shallow groove 203. In step S6, the second shallow groove 203 is etched to a preset depth by a precise etching process to determine its final depth. The depth difference between the first shallow groove 103 and the second shallow groove 203 is determined by the thickness of the first dielectric layer 3. This design allows the two grooves to differ in depth to meet different circuit performance requirements.

[0063] In step S1, a semiconductor substrate is provided, which has a clear layout plan and includes at least two regions that require different processing depths, namely a first region 1 and a second region 2. These two regions are intended to form shallow trench isolation structures with different depths according to the specific requirements of subsequent circuit design. In this embodiment, silicon (Si) is selected as the substrate material. However, in other specific embodiments, the choice of substrate material can be more extensive, including but not limited to other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0064] In step S2, firstly, a first dielectric layer 3 is formed on the substrate in sequence. The layer can be used as a buffer layer or a pad dielectric layer (PAD OXIDE), and its main function is to relieve the stress between the first hard mask layer 4 and the substrate. In this embodiment, the first dielectric layer 3 is an oxide layer, which is formed by a thermal oxidation process, and the specific material is silicon dioxide (SiO2). Then, a first hard mask layer 4 is formed on the first dielectric layer 3, which is composed of silicon nitride and is formed by a process such as PECVD. The thickness of the first hard mask layer 4 ranges from 40 angstroms to 400 angstroms. Finally, a second hard mask layer 5 is formed on the first hard mask layer 4, which is composed of amorphous carbon and is also formed by a process such as PECVD. The thickness of the second hard mask layer 5 ranges from 200 angstroms to 1500 angstroms. Since the second hard mask layer 5 is used as a mask in both the steps of forming the first opening 102 and the second opening 202 , and the first hard mask layer 4 is used as a mask only when forming the first shallow trench 103 and the second shallow trench 203 , the thickness of the first hard mask layer 4 does not need to be too thick.

[0065] In step S3, first, a first initial opening 101 is formed on the second hard mask layer 5 of the first region 1, specifically including the following steps: S3.1 A first patterned photoresist layer 6 is formed on the surface of the second hard mask layer 5; this step is implemented by a photolithography process, and is intended to define the area for subsequent etching. S3.2 Using the first patterned photoresist layer 6 as a mask, the second hard mask layer 5 of the first region 1 is etched through, and stops on the surface of the first hard mask layer 4 to form a first initial opening 101; in this embodiment, the etching process adopts a dry etching process, and the etching gas used is CF4, and its gas flow rate is controlled between 50sccm-150sccm. S3.3 In the process of forming the first initial opening 101, the first patterned photoresist layer 6 may be completely consumed, or there may be residue. If the photoresist layer is not completely consumed, an additional process step of removing the photoresist is required. This can usually be done by removing the residual photoresist through an ashing process or stripping. Finally, etching is performed using the second hard mask layer 5 as a mask until the etching stops at the surface of the first dielectric layer 3 , thereby forming a first opening 102 .

[0066] In order to further optimize the effect of the photolithography process, in step S3, a dielectric anti-reflection layer can be formed between the second hard mask layer 5 and the first patterned photoresist layer 6. The function of this dielectric anti-reflection layer is to reflect the light in the photolithography process, thereby ensuring that the pattern of the initial opening is more regular and precise. In the subsequent operation process, the first patterned photoresist layer 6 is continued to be used as a mask to etch the dielectric anti-reflection layer and the second hard mask layer 5 of the first area 1. When the etching reaches the surface of the first hard mask layer 4, it stops immediately, thereby forming a first initial opening 101. After the etching is completed, the first patterned photoresist layer 6 and the dielectric anti-reflection layer are removed by chemical or physical methods.

[0067] In step S4, first, a second initial opening 201 is formed on the second hard mask layer 5 of the second region 2, specifically including the following steps: S4.1 A second patterned photoresist layer 7 is formed in the first opening 102 and on the surface of the second hard mask layer 5; this step is achieved by a photolithography process. S4.2 Using the second patterned photoresist layer 7 as a mask, etching penetrates the second hard mask layer 5 of the second region 2, stops on the surface of the first hard mask layer 4, and forms the second initial opening 201; in this embodiment, the etching process adopts a dry etching process, and the etching gas used is CF4, and its gas flow rate is controlled between 50sccm-150sccm. S4.3 Retain the remaining second patterned photoresist layer 7, or form a second patterned photoresist layer 7 again in the first opening 102 of the first region 1 and on the second hard mask layer 5, and use the second patterned photoresist layer 7 and the second hard mask layer 5 as masks to etch the second initial opening 201 until the etching stops on the surface of the substrate, thereby forming a second opening 202.

[0068] In steps S5 and S6, a wet etching process is used to remove the second hard mask layer 5. Then, the first hard mask layer 4 is used as a mask, and the areas below the first opening 102 and the second opening 202 are simultaneously etched. In this embodiment, the etching process adopts a dry etching process, and the etching gas used is CF4, and its gas flow rate is controlled between 50sccm-150sccm. Finally, a first shallow trench 103 is formed below the first opening 102; at the same time, a second shallow trench 203 is formed below the second opening 202. After the formation of the shallow trench is completed, the subsequent process steps are further performed: S7. A second dielectric layer 8 is formed inside the first shallow trench 103 and the second shallow trench 203 and above the first hard mask layer 4; in this embodiment, the second dielectric layer 8 is silicon oxide, which is formed by the HARP process. In the HARP process, TEOS (tetraethyl orthosilicate) and O3 are used as process gases. S8. Perform a chemical mechanical polishing (CMP) process to remove the second dielectric layer 8 above the first hard mask layer 4, and use the first hard mask layer 4 as a polishing stop layer to significantly improve the polishing effect. S9. Use a wet etching process to remove the first hard mask layer 4 to form a double shallow trench isolation structure consisting of a first shallow trench isolation structure 9 and a second shallow trench isolation structure 10.

[0069] In an embodiment of the present invention, Si is selected as the substrate material, and SiO2 is used as the material of the first dielectric layer 3. It is worth noting that SiO2 and Si show a selectivity close to 1 under specific etching conditions, which means that the two show very similar etching rates or chemical reaction rates during the etching process. Therefore, the depth difference between the first shallow trench 103 and the second shallow trench 203 is close to or even equal to the thickness of the first dielectric layer 3 (SiO2). This method greatly simplifies the process flow, improves production efficiency, and ensures the high precision and reliability of the shallow trench isolation structure. By controlling the thickness of the first dielectric layer 3 (SiO2), the depth difference between the first shallow trench 103 and the second shallow trench 203 can be indirectly and accurately regulated, thereby meeting the strict requirements of semiconductor devices for fine structure size and excellent performance.

[0070] Example 2

[0071] A method for forming a dual shallow trench isolation structure with different depths is provided, comprising the following steps:

[0072] S1. Provide a substrate, the substrate comprising two different processing regions: a first region 1 and a second region 2;

[0073] S2. Forming a first dielectric layer 3, a first hard mask layer 4 of different materials, and a second hard mask layer 5 in sequence on the substrate;

[0074] S3. forming a first initial opening 101 on the second hard mask layer 5 in the first region 1, stopping at the surface of the first hard mask layer 4;

[0075] S4. A second initial opening 201 is formed on the second hard mask layer 5 in the second region 2, and etching is performed using the second hard mask layer 5 as a mask, and the etching stops at the substrate surface to form a second opening 202;

[0076] S6. Using the second hard mask layer 5 as a mask, the area below the first initial opening 101 and the second opening 202 is etched at the same time to form a first shallow groove 103 below the first initial opening 101 and a second shallow groove 203 below the second opening 202; the depth of the second shallow groove 203 is determined by etching to a preset depth, and the depth difference between the first shallow groove 103 and the second shallow groove 203 is determined by the thickness of the first hard mask layer 4 and the first dielectric layer 3.

[0077] The main difference from Example 1 is that in step S3, the method forms a first initial opening 101 on the second hard mask layer 5 in the first area 1, and stops on the surface of the first hard mask layer 4. In step S6, the second hard mask layer 5 is used as a mask to simultaneously etch the area below the first initial opening 101 and the second opening 202, forming a first shallow trench 103 below the first initial opening 101, and forming a second shallow trench 203 below the second opening 202. The depth of the second shallow trench 203 is determined by controlling the etching to a preset depth, and the depth difference between the first shallow trench 103 and the second shallow trench 203 is jointly determined by the thickness of the first hard mask layer 4 and the first dielectric layer 3. By determining the etching rate ratio of the first hard mask layer and the first dielectric layer 3 to the substrate, respectively, the depth difference formed between the first shallow trench 103 and the second shallow trench 203 during the etching process can be effectively controlled.

[0078] Example 3

[0079] A method for forming a semiconductor device, using the method for forming a dual shallow trench isolation structure with different depths described in Embodiment 1 or Embodiment 2 to form two shallow trench isolation structures with different depths, aiming to improve the overall performance of the semiconductor device by using shallow trench isolation structures with different depths.

[0080] It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principles of the present invention. These improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for forming a dual shallow trench isolation structure with different depths, characterized in that: The following steps are involved: S1. Providing a substrate, wherein the substrate comprises two different processing regions: a first region and a second region; S2. forming a first dielectric layer, a first hard mask layer of different materials, and a second hard mask layer in sequence on the substrate; S3. forming a first initial opening on the second hard mask layer in the first region, performing etching using the second hard mask layer as a mask, and stopping the etching at the surface of the first dielectric layer to form a first opening; S4. forming a second initial opening on the second hard mask layer in the second region, performing etching using the second hard mask layer as a mask, and stopping the etching on the surface of the substrate to form a second opening; S5. removing the second hard mask layer; S6. Using the first hard mask layer as a mask, simultaneously etching the areas below the first opening and the second opening to form a first shallow trench below the first opening and a second shallow trench below the second opening.

2. The forming method according to claim 1, characterized in that: The depth of the first shallow trench is less than that of the second shallow trench. The depth of the second shallow trench is determined by etching to a preset depth in step S6. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

3. The forming method according to claim 1, characterized in that: Step S3 further comprises the following steps: S3.1 forming a first patterned photoresist layer on a surface of the second hard mask layer; S3.2 using the first patterned photoresist layer as a mask, etching through the second hard mask layer in the first region, stopping at the surface of the first hard mask layer, to form the first initial opening; S3.3 removing the first patterned photoresist layer.

4. The forming method according to claim 1, characterized in that: Step S3 further comprises the following steps: S3.1 forming a dielectric anti-reflective layer and a first patterned photoresist layer in sequence on a surface of the second hard mask layer; S3.2 using the first patterned photoresist layer as a mask, etching through the dielectric anti-reflective layer and the second hard mask layer in the first region, stopping at the surface of the first hard mask layer, to form the first initial opening; S3.3 removing the first patterned photoresist layer and the dielectric anti-reflective layer.

5. The forming method according to claim 1, characterized in that: Step S4 further comprises the following steps: S4.1 forming a second patterned photoresist layer in the first opening and on the second hard mask layer; S4.2 using the second patterned photoresist layer as a mask, etching through the second hard mask layer in the second region, stopping at the surface of the first hard mask layer, to form the second initial opening; S4.3 retain the second patterned photoresist layer, and use the second patterned photoresist layer and the second hard mask layer as masks to etch the second initial opening, and stop etching at the surface of the substrate to form the second opening.

6. The forming method according to claim 1, characterized in that: The substrate is silicon, the first dielectric layer is silicon dioxide, the first hard mask layer is silicon nitride, and the second hard mask layer is amorphous carbon.

7. The forming method according to claim 6, characterized in that: The thickness of the first hard mask layer is 40 angstroms to 400 angstroms, and the thickness of the second hard mask layer is 200 angstroms to 1500 angstroms.

8. A method for forming a dual shallow trench isolation structure with different depths, characterized in that: The following steps are involved: S1. Providing a substrate, wherein the substrate comprises two different processing regions: a first region and a second region; S2. forming a first dielectric layer, a first hard mask layer of different materials, and a second hard mask layer in sequence on the substrate; S3. forming a first initial opening on the second hard mask layer in the first region, stopping at the surface of the first hard mask layer; S4. forming a second initial opening on the second hard mask layer in the second region, performing etching using the second hard mask layer as a mask, and stopping the etching on the surface of the substrate to form a second opening; S6. Using the second hard mask layer as a mask, etching the area below the first initial opening and the second opening at the same time, forming a first shallow trench below the first initial opening and forming a second shallow trench below the second opening; The depth of the second shallow trench is determined by etching to a preset depth, and the depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first hard mask layer and the first dielectric layer.

9. The forming method according to claim 1 or 8, characterized in that: After forming the first shallow trench and the second shallow trench, the method further comprises the following steps: S7. forming a second dielectric layer inside the first shallow trench and the second shallow trench and above the first hard mask layer; S8. performing a chemical mechanical polishing process to remove the second dielectric layer above the first hard mask layer to expose the surface of the first hard mask layer; S9. Remove the first hard mask layer to form shallow trench isolation structures of two depths.

10. A method for forming a semiconductor device, characterized in that: The method for forming a dual shallow trench isolation structure with different depths as claimed in any one of claims 1 to 9 is adopted to form two shallow trench isolation structures with different depths.

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