Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: a gate structure is arranged on a substrate, a source-drain region is arranged in the substrate at at least one side of the gate structure, and an interlayer dielectric layer is formed on the gate structure and the substrate; a first groove and a second groove are formed in the interlayer dielectric layer, the position of the first groove corresponds to that of the gate structure, and the position of the second groove corresponds to that of the source-drain region; forming a lateral barrier layer on the side wall of the first groove and the side wall of the second groove; dielectric structures are formed in the first groove and the second groove of which the side walls are provided with the lateral barrier layers; a first through hole and a second through hole which penetrate through the dielectric structure and the interlayer dielectric layer in sequence are formed, the first through hole is formed in the gate structure, and the second through hole is formed in the source-drain region. The lateral barrier layer delays the etching rate of the first through hole and the second through hole in the direction parallel to the surface of the substrate, and the phenomenon that the critical sizes of the first through hole and the second through hole are too large due to over-etching at the top positions of the first through hole and the second through hole is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Semiconductor integrated circuits are integrated on the same wafer, i.e., semiconductor substrate, such as silicon substrate. Each doped region of the integrated circuit device on the wafer needs to be led out through contact holes and metal layers, which form a metal interconnection structure. In the semiconductor manufacturing process, silicon contact hole etching mainly forms two structures, one is the contact hole on the polysilicon gate, and the other is the contact hole on the active area (formed on the electron / hole heavily doped silicon substrate).

[0003] However, the current contact hole forming method still needs to be improved. Summary of the invention

[0004] The problem solved by the present invention is how to improve the morphology of the contact hole so that the critical dimensions of the contact hole located on the source and drain regions and the contact hole located on the gate structure will not be too large, and no bridging occurs between the conductive plug in the contact hole on the source and drain regions and the conductive plug in the contact hole on the gate structure.

[0005] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a gate structure, the substrate having a source-drain region on at least one side of the gate structure, and an interlayer dielectric layer formed on the gate structure and the substrate; forming a first groove and a second groove in the interlayer dielectric layer, the position of the first groove corresponds to the gate structure, and the position of the second groove corresponds to the position of the source-drain region; forming a lateral barrier layer on the sidewall of the first groove and the sidewall of the second groove; forming a dielectric structure in the first groove and the second groove with the lateral barrier layer formed on the sidewall; forming a first through hole and a second through hole that successively penetrate the dielectric structure and the interlayer dielectric layer, the first through hole is located on the gate structure, and the second through hole is located on the source-drain region.

[0006] Optionally, the width of the first through hole is smaller than the width of the first groove, and the width of the second through hole is smaller than the width of the second groove.

[0007] Optionally, the step of forming a dielectric structure in the first groove and the second groove having the lateral barrier layer formed on the sidewall includes: filling an initial dielectric structure in the first groove and the second groove; and flattening the initial dielectric structure until the surface of the initial dielectric structure is flush with the surface of the lateral barrier layer to form the dielectric structure.

[0008] Optionally, in the step of providing a substrate, the substrate and the gate structure also have a front barrier layer, and the interlayer dielectric layer is located on the front barrier layer; the step of forming a first through hole and a second through hole that successively penetrate the dielectric structure and the interlayer dielectric layer includes: forming a first mask layer with an opening on the dielectric structure and the interlayer dielectric layer, the opening is located at a corresponding position of the dielectric structure and the opening exposes the surface of the dielectric structure; using the first mask layer as a mask, etching the dielectric structure and the interlayer dielectric layer until the front barrier layer is exposed; removing the exposed front barrier layer to form the first through hole and the second through hole.

[0009] Optionally, after etching the dielectric structure and the interlayer dielectric layer, and before removing the exposed front barrier layer, the first mask layer is removed.

[0010] Optionally, in the process of removing the exposed front barrier layer, the lateral barrier layers located on the interlayer dielectric layer, on the sidewalls of the first groove and on the sidewalls of the second groove are removed.

[0011] Optionally, the material of the front barrier layer is the same as the material of the lateral barrier layer.

[0012] Optionally, the step of forming the first groove and the second groove in the interlayer dielectric layer includes: forming a second mask layer on the interlayer dielectric layer, the second mask layer exposing a portion of the interlayer dielectric layer; using the second mask layer as a mask, etching the interlayer dielectric layer to form the first groove and the second groove.

[0013] Optionally, in the step of forming a lateral barrier layer on the sidewalls of the first groove and the sidewalls of the second groove, the lateral barrier layer is also formed on the interlayer dielectric layer, the bottom of the first groove and the bottom of the second groove.

[0014] Optionally, the step of forming a lateral barrier layer on the sidewalls of the first groove and the sidewalls of the second groove includes: forming an initial lateral barrier layer on the interlayer dielectric layer, the sidewalls of the first groove, the bottom of the first groove, the sidewalls of the second groove and the bottom of the second groove by chemical vapor deposition; and performing surface nitridation treatment on the initial lateral barrier layer to form the lateral barrier layer.

[0015] Optionally, the material of the interlayer dielectric layer is silicon oxide; the material of the dielectric structure is silicon oxide; and the material of the lateral blocking layer is silicon nitride.

[0016] Optionally, the method further includes: after forming the first through hole and the second through hole, forming a first conductive plug located in the first through hole and a second conductive plug located in the second through hole.

[0017] Optionally, the step of forming a first conductive plug in the first through hole and a second conductive plug in the second through hole includes: filling the first through hole and the second through hole with conductive material, respectively, to form an initial first conductive plug in the first through hole and an initial second conductive plug in the second through hole; and performing planarization on the initial first conductive plug, the initial second conductive plug and the interlayer dielectric layer to form a first conductive plug in the first through hole and a second conductive plug in the second through hole.

[0018] Optionally, in the step of forming a first conductive plug in the first through hole and a second conductive plug in the second through hole, the first conductive plug is electrically connected to the gate structure, and the second conductive plug is electrically connected to the source and drain region.

[0019] Correspondingly, the present invention further provides a semiconductor structure, which is formed by any of the above-mentioned methods for forming a semiconductor structure.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the method for forming a semiconductor structure of the technical solution of the present invention, the lateral barrier layer slows down the etching rate of the first through hole and the second through hole in the direction parallel to the substrate surface, effectively reduces the phenomenon that the top positions of the first through hole and the second through hole are over-etched, causing the critical dimensions of the first through hole and the second through hole to be too large, and reduces the probability that the conductive material in the first through hole located on the gate structure and the conductive material in the second through hole located on the source and drain region are bridged and short-circuited when the conductive material is filled in the first through hole and the second through hole, causing the yield of the semiconductor device to decrease; and after the dielectric structure is formed in the first groove and the second groove with the lateral barrier layer formed on the sidewall, the first through hole and the second through hole are formed in a manner of successively penetrating the dielectric structure and the interlayer dielectric layer, Compared with the method of directly etching the interlayer dielectric layer to form the first through hole and the second through hole after forming the lateral barrier layer, the surfaces of the dielectric structure and the lateral barrier layer are flat, which is conducive to forming a photoresist layer on the dielectric structure and the lateral barrier layer and performing a photolithography process, thereby improving the alignment accuracy of the photolithography process when forming the first through hole and the second through hole, thereby improving the etching accuracy of the first through hole and the second through hole formed by etching; in addition, in the process of etching to form the first through hole and the second through hole, the lateral barrier layer located on the interlayer dielectric layer, the lateral barrier layer located on the side wall of the first groove, and the lateral barrier layer located on the side wall of the second groove are synchronously consumed, so that the openings at the tops of the first through hole and the second through hole formed are slightly enlarged, which is conducive to the filling of conductive materials.

[0022] In an optional solution of the present invention, the initial lateral barrier layer is subjected to a surface nitridation treatment to form the lateral barrier layer. The nitridation treatment improves the compactness of the lateral barrier layer, thereby improving the etching resistance of the lateral barrier layer in the process of etching to form the first through hole and the second through hole, effectively reducing the occurrence of over-etching at the top of the first through hole and the second through hole, which causes the critical dimensions of the first through hole and the second through hole to be too large, and reducing the probability of the conductive material in the first through hole located on the gate structure bridging and short-circuiting with the conductive material in the second through hole located on the source and drain region when the conductive material is filled in the first through hole and the second through hole, resulting in a decrease in the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 to Figure 2 is a schematic structural diagram of each step of a formation process of a semiconductor structure according to an embodiment;

[0024] Figures 3 to 13 It is a structural schematic diagram of each step of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] As can be seen from the background technology, there are still problems with the morphology of the contact hole in the prior art. The reasons for the problems are now analyzed in conjunction with an embodiment:

[0026] Please refer to Figure 1 A substrate 100 is provided, wherein the substrate 100 has a gate structure 101, wherein the substrate 100 has a source and drain region on at least one side of the gate structure 101, and an interlayer dielectric layer 102 is formed on the gate structure 101 and the substrate 100.

[0027] Please refer to Figure 2 , forming a mask layer on the interlayer dielectric layer 102, wherein the mask layer exposes a portion of the interlayer dielectric layer 102; using the mask layer as a mask, etching the interlayer dielectric layer 102 to form a first through hole and a second through hole penetrating the interlayer dielectric layer 102, wherein the first through hole is located on the gate structure 101, and the second through hole is located on the source and drain region; forming a first conductive plug 103 located in the first through hole and a second conductive plug 104 located in the second through hole.

[0028] The interlayer dielectric layer 102 is relatively thick. When etching to form the first through hole and the second through hole with a high aspect ratio, it is easy to cause over-etching at the top of the first through hole and the second through hole, resulting in an increase in the critical dimensions of the formed first through hole and the second through hole, and the morphology of the first through hole and the second through hole is not good. When forming the first conductive plug 103 located in the first through hole and the second conductive plug 104 located in the second through hole, the first conductive plug 103 and the second conductive plug 104 are prone to bridge, resulting in a decrease in the yield of the semiconductor device.

[0029] To solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a gate structure, the substrate having a source-drain region on at least one side of the gate structure, and an interlayer dielectric layer formed on the gate structure and the substrate; forming a first groove and a second groove in the interlayer dielectric layer, the position of the first groove corresponds to the gate structure, and the position of the second groove corresponds to the position of the source-drain region; forming a lateral barrier layer on the sidewalls of the first groove and the second groove; forming a dielectric structure in the first groove and the second groove with the lateral barrier layer formed on the sidewalls; forming a first through hole and a second through hole that successively penetrate the dielectric structure and the interlayer dielectric layer, the first through hole is located on the gate structure, and the second through hole is located on the source-drain region.

[0030] In the method for forming a semiconductor structure of the technical solution of the present invention, the lateral barrier layer slows down the etching rate of the first through hole and the second through hole in the direction parallel to the substrate surface, effectively reduces the phenomenon that the top positions of the first through hole and the second through hole are over-etched, causing the critical dimensions of the first through hole and the second through hole to be too large, and reduces the probability that when the conductive material is filled in the first through hole and the second through hole, the conductive material in the first through hole located on the gate structure and the conductive material in the second through hole located on the source and drain region are bridged and short-circuited, causing the yield of the semiconductor device to decrease; and after the dielectric structure is formed in the first groove and the second groove with the lateral barrier layer formed on the sidewall, the first through hole and the second through hole that successively penetrate the dielectric structure and the interlayer dielectric layer are formed. Compared with the method of directly etching the interlayer dielectric layer to form the first through hole and the second through hole after forming the lateral barrier layer, the surfaces of the dielectric structure and the lateral barrier layer are flat, which is conducive to forming a photoresist layer on the dielectric structure and the lateral barrier layer and performing a photolithography process, thereby improving the alignment accuracy of the photolithography process when forming the first through hole and the second through hole, thereby improving the etching accuracy of the first through hole and the second through hole formed by etching; in addition, in the process of etching to form the first through hole and the second through hole, the lateral barrier layer located on the interlayer dielectric layer, the lateral barrier layer located on the side wall of the first groove, and the lateral barrier layer located on the side wall of the second groove are simultaneously consumed, so that the openings at the tops of the first through hole and the second through hole formed are slightly enlarged, which is conducive to the filling of the conductive material.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 3 to 13 It is a structural schematic diagram of each step of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0033] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 has a gate structure 201, wherein the substrate 200 on at least one side of the gate structure 201 has a source / drain region I, and an interlayer dielectric layer 202 is formed on the gate structure 201 and the substrate 200.

[0034] In the step of providing the substrate 200 , a front barrier layer 203 is further provided on the substrate 200 and the gate structure 201 , and the interlayer dielectric layer 202 is located on the front barrier layer 203 .

[0035] The material of the substrate 200 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0036] The material of the interlayer dielectric layer 202 is silicon oxide; the material of the front barrier layer 203 is silicon nitride.

[0037] Please refer to Figures 4 to 5 A first groove 204 and a second groove 205 are formed in the interlayer dielectric layer 202, wherein the position of the first groove 204 corresponds to the gate structure 201, and the position of the second groove 205 corresponds to the position of the source and drain region I.

[0038] The position of the first groove 204 corresponds to the gate structure 201 , that is, the projection of the first groove 204 on the surface of the substrate 200 is located within the projection range of the gate structure 201 on the surface of the substrate 200 .

[0039] The position of the second groove 205 corresponds to the position of the source / drain region I, that is, the projection of the second groove 205 on the surface of the substrate 200 is located within the range of the source / drain region I.

[0040] The steps of forming the first groove 204 and the second groove 205 in the interlayer dielectric layer 202 include: Figure 4 As shown, a second mask layer 206 is formed on the interlayer dielectric layer 202, and the second mask layer 206 exposes a portion of the interlayer dielectric layer 202; Figure 5 As shown, the second mask layer 206 (as shown Figure 4 ) is used as a mask, and the interlayer dielectric layer 202 is etched to form the first groove 204 and the second groove 205.

[0041] The step of forming the second mask layer 206 includes: forming a photoresist layer on the interlayer dielectric layer 202 ; exposing and developing the photoresist layer to form the second mask layer 206 .

[0042] In some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 using the second mask layer 206 as a mask to form the first groove 204 and the second groove 205 , the etching is dry etching.

[0043] Specifically, in some embodiments of the present invention, the depth range of the first groove 204 and the second groove 205 is:

[0044] The position of the first groove 204 defines the position of a first conductive plug 213 to be formed subsequently, and the second groove 205 defines the position of a second conductive plug 214 to be formed subsequently.

[0045] Please refer to Figure 6A lateral barrier layer 207 is formed on the sidewalls of the first groove 204 and the sidewalls of the second groove 205 .

[0046] In the step of forming the lateral barrier layer 207 on the sidewalls of the first groove 204 and the second groove 205 , the lateral barrier layer 207 is also formed on the interlayer dielectric layer 202 , the bottom of the first groove 204 and the bottom of the second groove 205 .

[0047] The step of forming a lateral barrier layer 207 on the sidewalls of the first groove 204 and the sidewalls of the second groove 205 includes: forming an initial lateral barrier layer (not shown) on the interlayer dielectric layer 202, the sidewalls of the first groove 204, the bottom of the first groove 204, the sidewalls of the second groove 205 and the bottom of the second groove 205 by chemical vapor deposition; and performing surface nitriding treatment on the initial lateral barrier layer (not shown) to form the lateral barrier layer 207.

[0048] The material of the lateral barrier layer 207 is silicon nitride. Specifically, in some embodiments of the present invention, the thickness of the lateral barrier layer 207 is in the range of: The lateral barrier layer 207 is relatively thin to prevent the critical dimensions of the first through hole 211 and the second through hole 212 formed by etching from being too small due to the lateral barrier layer 207 being too thick.

[0049] The purpose of the nitridation treatment is to improve the compactness of the lateral barrier layer 207, so that the lateral barrier layer 207 is more resistant to etching, thereby ensuring the morphology of the top openings of the first through hole 211 and the second through hole 212 formed by subsequent etching.

[0050] Please refer to Figure 7 A dielectric structure 208 is formed in the first groove 204 and the second groove 205 whose sidewalls have the lateral blocking layer 207 formed therein.

[0051] The step of forming a dielectric structure 208 in the first groove 204 and the second groove 205 with the lateral blocking layer 207 formed on the sidewalls includes: filling the first groove 204 and the second groove 205 with an initial dielectric structure; and flattening the initial dielectric structure until the surface of the initial dielectric structure is flush with the surface of the lateral blocking layer 207 to form the dielectric structure 208.

[0052] The dielectric structure 208 is flush with the surface of the lateral barrier layer 207, thereby providing a flat surface for subsequent formation of photoresist and photolithography on the surfaces of the dielectric structure 208 and the lateral barrier layer 207, thereby improving the alignment accuracy of photolithography and improving the etching accuracy of the first through hole and the second through hole formed by etching.

[0053] The purpose of the planarization process is to obtain a dielectric structure 208 with a flat surface.

[0054] The planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0055] The dielectric structure 208 is made of silicon oxide and can be formed by chemical vapor deposition.

[0056] Please refer to Figures 8 to 11 , forming a first through hole 211 and a second through hole 212 that successively penetrate the dielectric structure 208 and the interlayer dielectric layer 202, wherein the first through hole 211 is located on the gate structure 201, and the second through hole 212 is located on the source and drain region I.

[0057] The steps of forming the first through hole 211 and the second through hole 212 successively penetrating the dielectric structure 208 and the interlayer dielectric layer 202 include: Figure 8 As shown, a first mask layer 210 having an opening 209 is formed on the dielectric structure 208 and the interlayer dielectric layer 202, wherein the opening 209 is located at a corresponding position of the dielectric structure 208 and the opening 209 exposes the surface of the dielectric structure 208; Fig. 9 As shown, the dielectric structure 208 and the interlayer dielectric layer 202 are etched using the first mask layer 210 as a mask until the front barrier layer 203 is exposed; Fig.11 As shown, the exposed front barrier layer 203 is removed to form the first through hole 211 and the second through hole 212 .

[0058] After etching the dielectric structure 208 and the interlayer dielectric layer 202 and before removing the exposed front barrier layer 203, the method further includes: Fig.10 As shown, the first mask layer 210 is removed.

[0059] In the process of removing the exposed front barrier layer 203, the lateral barrier layer 207 located on the interlayer dielectric layer 202, on the sidewalls of the first groove 204, and on the sidewalls of the second groove 205 is removed. The lateral barrier layer 207 located on the sidewalls of the first groove 204 and on the sidewalls of the second groove 205 is removed, so that the top opening sizes of the obtained first through hole 211 and the second through hole 212 are increased, which is conducive to filling the first through hole 211 and the second through hole 212 with conductive materials.

[0060] The steps of forming the first mask layer 210 include: forming a photoresist layer on the dielectric structure 208 and the interlayer dielectric layer 202 ; and exposing and developing the photoresist layer to form the first mask layer 210 .

[0061] In some embodiments of the present invention, in the step of etching the dielectric structure 208 and the interlayer dielectric layer 202 using the first mask layer 210 as a mask, the etching is dry etching.

[0062] The dielectric structure 208 and the interlayer dielectric layer 202 are etched using the first mask layer 210 as a mask until the front barrier layer 203 is exposed. The front barrier layer 203 serves as an etching barrier layer to prevent the gate structure 201 from being etched and lost.

[0063] The material of the front barrier layer 203 is the same as the material of the lateral barrier layer 207. Specifically, in some embodiments of the present invention, the material of the front barrier layer 203 and the material of the lateral barrier layer 207 are silicon nitride.

[0064] The width of the first through hole 211 is smaller than the width of the first groove 204 , and the width of the second through hole 212 is smaller than the width of the second groove 205 .

[0065] The width of the first through hole 211 is the size of the first through hole 211 in a direction from one gate structure 201 to an adjacent structure 201 .

[0066] The width of the second through hole 212 is the size of the second through hole 212 in a direction from one gate structure 201 to an adjacent structure 201 .

[0067] Specifically, in some embodiments of the present invention, the width of the first through hole 211 is smaller than the width of the first groove 204. That is, the projection of the first through hole 211 on the surface of the substrate 200 is located within the projection range of the first groove 204 on the surface of the substrate 200, and the width of the first groove 204 is larger than the width of the first through hole 211, which can effectively control the critical size of the formed first through hole 211.

[0068] Specifically, in some embodiments of the present invention, the width of the second through hole 212 is smaller than the width of the second groove 205. That is, the projection of the second through hole 212 on the surface of the substrate 200 is located within the projection range of the second groove 205 on the surface of the substrate 200, and the width of the second groove 205 is greater than the width of the second through hole 212, which can effectively control the process window of the formed second through hole 212, and is conducive to improving the etching accuracy of the second through hole 212.

[0069] Please refer to Figure 12 to Figure 13 , when forming the first through hole 211 (such as Fig.11 as shown) and the second through hole 212 (as shown Fig.11 After that, a first conductive plug 213 located in the first through hole 211 and a second conductive plug 214 located in the second through hole 212 are formed.

[0070] The steps of forming the first conductive plug 213 in the first through hole 211 and the second conductive plug 214 in the second through hole 212 include: Fig.12 As shown, the first through hole 211 and the second through hole 212 are filled with conductive materials, respectively, to form a conductive material in the first through hole 211 (as shown in FIG. Fig.11 The initial first conductive plug 215 in the second through hole 212 (as shown) and Fig.11 As shown) in the initial second conductive plug 216; Fig.13 As shown, the initial first conductive plug 215, the initial second conductive plug 216 and the interlayer dielectric layer 202 are planarized to form a first through hole 211 (as shown in FIG. Fig.11 ) and the first conductive plug 213 in the second through hole 212 (as shown in FIG. Fig.11 ) within the second conductive plug 214.

[0071] After the initial first conductive plug 215, the initial second conductive plug 216 and the interlayer dielectric layer 202 are planarized to form the first conductive plug 213 in the first through hole 211 and the second conductive plug 214 in the second through hole 212, the thickness of the interlayer dielectric layer 202 is in the range of:

[0072] In the step of forming a first conductive plug 213 in the first through hole 211 and a second conductive plug 214 in the second through hole 212 , the first conductive plug 213 is electrically connected to the gate structure 201 , and the second conductive plug 214 is electrically connected to the source and drain region I.

[0073] The first conductive plug 213 and the second conductive plug 214 include a first conductive layer (not shown), a second conductive layer (not shown) located on the first conductive layer, and a third conductive layer (not shown) located on the second conductive layer. Specifically, in some embodiments of the present invention, the material of the first conductive layer is titanium; the material of the second conductive layer is titanium nitride; and the material of the third conductive layer is tungsten.

[0074] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, which is formed by the above-mentioned method for forming a semiconductor structure, and will not be described in detail herein.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a gate structure, the substrate has a source and drain region on at least one side of the gate structure, and an interlayer dielectric layer is formed on the gate structure and the substrate; forming a first groove and a second groove in the interlayer dielectric layer, wherein the position of the first groove corresponds to the gate structure, and the position of the second groove corresponds to the position of the source and drain region; forming a lateral barrier layer on a sidewall of the first groove and a sidewall of the second groove; forming a dielectric structure in the first groove and the second groove whose sidewalls are formed with the lateral barrier layer; A first through hole and a second through hole are formed to successively penetrate the dielectric structure and the interlayer dielectric layer, wherein the first through hole is located on the gate structure, and the second through hole is located on the source and drain region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The width of the first through hole is smaller than that of the first groove, and the width of the second through hole is smaller than that of the second groove.

3. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a dielectric structure in the first groove and the second groove having the lateral barrier layer formed on the sidewalls comprises: Filling an initial dielectric structure in the first groove and the second groove; The initial dielectric structure is planarized until the surface of the initial dielectric structure is flush with the surface of the lateral barrier layer, thereby forming the dielectric structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the substrate and the gate structure also have a front barrier layer, and the interlayer dielectric layer is located on the front barrier layer; The steps of forming a first through hole and a second through hole successively penetrating the dielectric structure and the interlayer dielectric layer include: forming a first mask layer having openings on the dielectric structure and the interlayer dielectric layer, wherein the openings are located at positions corresponding to the dielectric structure and the openings expose a surface of the dielectric structure; Using the first mask layer as a mask, etching the dielectric structure and the interlayer dielectric layer until the front barrier layer is exposed; The exposed front barrier layer is removed to form the first through hole and the second through hole.

5. The method for forming a semiconductor structure according to claim 4, wherein: After etching the dielectric structure and the interlayer dielectric layer, and before removing the exposed front barrier layer, the first mask layer is removed.

6. The method for forming a semiconductor structure according to claim 4, wherein: In the process of removing the exposed front barrier layer, the lateral barrier layers located on the interlayer dielectric layer, on the sidewalls of the first groove and on the sidewalls of the second groove are removed.

7. The method for forming a semiconductor structure according to claim 1 or 6, wherein: The material of the front barrier layer is the same as that of the lateral barrier layers.

8. The method for forming a semiconductor structure according to claim 4, wherein: The step of forming a first groove and a second groove in the interlayer dielectric layer comprises: forming a second mask layer on the interlayer dielectric layer, wherein the second mask layer exposes a portion of the interlayer dielectric layer; The interlayer dielectric layer is etched using the second mask layer as a mask to form the first groove and the second groove.

9. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming lateral barrier layers on the sidewalls of the first groove and the second groove, the lateral barrier layers are also formed on the interlayer dielectric layer, the bottom of the first groove and the bottom of the second groove.

10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming a lateral barrier layer on the sidewall of the first groove and the sidewall of the second groove comprises: Forming an initial lateral blocking layer on the interlayer dielectric layer, the sidewall of the first groove, the bottom of the first groove, the sidewall of the second groove and the bottom of the second groove by chemical vapor deposition; The initial lateral barrier layer is subjected to a surface nitridation treatment to form the lateral barrier layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the interlayer dielectric layer is silicon oxide; the material of the dielectric structure is silicon oxide; and the material of the lateral blocking layer is silicon nitride.

12. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first through hole and the second through hole, a first conductive plug located in the first through hole and a second conductive plug located in the second through hole are formed.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming a first conductive plug located in the first through hole and a second conductive plug located in the second through hole comprises: Conductive materials are filled in the first through hole and the second through hole respectively to form an initial first conductive plug located in the first through hole and an initial second conductive plug located in the second through hole; the initial first conductive plug, the initial second conductive plug and the interlayer dielectric layer are planarized to form a first conductive plug located in the first through hole and a second conductive plug located in the second through hole.

14. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a first conductive plug in the first through hole and a second conductive plug in the second through hole, the first conductive plug is electrically connected to the gate structure, and the second conductive plug is electrically connected to the source and drain regions.

15. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure as claimed in any one of claims 1 to 14.

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