Semiconductor device

Abstract

The semiconductor device includes a wiring substrate and a semiconductor element. The wiring substrate includes a first signal pad; and a pair of first ground pads spaced apart from the first signal pads and arranged facing each other across the first signal pads in a plan view. The semiconductor element includes a second signal pad; and a pair of second ground pads spaced apart from the second signal pad and arranged facing each other across the second signal pad in plan view. A first bump is formed on the second signal pad, the first bump being electrically connected to the first signal pad via a first bonding portion. A second bump and a third bump disposed closer to the second signal pad side than the second bump are formed on the second ground pad, and at least the second bump is electrically connected to the first ground pad via a second bonding portion. A portion of the second bonding portion is located closer to the first signal pad side than the first ground pad, and an interval between the first signal pad and the second bonding portion is narrower than an interval between the first signal pad and the first ground pad in plan view.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device that processes high frequencies such as millimeter waves. In such a semiconductor device, for example, a semiconductor element is mounted on a wiring substrate having a wiring pattern formed thereon. The wiring pattern and the semiconductor element are electrically connected, for example, via bumps (see, for example, Patent Document 1).

[0003] <Prior Art Literature>

[0004] <Patent Documents>

[0005] Patent Document 1: Japanese Patent Application Publication No. 2001-230343 Summary of the invention

[0006] <Problems to be Solved by the Invention>

[0007] In a semiconductor device that handles high frequencies such as described above, it is preferable to arrange a wiring pattern in a wiring substrate so that transmission loss of a signal is unlikely to occur.

[0008] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of reducing signal transmission loss.

[0009] <Methods used to solve the problem>

[0010] The semiconductor device includes: a wiring substrate; and a semiconductor element mounted on the wiring substrate, wherein the wiring substrate includes a first signal pad on a side opposite to the semiconductor element; and a pair of first ground pads separated from the first signal pad and arranged opposite to each other with the first signal pad interposed therebetween in a plan view, the semiconductor element includes a second signal pad on a side opposite to the wiring substrate; and a pair of second ground pads separated from the second signal pad and arranged opposite to each other with the second signal pad interposed therebetween in a plan view, a first bump is formed on the second signal pad, the first bump is electrically connected to the first signal pad via a first bonding portion, a second bump is formed on each of the second ground pads, and a third bump is arranged closer to the second signal pad than the second bump, at least the second bump is electrically connected to each of the first ground pads via a second bonding portion, a portion of the second bonding portion is located closer to the first signal pad than each of the first ground pads, and a distance between the first signal pad and the second bonding portion is narrower than a distance between the first signal pad and each of the first ground pads in a plan view.

[0011] <Effects of the Invention>

[0012] According to the disclosed technology, it is possible to provide a semiconductor device capable of reducing signal transmission loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 FIG. 1 is a diagram schematically showing a semiconductor device according to a first embodiment.

[0014] Figure 2 is a cross-sectional view exemplarily showing a semiconductor device according to a comparative example.

[0015] Figure 3 FIG. 1 is a diagram schematically showing a semiconductor device according to Modification 1 of the first embodiment.

[0016] Figure 4 : is a cross-sectional view schematically showing a semiconductor device according to a second modification of the first embodiment.

[0017] Figure 5 : is a cross-sectional view schematically showing a semiconductor device according to Modification 3 of the first embodiment.

[0018] Explanation of symbols

[0019] 1, 1A, 1B, 1C Semiconductor devices

[0020] 10 Wiring substrate

[0021] 11.13 Insulation layer

[0022] 12, 14 wiring layer

[0023] 20 Semiconductor components

[0024] 21 Semiconductor substrate

[0025] 22 Wiring Layer

[0026] 30 Bump

[0027] 40 Joint

[0028] 50 Underfill resin

[0029] 141a First signal pad

[0030] 141b First wiring pattern

[0031] 142a First ground pad

[0032] 142b Second wiring pattern

[0033] 221a Second signal pad

[0034] 221b Third wiring pattern

[0035] 222a Second ground pad

[0036] 222b Fourth wiring pattern

[0037] 301 First Bump

[0038] 302a Second bump

[0039] 302b Third bump

[0040] 302c Wide section

[0041] 302d Narrow Width

[0042] 401 First joint

[0043] 402 second joint

[0044] 402a Part I

[0045] 402b Part 2 DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that in each of the drawings, the same components are denoted by the same reference numerals, and overlapping descriptions may be omitted.

[0047] <First Embodiment>

[0048] Figure 1 FIG. 1 is a diagram schematically showing a semiconductor device according to a first embodiment. Figure 1 (a) is a cross-sectional view. Figure 1 (b) is a bottom view showing the side of the semiconductor element 20 that is opposite to the wiring substrate 10 , and mainly shows the wiring layer 22 . Figure 1 (c) is a plan view showing the side of the wiring substrate 10 that is opposite to the semiconductor element 20 , and mainly shows the wiring layer 14 .

[0049] Reference Figure 1 , the semiconductor device 1 includes a wiring substrate 10 , a semiconductor element 20 , a bump 30 , a bonding portion 40 , and an underfill resin 50 .

[0050] It should be noted that, in this embodiment, for convenience, Figure 1The semiconductor element 20 side is set as the upper side or one side, and the wiring substrate 10 side is set as the lower side or the other side. In addition, the surface of the semiconductor element 20 side of each part is set as one surface or the upper surface, and the surface of the wiring substrate 10 side is set as the other surface or the lower surface. However, the semiconductor device 1 can be used in an upside-down state, or can be arranged at any angle. In addition, the top view refers to observing the object from the normal direction of the upper surface of the semiconductor element 20, and the planar shape refers to the shape of the object observed from the normal direction of the upper surface of the semiconductor element 20.

[0051] Wiring substrate 10 includes insulating layer 11 , wiring layer 12 , insulating layer 13 , and wiring layer 14 .

[0052] As the material of the insulating layer 11, for example, non-photosensitive (thermosetting resin) epoxy-based insulating resin or polyimide-based insulating resin can be used. As the material of the insulating layer 11, for example, photosensitive epoxy-based insulating resin or acrylic-based insulating resin can also be used. The thickness of the insulating layer 11 can be, for example, about 20 to 40 μm. The insulating layer 11 can contain silicon dioxide (SiO 2 ) and other fillers.

[0053] The wiring layer 12 is formed on the insulating layer 11. As a material of the wiring layer 12, copper or the like can be used, for example. The thickness of the wiring layer 12 can be, for example, about 10 to 20 μm.

[0054] The insulating layer 13 is formed on the insulating layer 11 so as to cover the upper surface and the side surfaces of the wiring layer 12. The material of the insulating layer 13 may be the same as that of the insulating layer 11. The thickness of the insulating layer 13 may be about 20 to 40 μm, for example. The insulating layer 13 may contain silicon dioxide (SiO 2 ) and other fillers.

[0055] The wiring layer 14 is formed on the insulating layer 13. The wiring layer 14 is configured to include through-hole wiring filled in a through-hole that penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12, and a pad and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the through-hole. The thickness of the wiring pattern constituting the wiring layer 14 can be, for example, about 10 to 20 μm.

[0056] The semiconductor element 20 is mounted on the wiring substrate 10. The semiconductor element 20 is, for example, an element that processes a high-frequency signal in the terahertz frequency band, the submillimeter wave frequency band, or the millimeter wave frequency band or higher.

[0057] The semiconductor element 20 includes a semiconductor substrate 21 and a wiring layer 22. The semiconductor substrate 21 is a substrate made of, for example, silicon, GaAs, GaN, etc. The wiring layer 22 is formed on the lower surface side of the semiconductor substrate 21. The wiring layer 22 is configured to include a pad and a wiring pattern.

[0058] The bumps 30 are formed on the pads of the wiring layer 22. The bumps 30 are electrically connected to the corresponding pads of the wiring layer 14 via the bonding portion 40. An underfill resin 50 is filled between the semiconductor substrate 21 and the upper surface of the wiring substrate 10.

[0059] Here, the wiring layer 14 of the wiring substrate 10 and the wiring layer 22 of the semiconductor element 20 will be described in further detail.

[0060] like Figure 1 As shown in (c), the wiring layer 14 includes a first signal pad 141a and a first wiring pattern 141b extending from the first signal pad 141a. In addition, the wiring layer 14 includes a pair of first ground pads 142a and a second wiring pattern 142b extending from each of the first ground pads 142a. The pair of first ground pads 142a are separated from the first signal pad 141a and are arranged opposite to each other across the first signal pad 141a in a plan view.

[0061] The pair of second wiring patterns 142b are separated from the first wiring pattern 141b and arranged opposite to each other via the first wiring pattern 141b in a plan view. The first wiring pattern 141b and the pair of second wiring patterns 142b form a GSG (Grand / Signal / Grand) structure. The high-frequency signal from the semiconductor element 20 flows through the first wiring pattern 141b.

[0062] It should be noted that in Figure 1 In (c), for convenience, the positions of the first bump 301 , the second bump 302 a , the third bump 302 b , the first bonding portion 401 , and the second bonding portion 402 described later are indicated by dotted lines together with the wiring layer 14 .

[0063] like Figure 1 As shown in (b), the wiring layer 22 includes a second signal pad 221a and a third wiring pattern 221b extending from the second signal pad 221a. In addition, the wiring layer 22 includes a pair of second ground pads 222a and a fourth wiring pattern 222b extending from each second ground pad 222a. The pair of second ground pads 222a are separated from the second signal pad 221a and arranged opposite to each other across the second signal pad 221a in a plan view. The pair of fourth wiring patterns 222b are separated from the third wiring pattern 221b and arranged opposite to each other across the third wiring pattern 221b in a plan view.

[0064] like Figure 1 As shown in (b), the bump 30 includes a first bump 301, a second bump 302a, and a third bump 302b. Figure 1 As shown in (c), the joint portion 40 includes a first joint portion 401 and a second joint portion 402 .

[0065] A first bump 301 is formed on the second signal pad 221a, and the first bump 301 is electrically connected to the first signal pad 141a via the first joint 401. In addition, a second bump 302a and a third bump 302b arranged closer to the second signal pad 221a than the second bump 302a are formed on each second ground pad 222a, and at least the second bump 302a is electrically connected to each first ground pad 142a via the second joint 402.

[0066] It should be noted that the electrical connection between the first grounding pad 142a and the second grounding pad 222a can be reliably achieved through the second bump 302a and the second joint 402. Therefore, the third bump 302b may be connected to the second joint 402, or may not be connected to the second joint 402. In other words, among the second bump 302a and the third bump 302b, as long as at least the second bump 302a is electrically connected to the first grounding pad 142a via the second joint 402. However, the second joint 402 needs to be connected to the first grounding pad 142a.

[0067] The first bump 301, the second bump 302a and the third bump 302b are, for example, metal columns. As metal columns, for example, copper columns can be cited. The first bump 301, the second bump 302a and the third bump 302b are, for example, columnar. In the present embodiment, the first bump 301, the second bump 302a and the third bump 302b are cylindrical. The diameter of the first bump 301 is equal to the diameter of the second bump 302a. In addition, the diameter of the third bump 302b is smaller than the diameter of the second bump 302a. In this way, by making the diameter of the third bump 302b smaller than the diameter of the second bump 302a, even if the second grounding pad 222a has a small area, two bumps can be arranged.

[0068] For example, solder can be used as a material of the first bonding portion 401 and the second bonding portion 402. Examples of the material of the solder include alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Bi, alloys of Sn and Ag, and alloys of Sn, Ag, and Cu.

[0069] A portion of the second bonding portion 402 is located closer to the first signal pad 141a than the first ground pad 142a. In addition, in a plan view, the interval P2 between the first signal pad 141a and the second bonding portion 402 is narrower than the interval P1 between the first signal pad 141a and the first ground pad 142a. The interval P1 may be, for example, about 50 μm, and the interval P2 may be, for example, about 30 μm.

[0070] Figure 2 1 is a cross-sectional view schematically showing a semiconductor device according to a comparative example. In the semiconductor device 1X, each pad of the wiring layer 22 and each pad of the wiring layer 14 are connected via one bump 30. In addition, the bonding portion 40 does not protrude from each pad of the wiring layer 14, and the interval between adjacent pads constituting the wiring layer 14 is P1.

[0071] Since the high-frequency signal flows through the wiring layer 14, the narrower the interval P1, the better. The narrower the interval P1, the lower the transmission loss of the high-frequency signal. However, since the shortest value of the interval P1 is determined by the design rules of the wiring substrate 10, it cannot be narrower than it. It should be noted that the design rules of the wiring substrate 10 are determined by the material of the wiring substrate 10 and the process of forming the wiring layer 14.

[0072] On the other hand, since the wiring layer 22 of the semiconductor element 20 is formed by a semiconductor process, fine wiring can be formed, and the interval between the second signal pad 221a and the second ground pad 222a can be narrower than the interval P1. Figure 1 As shown, in the semiconductor device 1, in a plan view, the interval between the second signal pad 221a and the second ground pad 222a is narrower than the interval P1 between the first signal pad 141a and the first ground pad 142a, and two bumps (a second bump 302a and a third bump 302b) are arranged on each second ground pad 222a.

[0073] Thus, the lower end of the third bump 302b can be brought closer to the first signal pad 141a, and the second bonding portion 402 provided near the lower end of the third bump 302b can be made to protrude from the first ground pad 142a toward the first signal pad 141a. Thus, the interval P2 can be made narrower than the interval P1. That is, in the semiconductor device 1, the same effect as in the case of reducing the interval P1 can be obtained. Figure 2 Compared with the semiconductor device 1X shown in the figure, the transmission loss of the high frequency signal can be reduced. Therefore, the antenna characteristics can be improved.

[0074] Preferably, part or all of the third bump 302b protrudes from the first ground pad 142a toward the first signal pad 141a in plan view. This makes it easier for the second bonding portion 402 provided near the lower end of the third bump 302b to protrude from the first ground pad 142a toward the first signal pad 141a.

[0075] (Variation of the first embodiment>

[0076] In the modification of the first embodiment, an example in which the shape of the bump or the engaging portion is different is shown. In the modification of the first embodiment, the description of the same components as those of the embodiment already described may be omitted.

[0077] Figure 3 FIG. 2 is a diagram schematically showing a semiconductor device according to a first modification of the first embodiment. Figure 3 In the semiconductor device 1A shown, the second joint portion 402 includes a first portion 402a connected to the second bump 302a and a second portion 402b connected to the third bump 302b. The first portion 402a and the second portion 402b are separated from each other and do not contact each other. In this way, the second joint portion 402 can also be divided into a plurality of separated portions.

[0078] It should be noted that the electrical connection between the first grounding pad 142a and the second grounding pad 222a can be reliably achieved through the second bump 302a and the first portion 402a. Therefore, the third bump 302b may not be connected to the second portion 402b. However, the second portion 402b needs to be connected to the first grounding pad 142a.

[0079] Figure 4 FIG. 4 is a cross-sectional view schematically showing a semiconductor device according to a second modification of the first embodiment. Figure 4 In the semiconductor device 1B shown, each bump 30 has a sharp tip and includes a wide portion 302c located on the semiconductor element 20 side and a narrow portion 302d protruding from the wide portion 302c toward the wiring substrate 10. In this way, each bump 30 may have a shape other than a cylindrical shape.

[0080] Figure 4The bump 30 of the shape shown can be formed on each pad constituting the wiring layer 22 by, for example, a wire bump method using a metal wire such as gold. Specifically, for example, a metal wire of a predetermined length is drawn out from a capillary of a wiring machine, and the top end of the metal wire is rounded into a spherical shape by discharge, and then the capillary is lowered so that the top spherical part of the metal wire contacts the pad, and is bonded to the pad by heating and ultrasonic vibration. Next, the metal wire is pulled apart by fixing the metal wire with pliers while pulling up the capillary. Thus, a bump 30 with a sharp tip electrically connected to the pad is formed.

[0081] By making the top end of the bump 30 sharp, the amount of protrusion of the bump 30 on the second bonding portion 402 is suppressed, thereby reducing the possibility of a short circuit between the first signal pad 141a and the second bonding portion 402.

[0082] Figure 5 FIG. 4 is a cross-sectional view schematically showing a semiconductor device according to a third modification of the first embodiment. Figure 5 In the semiconductor device 1C shown, each bump 30 is cylindrical and has the same diameter. If the second ground pad 222a has a large area, each bump 30 can have a single shape. In this case, there is no need to prepare multiple types of bumps 30, which is advantageous in terms of manufacturing.

[0083] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions may be made to the above embodiments without departing from the scope of the claims.

Claims

1. A semiconductor device comprising: Wiring substrate; as well as A semiconductor element is mounted on the wiring substrate. in, The wiring substrate has a A first signal pad; as well as a pair of first ground pads, separated from the first signal pads and arranged opposite to each other across the first signal pads in a plan view, The semiconductor element has a a second signal pad; and a pair of second ground pads, separated from the second signal pads and arranged opposite to each other across the second signal pads in a plan view, A first bump is formed on the second signal pad, and the first bump is electrically connected to the first signal pad via a first bonding portion. A second bump and a third bump arranged at a position closer to the second signal pad than the second bump are formed on each of the second ground pads, and at least the second bump is electrically connected to each of the first ground pads via a second bonding portion. A portion of the second bonding portion is located closer to the first signal pad than each of the first ground pads. In a plan view, a distance between the first signal pad and the second bonding portion is narrower than a distance between the first signal pad and each of the first ground pads.

2. The semiconductor device according to claim 1, wherein The second bump and the third bump are cylindrical, The diameter of the third bump is smaller than the diameter of the second bump.

3. The semiconductor device according to claim 1, wherein The first bump, the second bump and the third bump are cylindrical, The diameters of the first bump, the second bump and the third bump are equal.

4. The semiconductor device according to claim 1, wherein The first bump, the second bump, and the third bump include a wide portion located on the semiconductor element side and a narrow portion protruding from the wide portion toward the wiring substrate side.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The second engaging portion includes a first portion connected to the second bump and a second portion connected to the third bump. The first portion and the second portion are separated from each other.

6. The semiconductor device according to any one of claims 1 to 4, wherein: Part or all of the third bumps protrude from above each of the first ground pads toward the first signal pads in a plan view.

7. The semiconductor device according to any one of claims 1 to 4, wherein: In a plan view, a distance between the second signal pad and each of the second ground pads is narrower than a distance between the first signal pad and each of the first ground pads.

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